US20060118457A1 - Film carrier tape for mounting electronic component - Google Patents

Film carrier tape for mounting electronic component Download PDF

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Publication number
US20060118457A1
US20060118457A1 US10/534,190 US53419005A US2006118457A1 US 20060118457 A1 US20060118457 A1 US 20060118457A1 US 53419005 A US53419005 A US 53419005A US 2006118457 A1 US2006118457 A1 US 2006118457A1
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United States
Prior art keywords
film carrier
solder resist
electronic part
resist layer
carrier tape
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Abandoned
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US10/534,190
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English (en)
Inventor
Shuichi Kawasaki
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Mitsui Mining and Smelting Co Ltd
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Individual
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Filing date
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Assigned to MITSUI MINING & SMELTING CO., LTD. reassignment MITSUI MINING & SMELTING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KAWASAKI, SHUICHI
Publication of US20060118457A1 publication Critical patent/US20060118457A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Definitions

  • the present invention relates to film carrier tapes for mounting electronic parts which are reduced in warpage distortion. More particularly, the present invention relates to film carrier tapes for mounting electronic parts, which have film carriers each having substantially the same size as that of an electronic part to be mounted, such as COF (chip on film), CSP (chip size package) and BGA (ball grid array), in which two or more film carriers are arranged on a tape of a long insulating film side by side in the width direction of the tape, and which are remarkably reduced in warpage distortion.
  • COF chip on film
  • CSP chip size package
  • BGA ball grid array
  • film carrier tapes for mounting electronic part are employed.
  • the film carrier tapes for mounting electronic part are produced by forming a wiring pattern made of a conductive metal on a surface of a long insulating film, and most of the film carrier tapes are produced by further forming a solder resist layer on a surface of the wiring pattern except a terminal portion.
  • thermosetting resins such as epoxy resins are employed for forming the solder resist layer.
  • thermosetting resins for forming the solder resist layer have properties that they slightly suffer cure shrinkage when they are cured by heating, and in the film carrier tapes for mounting electronic part having such a solder resist layer, warpage distortion in the width direction or the lengthwise direction is brought about by the cure shrinkage of the thermosetting resin for forming the solder resist layer.
  • the warpage distortion in the width direction or the lengthwise direction of the long film carrier tape can be corrected by, for example, passing the film carrier tape through a large number of rolls under heating or heating the film carrier tape with bending the tape in the opposite direction to the direction of the warpage distortion (i.e., with giving reverse warpage).
  • Such a warpage-removal method is particularly effective for removing warpage of a film carrier tape in which one wiring pattern is formed in the width direction of a tape made of an insulating film.
  • film carriers each having an area substantially the same as that of an electronic part to be mounted, such as COF (chip on film), CSP (chip size package) and BGA (ball grid array), came to be used more frequently. Because such a film carrier occupies a small area, plural film carriers (e.g., 2 or 4 film carriers) can be arranged side by side in the width direction of a tape made of an insulating film in the production of a film carrier tape.
  • COF chip on film
  • CSP chip size package
  • BGA ball grid array
  • Patent document 1 Japanese Patent Application No. 249499/2001
  • the film carrier tape for mounting electronic part of the present invention is a film carrier tape comprising a long insulating film and a large number of wiring patterns formed on a surface of the insulating film, said wiring patterns being made of a conductive metal, wherein:
  • the wiring patterns are each independently covered with a solder resist layer except a connecting terminal portion, and the solder resist layer formed on each surface of the wiring patterns is split and/or divided into plural sections.
  • the film carrier tape for mounting electronic part of the present invention is also a film carrier tape comprising a long insulating film and a large number of wiring patterns formed on a surface of the insulating film, said wiring patterns being made of a conductive metal and at least two of said wiring patterns being arranged side by side in the width direction of the long insulating film, wherein:
  • the wiring patterns are each independently covered with a solder resist layer except a connecting terminal portion, and the solder resist layer formed on each surface of the wiring patterns is split and/or divided into plural sections.
  • the solder resist layer is formed by dividing and applying a solder resist, and in each of the divided sections of the solder resist layer, the stress attributable to cure shrinkage is small. Therefore, distortion of the film carrier can be reduced.
  • FIG. 1 is a plan view showing an example of a film carrier tape for mounting electronic part of the present invention.
  • FIG. 2 is a cross sectional view taken on line A-A′ of FIG. 1 .
  • FIG. 4 is a group of views showing a method of measuring warpage distortion of a film carrier in the present invention.
  • FIG. 5 is a group of views each showing an example of a film carrier tape for mounting electronic part of the present invention wherein a solder resist layer is formed in a region of not less than 20% of the wiring patterns except terminal portions.
  • FIG. 6 is a group of cross sectional views showing examples of divided sections of a solder resist layer.
  • FIG. 1 is a plan view showing an example of the film carrier tape for mounting electronic part of the present invention
  • FIG. 2 is a cross sectional view taken on line A-A′ of FIG. 1 .
  • the film carrier tape 10 for mounting electronic part of the present invention comprises a long insulating film 11 and a large number of film carriers 12 formed on a surface of the insulating film.
  • polyimide resins examples include aromatic polyimides synthesized from pyromellitic dianhydride and aromatic diamines and aromatic polyimides having biphenyl skeleton synthesized from biphenyltetracarboxylic dianhydride and aromatic diamines. Particularly in the present invention, it is preferable to use aromatic polyimides having biphenyl skeleton (e.g., Upilex S, trade name, available from Ube industries, Ltd.). The aromatic polyimides having biphenyl skeleton have lower water absorption than other aromatic polyimides.
  • the thickness of the insulating film employable in the present invention is not specifically restricted.
  • An insulating film having a thickness of not more than 75 ⁇ m tends to be lowered in the retention of shape and is liable to be distorted, so that the present invention is very useful for producing a thin film carrier using an insulating film having a thickness (average thickness) of not more 75 ⁇ m, preferably 50 to 12.5 ⁇ m.
  • a large number of sprocket holes 14 are formed in order to carry the insulating film 11 or to make positioning.
  • positioning holes, device holes, solder ball holes for arranging solder balls used as outer terminals, and slits for ensuring connection to electronic parts may be further formed. These can be formed in a punching step or a perforation step using laser beam.
  • the copper foil employable herein is an electrodeposited copper foil or a rolled copper foil. Taking etchability and operability into account, it is preferable to use an electrodeposited copper foil.
  • plural film carriers 12 are arranged independently from one another in the width direction of the tape.
  • the insulating film 11 having an effective width of 35 mm two film carriers each having a side length of 14 mm can be arranged side by side in the width direction, and on the insulating film 11 having an effective width of 70 mm, four film carriers each having a side length of 14 mm can be arranged side by side in the width direction.
  • the surface of the wiring pattern 15 formed on the insulating film 11 is applied with a solder resist ink except a terminal portion 16 that ensures connection to an electronic part, whereby a solder resist layer 20 is formed.
  • the resin applied to form the solder resist layer 20 is usually a coating liquid (solder resist ink) in which a thermosetting resin is dissolved or dispersed in an organic solvent. By applying such a solder resist ink and then heating it, the solder resist layer 20 is formed.
  • the resin of the solder resist layer 20 slightly suffers cure shrinkage, and as a result, warpage distortion in a state such that the solder resist layer 20 being inner side takes place in a region where the solder resist ink is applied.
  • Some film carrier tapes for mounting electronic part do not need formation of a solder resist layer.
  • the solder resist layer 20 which has been formed in one united body by coating the whole surface in the conventional technique, is formed by splitting or dividing the region to be coated into several sections and then coating them, and the stress in each of the split or divided sections is made as small as possible.
  • the stress is suppressed to such a level as comparable to a strength of shape retention of the insulating film 11 present under the thus divided solder resist layer 20 to thereby hold down the warpage distortion of the divided solder resist layer 20 formed area to the minimum.
  • the resin for forming the solder resist layer 20 is a curing resin
  • the curing resins preferably used include thermosetting resins, such as epoxy resins, urethane modified epoxy resins, phenolic resins and polyimide resin precursors.
  • thermosetting resins such as epoxy resins, urethane modified epoxy resins, phenolic resins and polyimide resin precursors.
  • Such a thermosetting resin is dissolved or dispersed in a solvent, and the solution or the dispersion is adjusted to have a viscosity of usually 10 to 40 Pa ⁇ s, preferably 20 to 30 Pa ⁇ s, so as to enable squeegee coating using a screen mask.
  • the region to be coated with a solder resist is divided into plural sections, and these sections are applied with the solder resist. That is to say, the region to be coated with the solder resist is a joined area of the A section 20 a , the B section 20 b , the C section 20 c and the D section 20 d in FIGS. 1 and 3 , however in the embodiment shown in FIGS. 1 and 3 , this region is divided into 4 sections, then these sections are each applied with the solder resist independently from the adjacent sections, and the solder resist is cured to form a solder resist layer 20 having been divided into 4 sections.
  • the solder resist layer 20 is preferably divided into 2 to 16 sections, particularly preferably 2 to 8 sections, though it depends upon the size of the film carrier and the properties of the insulating film, the solder resist and other materials.
  • shrinkage stress attributable to curing of the solder resist in each section is reduced, and the distortion of the whole film carrier is also reduced.
  • the size of the solder resist after dividing the length of one side does not necessarily have to be less than 5 mm because the properties of the insulating film, the solder resist and the like are entangled.
  • the shape and the relative size of each of the split and/or divided sections of the solder resist layer 20 are not specifically restricted, however it is preferable to divide the region to be covered with the solder resist as equally as possible. By uniformalizing the stress produced in each section, the distortion of the whole film carrier can be further reduced. That is to say, it is preferable that the areas of the sections are equalized to one another and the shapes of the sections are made substantially the same as one another.
  • the length of one side of each section of the divided solder resist is desired to be in the range of about 2 to 10 mm, preferably about 2.5 to 7.5 mm.
  • the film carrier formed by splitting and/or dividing the solder resist layer is not limited to the aforesaid CSP or BGA, and the film carrier can be applied to general TAB tapes.
  • the film carrier can be applied to a film carrier tape for mounting electronic part wherein a solder resist layer is formed in a region of not less than 30% of the wiring patterns (except terminal portions).
  • FIG. 5 ( a ) an example wherein a solder resist layer having been divided into 12 sections is formed on wiring patterns 15 formed on a surface of an insulating film 11 having a device hole is shown.
  • a distance (W) between the divided sections can be properly determined so as not to transmit the stress produced in one section to its adjacent section, and the distance is in the range of usually 20 ⁇ m to 50 mm, preferably 20 ⁇ m to 3 mm.
  • the distance between the sections is determined in the above range, the internal stress produced in one section is not transmitted to the adjacent section, and besides there is no problem in the protection of a wiring pattern in each section. It is desirable that the shapes of the sections closely resemble one another. When the shapes of the sections closely resemble one another, the internal stress produced in each section is uniformalized, and hence, the distortion of the whole film carrier is reduced.
  • the thickness (h 0 ) of the solder resist layer split or divided as above is the same as that of a conventional solder resist layer, and the solder resist layer on the upper surface of the wiring pattern has an average thickness of usually 3 to 50 ⁇ m, preferably 5 to 40 ⁇ m, after curing.
  • the solder resist layer 20 is split or divided as shown in FIG. 6 ( a ), and between the adjacent sections, there is an area where no solder resist layer is formed as above.
  • the internal stress produced in one section has only to be not transmitted to the adjacent section, so that the section of the solder resist layer 20 may be connected to its adjacent section at least in part, as shown in 6 ( b ).
  • the thickness (h 1 ) of the solder resist layer between these sections is not more than 1 ⁇ 2 of the usual thickness (h 0 ) of the solder resist layer, and h 1 may be 0.
  • the divided solder resist layer 20 In order to form the divided solder resist layer 20 , masking is made on a conventional screen correspondingly to the sections, and the resin has only to be applied. In case of a solder resist of adhesion type which has begun to be adopted recently, a gap is formed, and then the solder resist has only to be allowed to adhere. In case of a solder resist using a photosensitive resin, the resin is applied, and then the resin has only to be exposed and developed so as to split and/or divide the solder resist layer.
  • the solder resist layer whose divided sections are connected to one another at least in part can be formed by controlling a line width of a screen mask that is used when a solder resist coating liquid is applied.
  • a surface of a terminal portion 16 (e.g., lead, bonding pad) exposed from the solder resist layer 20 is subjected to plating treatment.
  • plating treatments include tin plating, nickel plating, nickel-gold multilayer plating, nickel-palladium-gold multilayer plating, solder plating and tin-bismuth plating.
  • the above-mentioned plated layer is formed on the surface of the wiring pattern present between the divided sections of the solder resist layer.
  • the plating treatment may be carried out prior to the formation of the solder resist layer.
  • the film carrier tape for mounting electronic part of the present invention produced as above can be used in a usual manner.
  • an electronic part (not shown in the figures) is arranged by the use of an adhesive or the like, and electrical connection is made between the connecting terminal 16 and a bump electrode provided on the electronic part, whereby mounting of the electronic part can be achieved.
  • a conductive metal wire such as a gold wire can be employed.
  • the film carrier has an area substantially the same as an area of the electronic part to be mounted, but the present invention is not limited to such a film carrier tape.
  • the connecting terminal 16 of the film carrier tape for mounting electronic part of the present invention is connected to a solder ball through the wiring pattern 15 .
  • the solder resist layer is split or divided as described above, and therefore, warpage distortion of a film carrier attributable to the cure shrinkage of the solder resist occurring in the curing can be reduced.
  • Distortion of the film carrier in the film carrier tape for mounting electronic part of the present invention is measured in the following manner. As shown in FIG. 4 ( a ), a point of the film carrier tape, at which a sprocket hole to carry the film carrier tape is formed, is taken as a standard point. Then, with regard to one film carrier of the film carrier tape produced, heights of measuring points ⁇ circle around (1) ⁇ to ⁇ circle around (5) ⁇ based on the standard point are measured.
  • warpage distortion of a film carrier is reduced to not more than 50% of warpage distortion of a film carrier having no split or divided solder resist layer.
  • the solder resist layer is formed in such a manner that the layer is split or divided, whereby warpage distortion of a film carrier is reduced, and the film carrier tape for mounting electronic part exhibits high reliability.
  • the film carrier tape for mounting electronic part of the present invention is further described with reference to the following example by comparing it with a film carrier tape which has a solder resist layer formed on the whole surface of a wiring pattern except a connecting terminal and which is liable to suffer warpage.
  • the present invention is in no way limited to the example.
  • a polyimide film (trade name: Upilex S, available from Ube industries, Ltd.) having an average thickness of 50 ⁇ m and a width of 48 mm was punched to form sprocket holes and solder ball holes for arranging solder balls. As shown in FIG. 1 , the solder ball holes were formed so that film carriers each having a side length of 17 mm could be arranged in two rows.
  • an electrodeposited copper foil having an average thickness of 25 ⁇ m was applied onto the polyimide film, then the electrodeposited copper foil was applied with a photosensitive resin, and the photosensitive resin was exposed and developed. Using a pattern made of the thus developed photosensitive resin as a masking material, the electrodeposited copper foil was selectively etched to form a wiring pattern made of copper.
  • solder resist ink Onto a surface of the wiring pattern thus formed, a solder resist ink was applied, and the solder resist ink was cured by heating to form a solder resist layer (average thickness after curing: 10 ⁇ m).
  • the solder resist layer formed herein was a layer having been divided into 4 sections by providing a mask on a screen and having between the adjacent sections an area coated with no solder resist in a width of 200 ⁇ m (non-solder resist area), as shown in FIG. 1 .
  • solder resist layer consisting of divided 4 sections
  • a connecting terminal coated with no solder resist layer and the non-solder resist area were subjected to nickel plating and then gold plating. Thereafter, the whole film carrier tape was subjected to removal of warpage in a conventional manner.
  • a film carrier tape for mounting electronic part was produced in the same manner as in Example 1, except that the solder resist layer was not divided.
  • the solder resist layer is split or divided into plural sections, so that a stress that is brought with shrinkage occurring in the curing of the solder resist ink is scattered.
  • warpage distortion of a film carrier attributable to the cure shrinkage of the solder resist layer is remarkably reduced, and precision in the mounting of electronic part is surely enhanced.
  • the film carrier tape for mounting electronic part of the present invention is particularly useful as CSP, COF, BGA or the like.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
US10/534,190 2002-11-07 2003-10-09 Film carrier tape for mounting electronic component Abandoned US20060118457A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002324445A JP3914135B2 (ja) 2002-11-07 2002-11-07 電子部品実装用フィルムキャリアテープ
JP2002-32445 2002-11-07
PCT/JP2003/012972 WO2004042814A1 (ja) 2002-11-07 2003-10-09 電子部品実装用フィルムキャリアテープ

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US10/534,190 Abandoned US20060118457A1 (en) 2002-11-07 2003-10-09 Film carrier tape for mounting electronic component

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US (1) US20060118457A1 (ja)
JP (1) JP3914135B2 (ja)
KR (1) KR100713509B1 (ja)
CN (1) CN100377325C (ja)
TW (1) TWI284106B (ja)
WO (1) WO2004042814A1 (ja)

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US20110259772A1 (en) * 2008-09-25 2011-10-27 Illinois Tool Works Inc. Devices and method for handling microelectronics assemblies
TWI412818B (zh) * 2009-09-15 2013-10-21 Chunghwa Picture Tubes Ltd 液晶顯示面板及其走線結構
CN105552048A (zh) * 2016-01-28 2016-05-04 珠海格力节能环保制冷技术研究中心有限公司 导热焊盘及具有其的qfp芯片的封装结构

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CN102543765B (zh) * 2012-01-13 2014-12-10 迈普通信技术股份有限公司 一种贴片元器件焊盘设计方法、焊盘结构及印刷电路板
CN105451458B (zh) * 2014-08-19 2018-10-30 宁波舜宇光电信息有限公司 一种控制软硬结合板微量变形的方法及pcb基板半成品
CN105611722A (zh) * 2016-03-21 2016-05-25 安捷利电子科技（苏州）有限公司 一种mems产品的印制电路板
CN109714896B (zh) * 2018-11-23 2021-03-19 广州广合科技股份有限公司 一种改善多层印制电路大拼板内套板局部形变的方法
CN110351959A (zh) * 2019-07-17 2019-10-18 高德(苏州)电子有限公司 改善不对称压合线路板板翘的方法以及控制结构

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KR20050053790A (ko) 2005-06-08
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CN100377325C (zh) 2008-03-26
TW200407248A (en) 2004-05-16
TWI284106B (en) 2007-07-21
KR100713509B1 (ko) 2007-04-30
CN1708841A (zh) 2005-12-14
WO2004042814A1 (ja) 2004-05-21

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