US20060000637A1 - Printed circuit board and method for manufacturing printed circuit board - Google Patents

Printed circuit board and method for manufacturing printed circuit board Download PDF

Info

Publication number
US20060000637A1
US20060000637A1 US11/173,126 US17312605A US2006000637A1 US 20060000637 A1 US20060000637 A1 US 20060000637A1 US 17312605 A US17312605 A US 17312605A US 2006000637 A1 US2006000637 A1 US 2006000637A1
Authority
US
United States
Prior art keywords
thin copper
copper film
film
printed circuit
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/173,126
Other languages
English (en)
Inventor
Kei Nakamura
Takeshi Yamato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Assigned to NITTO DENKO CORPORATION reassignment NITTO DENKO CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NAKAMURA, KEI, YAMATO, TAKESHI
Publication of US20060000637A1 publication Critical patent/US20060000637A1/en
Priority to US11/955,432 priority Critical patent/US8092696B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0393Flexible materials
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Definitions

  • the present invention relates to printed circuit boards and a method for manufacturing such printed circuit boards.
  • a printed circuit board such as flexible printed circuit boards are widely used in a variety of electrical and electronic devices.
  • a printed circuit board includes, for example, an insulating layer of, e.g., polyimide, having on one side or both sides thereof conductor layers of, e.g., a copper foil with prescribed patterns.
  • conductor layers having prescribed patterns in printed circuit boards such as flexible printed circuit boards are formed by the known methods such as the semi-additive, substractive, and full-additive methods (refer to JP 2002-176259, for example).
  • FIGS. 4 ( a ), 4 ( b ), 4 ( c ), 4 ( d ), 4 ( e ), and 4 ( f ) are schematic cross sectional views showing the steps of a method for manufacturing a printed circuit board by the semi additive method.
  • an insulating layer 11 of a resin film is first prepared, as shown in FIG. 4 ( a ).
  • a thin conductive film 12 is formed on the insulating layer 11 by sputtering or electroless plating.
  • a plating resist 13 is formed on the thin conductive film 12 using a dry film resist or the like.
  • the plating resist 13 has patterns opposite to the prescribed patterns of a conductor layer formed in a step shown below.
  • a conductor layer 14 is formed by electrolytic plating on the surfaces of the thin conductive film 12 where the plating resist 13 is not formed.
  • side etching of the thin conductive film 12 under the conductor layer 14 may occur during the removal of the thin conductive film 12 except the portions under the conductor layer 14 by chemical etching or the like.
  • side etching is described now with reference to the figure below.
  • FIG. 5 is a magnified view of the region B in FIG. 4 ( f ).
  • the thin conductive film 12 under the conductor layer 14 was etched together with both ends thereof being gouged as shown in FIG. 5 . This results in a deterioration of the adhesion of the conductor layer 14 to the thin conductive film 12 . In the case of a significant decrease in the adhesion, the conductor layer 14 may be stripped off.
  • a printed circuit board comprises, in sequence, an insulating layer, a thin copper film, and a conductor layer, wherein the conductor layer and the thin copper film have prescribed patterns, and the thin copper film has a first surface in contact with the insulating layer and a second surface in contact with the conductor layer, and contains a grain of a size that extends between the first surface and the second surface.
  • the thin copper film and conductor layer with the prescribed patterns are formed in sequence on the insulating layer.
  • the thin copper film contains a grain of a size that extends between the first surface in contact with the insulating layer and the second surface in contact with the conductor layer. This reduces or prevents the incidence of side etching of the thin copper film under the conductor layer during the removal of the thin copper film except the portions on which the conductor layer is formed. In this manner, a sufficient adhesion area of the thin copper film to the insulating layer is ensured to improve the adhesion.
  • the thin copper film preferably has a thickness of not less than 50 nm and not more than 300 nm. This further improves the adhesion of the conductor layer to the thin copper film.
  • the conductor layer may include copper. This even further improves the adhesion of the conductor layer to the thin copper film.
  • the printed circuit board may further comprise a thin metal film between the insulating layer and the thin copper film. In this manner, a sufficient adhesion area of the thin copper film to the thin metal film is ensured to improve the adhesion.
  • the thin metal film may include at least one of chromium and nickel. This further improves the adhesion between the insulating layer and the thin copper film.
  • the thin metal film preferably has a thickness of not less than 5 nm and not more than 50 nm. This still further improves the adhesion between the insulating layer and the thin copper film.
  • the insulating layer may include a flexible substrate.
  • the flexible substrate having flexibility allows the flexibility of the printed circuit board to be improved.
  • a method for manufacturing a printed circuit board by a semi-additive method comprises the steps of forming a thin copper film on an insulating layer, forming a conductor layer having prescribed patterns on the thin copper film, removing the thin copper film except portions on which the conductor layer is formed, and applying a thermal treatment to the thin copper film between the step of forming the thin copper film and the step of forming the conductor layer or between the step of forming the conductor layer and the step of removing the thin copper film.
  • the thin copper film is thermally treated between the step of forming the thin copper film and the step of forming the conductor layer or between the step of forming the conductor layer and the step of removing the thin copper film, which increases the size of grains contained in the thin copper film. This reduces or prevents the incidence of side etching of the thin copper film under the conductor layer during the removal of the thin copper film except the portions on which the conductor layer is formed. Thus, a sufficient adhesion area of the thin copper film to the insulating layer is ensured to improve the adhesion. In addition, where a thin metal film is present between the insulating layer and the thin copper film, a sufficient adhesion area of the thin copper film to the thin metal film is ensured to improve the adhesion.
  • a temperature during the thermal treatment of the thin copper film may be not less than 200° C. and not more than 300° C. This allows the size of grains contained in the thin copper film to be sufficiently increased.
  • the method for manufacturing a printed circuit board may include the steps of forming a resist on the thin copper film that has patterns opposite to the prescribed patterns, forming a conductor layer on the thin copper film except portions on which the resist is formed, and removing the resist after forming the conductor layer, and wherein the step of applying the thermal treatment to the thin copper film is provided between the step of forming the thin copper film and the step of forming the resist or between the step of removing the resist and the step of removing the thin copper film.
  • the step of applying the thermal treatment to the thin copper film is provided between the step of forming the thin copper film and the step of forming the resist or between the step of removing the resist and the step of removing the thin copper film. This prevents the resist from dissolving by the thermal treatment of the thin copper film.
  • the manufacturing method may further comprise the step of forming a thin metal film between the insulating film and the thin copper film. In this manner, a sufficient adhesion area of the thin copper film to the thin metal film is ensured to improve the adhesion.
  • the step of forming the thin metal film may include the step of forming at least one of chromium and nickel as the thin metal film. This further improves the adhesion between the insulating layer and the thin copper film.
  • the step of forming the thin metal film may include the step of forming the thin metal film having a thickness of not less than 5 nm and not more than 50 nm. This still further improves the adhesion between the insulating layer and the thin copper film.
  • the step of forming the thin copper film on the insulating layer may include the step of forming the thin copper film on a flexible substrate that serves as the insulating layer.
  • the flexible substrate having flexibility allows the flexibility of the printed circuit board to be improved.
  • the thin copper film contains a grain of the size that extends between the first surface in contact with the insulating layer and the second surface in contact with the conductor layer. This reduces or prevents the incidence of side etching of the thin copper film under the conductor layer during the removal of the thin copper film except the portions on which the conductor layer is formed. In this manner, a sufficient adhesion area of the thin copper film to the insulating layer is ensured to improve the adhesion. In addition, where the thin metal film is present between the insulating layer and the thin copper film, a sufficient adhesion area of the thin copper film to the thin metal film is ensured to improve the adhesion.
  • FIGS. 1 ( a ), 1 ( b ), 1 ( c ), and 1 ( d ) are schematic cross sectional views showing the steps of a method for manufacturing a printed circuit board according to an embodiment of the invention
  • FIGS. 2 ( e ), 2 ( f ), and 2 ( g ) are schematic cross sectional views showing the steps of a method for manufacturing a printed circuit board according to an embodiment of the invention
  • FIG. 3 is a magnified view of the region A in FIG. 2 ( f )
  • FIGS. 4 ( a ), 4 ( b ), 4 ( c ), 4 ( d ), 4 ( e ), and 4 ( f ) are schematic cross sectional views showing the steps of a method for manufacturing a printed circuit board by the semi additive method.
  • FIG. 5 is a magnified view of the region B in FIG. 4 ( f )
  • FIGS. 1 ( a ), 1 ( b ), 1 ( c ), and 1 ( d ) as well as FIGS. 2 ( e ), 2 ( f ), and 2 ( g ) are schematic cross sectional views showing the steps of a method for manufacturing a printed circuit board according to an embodiment of the invention.
  • an insulator film is made of polyimide or polyester, for example.
  • the insulating layer 1 may be formed by applying a resin onto a substrate made of a metal foil.
  • a thin metal film 2 and a thin copper film 3 are formed in sequence on the insulating layer 1 , as shown in FIG. 1 ( b ).
  • the thin metal film 2 which is provided to improve the adhesion between the insulating layer 1 and the thin copper film 3 , may only be provided when necessary.
  • Each of the thin metal film 2 and thin copper film 3 is formed by sputtering, electroless plating, or other suitable means.
  • the thin metal film 2 as used here includes at least either of chromium and nickel.
  • the thin metal film 2 may be made of a single layer of chromium, a laminated film of chromium and nickel, or a film of a chromium-nickel alloy.
  • the thickness of the thin metal film 2 is preferably in the range of not less than 5 nm and not more than 50 nm, for example. This further improves the adhesion of the thin copper film 3 to the insulating layer 1 .
  • the thickness of the thin copper film 3 is preferably in the range of not less than 50 nm and not more than 300 nm, for example. This further improves the adhesion of conductor patterns 5 described below to the thin copper film 3 .
  • the thin copper film 3 is laminated with, e.g., a dry film, and exposed and developed to form plating resist 4 thereon.
  • the plating resist 4 have patterns opposite to the conductor patterns 5 which are formed in a step shown below.
  • the conductor patterns 5 are formed on the surfaces of the thin copper film 3 where the plating resist 4 is not formed by electrolytic plating using, e.g., a copper sulfate electrolytic plating solution.
  • a metal or an alloy other than copper may also be used as the material of the conductor patterns 5 .
  • the plating resist 4 is subsequently removed by, for example, stripping, as shown in FIG. 2 ( e ). Then, a thermal treatment is applied to the thin copper film 3 . During the thermal treatment, the thin copper film 3 is held at a temperature of not less than 200° C. and not more then 300° for approximately an hour, preferably not less than half an hour and not more than two hours. Setting the time to not less than half an hour and not more than two hours as described above allows the grain size to be sufficiently increased while preventing consumption of an excessive energy.
  • the above-described thermal treatment allows the grain size of the thin copper film 3 to be increased.
  • the grain size of the thin copper film 3 is as large as approximately not less than 40 nm and not more than 300 nm.
  • the thin copper film 3 and thin metal film 2 are removed, by chemical etching using, e.g., a mixed solution of a sulfuric acid and oxygenated water, except the portions on which the conductor patterns 5 are formed.
  • a protective insulating layer 6 of polyimide or the like having prescribed patterns is formed.
  • a terminal is provided on the portion of each conductor pattern 5 that is not covered with the protective insulating layer 6 ( i.e., an aperture).
  • the thermal treatment is possible without a plating resist being formed.
  • the thermal treatment may be performed between the step of FIG. 1 ( b ) and the step of FIG. 1 ( c ).
  • FIG. 3 is a magnified view of the region A in FIG. 2 ( f ). As shown in FIG. 3 , thermally treating the thin copper layer 3 allows the size of grains contained in the thin copper layer 3 to be increased.
  • the thermally treated thin copper film 3 contains a grain 21 of such size as to extend between one surface of the thin copper film 3 in contact with the insulating layer 1 and the other surface of the thin copper film 3 in contact with the conductor pattern 5 . That is, the thin copper film 3 has a point where only a single grain 21 is present in the thickness direction V. This reduces or prevents the incidence of side etching of the thin copper film 3 under the conductor pattern 5 during the removal of the thin copper film 3 except the portion on which the conductor pattern 5 is formed. This ensures a sufficient adhesion area of the thin copper film 3 to the insulating layer 1 to improve the adhesion. Where the thin metal film 2 is present between the insulating layer 1 and the thin copper film 3 , a sufficient adhesion area of the thin copper film 2 to the thin metal film 2 is ensured to improve the adhesion.
  • any other highly insulating films of plastics may also be used as the insulating layer 1 .
  • a polyethylene terephthalate film, a polyethylene naphthalate film, a polyether nitril film, polyethersulfone film, a polyvinyl chloride film or the like may be used.
  • a polyimide film it is preferred to use, in particular, a polyimide film, a polyethylene terephthalate film, or a polyethylene naphthalate film, since they are superior in such properties as thermal resistance, dimensional stability, electrical properties, mechanical properties, and chemical resistant properties.
  • a printed circuit board according to Inventive Example and the method for manufacturing the printed circuit board will be described below.
  • the manufacturing method according to Inventive Example is based upon the manufacturing method according to the above-described embodiment, and therefore the description of drawings is omitted.
  • an insulating layer 1 made of a 25- ⁇ m polyimide insulator film was prepared.
  • a thin metal film 2 made of 30-nm nichrome and a 200-nm thin copper film 3 were formed in sequence on the insulating layer 1 by sputtering.
  • the thin copper film 3 was laminated with a dry film, and then exposed and developed to form a plating resist 4 thereon having patterns opposite to conductor patterns that are formed in a step shown below.
  • conductor patterns 5 of copper with a thickness of 8 ⁇ m, a width of 15 ⁇ m, and a pitch of 15 ⁇ m were formed, by electrolytic plating using a copper sulfate electrolytic plating solution, on the surfaces of the thin copper film 3 where the plating resist 4 was not formed.
  • the plating resist 4 was then stripped off, after which the thin copper film 3 was held at 250° C. for an hour to be thermally treated.
  • the thin copper film 3 and thin metal film 2 were removed except the portions under the conductor patterns 5 by chemical etching using a mixed solution of a sulfuric acid/oxygenated water. This was followed by the formation of a protective insulating film 6 of polyimide having prescribed patterns.
  • the thin copper film 3 contained grains of the size equal to the thickness of the thin copper film 3 , 200 nm; i.e., grains of such size as to extend between one surface of the thin copper film 3 in contact with the thin metal film 2 and the other surface of the thin copper film 3 in contact with the conductor patterns 5 in the thickness direction V.
  • the thin copper film 3 under the conductor patterns 5 did not show any side etching.
  • the method for manufacturing a printed circuit board according to Comparative Example differed from the above-described method according to Inventive Example in that the thin copper film 3 was not thermally treated.
  • the sizes of all of grains contained in the thin copper film 3 were less than 200 nm, and there always existed two or more grains between one surface of the thin copper film 3 in contact with the thin metal film 2 and the other surface of the thin copper film 3 in contact with the conductor patterns 5 in the thickness direction V.
  • the thin copper film 3 under the conductor patterns 5 showed side etching.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Transmitters (AREA)
US11/173,126 2004-07-01 2005-07-01 Printed circuit board and method for manufacturing printed circuit board Abandoned US20060000637A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/955,432 US8092696B2 (en) 2004-07-01 2007-12-13 Method for manufacturing printed circuit board

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004195939A JP4298597B2 (ja) 2004-07-01 2004-07-01 配線回路基板および配線回路基板の製造方法
JP2004-195939 2004-07-01

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/955,432 Division US8092696B2 (en) 2004-07-01 2007-12-13 Method for manufacturing printed circuit board

Publications (1)

Publication Number Publication Date
US20060000637A1 true US20060000637A1 (en) 2006-01-05

Family

ID=34941781

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/173,126 Abandoned US20060000637A1 (en) 2004-07-01 2005-07-01 Printed circuit board and method for manufacturing printed circuit board
US11/955,432 Expired - Fee Related US8092696B2 (en) 2004-07-01 2007-12-13 Method for manufacturing printed circuit board

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/955,432 Expired - Fee Related US8092696B2 (en) 2004-07-01 2007-12-13 Method for manufacturing printed circuit board

Country Status (8)

Country Link
US (2) US20060000637A1 (ko)
EP (1) EP1613135B1 (ko)
JP (1) JP4298597B2 (ko)
KR (1) KR101156915B1 (ko)
CN (1) CN100593964C (ko)
AT (1) ATE431699T1 (ko)
DE (1) DE602005014421D1 (ko)
TW (1) TWI363589B (ko)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103298263A (zh) * 2012-02-28 2013-09-11 深南电路有限公司 一种印制线路板及其加工方法
CN109661114A (zh) * 2017-10-11 2019-04-19 欣兴电子股份有限公司 制造导线的方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4844730B2 (ja) * 2006-05-22 2011-12-28 住友金属鉱山株式会社 金属被覆ポリイミド基板の評価方法
US8877074B2 (en) * 2006-12-15 2014-11-04 The Regents Of The University Of California Methods of manufacturing microdevices in laminates, lead frames, packages, and printed circuit boards
TW200847867A (en) * 2007-04-26 2008-12-01 Mitsui Mining & Smelting Co Printed wire board and manufacturing method thereof, and electrolytic copper foil for copper-clad lamination board used for manufacturing the same
JP5736722B2 (ja) * 2010-10-22 2015-06-17 大日本印刷株式会社 サスペンション用基板、サスペンション用基板の製造方法、サスペンション、素子付サスペンション、およびハードディスクドライブ
CN102427058B (zh) * 2011-11-09 2015-07-22 深南电路有限公司 通过溅射工艺制作线路图形的方法和芯片的重新布线方法
JP5812845B2 (ja) * 2011-12-19 2015-11-17 新光電気工業株式会社 発光素子搭載用パッケージ及び発光素子パッケージ並びにそれらの製造方法
CN103906364B (zh) * 2012-12-25 2017-07-14 上海美维科技有限公司 一种印制电路板中隐埋电阻的加工方法
CN103966601B (zh) * 2013-02-05 2018-05-18 汉达精密电子(昆山)有限公司 非金属基体导电线路的制作方法及其产品
JP6337909B2 (ja) 2014-02-04 2018-06-06 株式会社村田製作所 電子部品モジュールの製造方法
KR101893503B1 (ko) * 2016-05-27 2018-08-30 (주) 화인켐 미세배선용 연성 회로 기판 및 이의 제조방법
CN113630977B (zh) * 2020-05-06 2023-01-17 鹏鼎控股(深圳)股份有限公司 厚铜电路板及其制作方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3220897A (en) * 1961-02-13 1965-11-30 Esther S Conley Conducting element and method
US3328275A (en) * 1963-12-18 1967-06-27 Revere Copper & Brass Inc Treatment of copper to form a dendritic surface
US3674656A (en) * 1969-06-19 1972-07-04 Circuit Foil Corp Bonding treatment and products produced thereby
US5366814A (en) * 1992-11-19 1994-11-22 Nikko Gould Foil Co., Ltd. Copper foil for printed circuits and process for producing the same
US5437914A (en) * 1993-03-19 1995-08-01 Mitsui Mining & Smelting Co., Ltd. Copper-clad laminate and printed wiring board
US5679230A (en) * 1995-08-21 1997-10-21 Oak-Mitsui, Inc. Copper foil for printed circuit boards
US6278185B1 (en) * 1998-05-27 2001-08-21 Intel Corporation Semi-additive process (SAP) architecture for organic leadless grid array packages
US6319620B1 (en) * 1998-01-19 2001-11-20 Mitsui Mining & Smelting Co., Ltd. Making and using an ultra-thin copper foil
US20020056192A1 (en) * 2000-09-27 2002-05-16 Tokihito Suwa Method of producing multilayer printed wiring board and multilayer printed wiring board
US20020171151A1 (en) * 2001-01-04 2002-11-21 International Business Machines Corporation Method for forming interconnects on semiconductor substrates and structures formed
US6689268B2 (en) * 2000-03-10 2004-02-10 Olin Corporation Copper foil composite including a release layer

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4352716A (en) * 1980-12-24 1982-10-05 International Business Machines Corporation Dry etching of copper patterns
MY101308A (en) 1986-06-09 1991-09-05 Minnesota Mining & Mfg Presensitized circuit material.
JPH0783168B2 (ja) * 1988-04-13 1995-09-06 株式会社日立製作所 プリント板の製造方法
DE4113261A1 (de) 1991-04-23 1992-10-29 Siemens Ag Verfahren zum aufbringen einer basiskupferschicht auf glasfaserverstaerktem oder keramikpulvergefuelltem teflonsubstrat und verfahren zur herstellung sehr feiner leiterbahnstrukturen darauf
JPH06120630A (ja) 1992-10-07 1994-04-28 Ulvac Japan Ltd プリント配線基板用の銅箔
JPH0732544A (ja) 1993-07-22 1995-02-03 Mitsui Mining & Smelting Co Ltd 紙基材銅張積層板およびその製造方法
JPH0951163A (ja) 1995-05-31 1997-02-18 Mitsui Toatsu Chem Inc フレキシブル回路基板
JPH0955575A (ja) * 1995-08-10 1997-02-25 Mitsui Toatsu Chem Inc 積層体
CN1090200C (zh) * 1996-02-13 2002-09-04 日东电工株式会社 电路基片,形成电路的支承基片及其生产方法
EP1120820A3 (en) * 2000-01-24 2008-01-09 Ebara Corporation Method and apparatus for forming interconnect
JP3633422B2 (ja) * 2000-02-22 2005-03-30 ソニーケミカル株式会社 接続材料
JP2002176259A (ja) 2000-09-27 2002-06-21 Hitachi Ltd 多層プリント配線板の製造方法および多層プリント配線板
JP2002268905A (ja) * 2001-03-07 2002-09-20 Canon Inc プログラム動作装置、プログラム書込制御装置、プログラム書込制御方法及び記憶媒体
TW587103B (en) 2001-04-06 2004-05-11 Phoenix Prec Technology Corp Circuit board Ni/Au electroplating process without electroplated wires
JP2003318532A (ja) * 2002-04-24 2003-11-07 Toyo Metallizing Co Ltd フレキシブルプリント配線用基板
JP2003324258A (ja) 2002-05-01 2003-11-14 Nippon Mektron Ltd プリント配線板用銅張板
JP2004039771A (ja) 2002-07-02 2004-02-05 Nitto Denko Corp 配線回路基板の製造方法
JP2004082444A (ja) * 2002-08-26 2004-03-18 Dainippon Printing Co Ltd 金属層付き樹脂体および配線体
JP2004335807A (ja) * 2003-05-08 2004-11-25 Nitto Denko Corp 配線回路基板の製造方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3220897A (en) * 1961-02-13 1965-11-30 Esther S Conley Conducting element and method
US3328275A (en) * 1963-12-18 1967-06-27 Revere Copper & Brass Inc Treatment of copper to form a dendritic surface
US3674656A (en) * 1969-06-19 1972-07-04 Circuit Foil Corp Bonding treatment and products produced thereby
US5366814A (en) * 1992-11-19 1994-11-22 Nikko Gould Foil Co., Ltd. Copper foil for printed circuits and process for producing the same
US5437914A (en) * 1993-03-19 1995-08-01 Mitsui Mining & Smelting Co., Ltd. Copper-clad laminate and printed wiring board
US5679230A (en) * 1995-08-21 1997-10-21 Oak-Mitsui, Inc. Copper foil for printed circuit boards
US6319620B1 (en) * 1998-01-19 2001-11-20 Mitsui Mining & Smelting Co., Ltd. Making and using an ultra-thin copper foil
US6278185B1 (en) * 1998-05-27 2001-08-21 Intel Corporation Semi-additive process (SAP) architecture for organic leadless grid array packages
US6689268B2 (en) * 2000-03-10 2004-02-10 Olin Corporation Copper foil composite including a release layer
US20020056192A1 (en) * 2000-09-27 2002-05-16 Tokihito Suwa Method of producing multilayer printed wiring board and multilayer printed wiring board
US20020171151A1 (en) * 2001-01-04 2002-11-21 International Business Machines Corporation Method for forming interconnects on semiconductor substrates and structures formed

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103298263A (zh) * 2012-02-28 2013-09-11 深南电路有限公司 一种印制线路板及其加工方法
CN109661114A (zh) * 2017-10-11 2019-04-19 欣兴电子股份有限公司 制造导线的方法
US10615054B2 (en) 2017-10-11 2020-04-07 Unimicron Technology Corp. Method for manufacturing conductive line

Also Published As

Publication number Publication date
EP1613135A1 (en) 2006-01-04
KR101156915B1 (ko) 2012-06-21
TWI363589B (en) 2012-05-01
EP1613135B1 (en) 2009-05-13
US8092696B2 (en) 2012-01-10
KR20060048744A (ko) 2006-05-18
TW200603707A (en) 2006-01-16
JP4298597B2 (ja) 2009-07-22
US20080164236A1 (en) 2008-07-10
JP2006019522A (ja) 2006-01-19
DE602005014421D1 (de) 2009-06-25
CN100593964C (zh) 2010-03-10
ATE431699T1 (de) 2009-05-15
CN1717161A (zh) 2006-01-04

Similar Documents

Publication Publication Date Title
US8092696B2 (en) Method for manufacturing printed circuit board
US8522427B2 (en) Method of manufacturing a printed circuit board
EP1592290A1 (en) Wired circuit board and production method thereof
US20070101571A1 (en) Printed wiring board, its manufacturing method and circuit device
JP3570802B2 (ja) 銅薄膜基板及びプリント配線板
EP1594352B1 (en) Method for manufacturing a double-sided printed circuit board
US11690178B2 (en) Multilayer printed wiring board and method of manufacturing the same
KR20180037343A (ko) 낮은 치수변화율을 갖는 연성동박적층필름 및 그 제조방법
US8017309B2 (en) Method of manufacturing wiring circuit board
KR20170028047A (ko) 연성동박적층필름, 그 제조방법, 및 그것을 이용한 연성인쇄회로기판의 제조방법
JP2009501433A (ja) フレキシブル回路基板
WO2004042814A1 (ja) 電子部品実装用フィルムキャリアテープ
KR20170071205A (ko) 연성동박적층판 및 이의 제조 방법
JPH01321687A (ja) フレキシブルプリント配線用基板
JPH05245432A (ja) ポリイミド樹脂被覆板及びその製造方法
JPH07273466A (ja) 多層配線板の製造方法
JP2000049440A (ja) プリント配線用多層板の製造方法
US20240206057A1 (en) Wiring substrate and method for manufacturing the same
US7955485B2 (en) Planar laminate substrate and method for fabricating organic laminate substrate PCBS, semiconductors, semiconductor wafers and semiconductor devices having miniaturized electrical pathways
JP2006222217A (ja) 配線回路基板の製造方法
CN115968112A (zh) 一种线路板制备方法以及线路板
JPH07123178B2 (ja) フレキシブル配線基板およびその製造方法
JP2002198399A (ja) 半導体キャリア用フィルムの製造方法
JPS62242389A (ja) フレキシブル配線板の製造方法
US20150334832A1 (en) Electrode structure

Legal Events

Date Code Title Description
AS Assignment

Owner name: NITTO DENKO CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NAKAMURA, KEI;YAMATO, TAKESHI;REEL/FRAME:016456/0569

Effective date: 20050822

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION