US20050073339A1 - Differential amplifier and bit-line sense amplifier adopting the same - Google Patents

Differential amplifier and bit-line sense amplifier adopting the same Download PDF

Info

Publication number
US20050073339A1
US20050073339A1 US10/742,314 US74231403A US2005073339A1 US 20050073339 A1 US20050073339 A1 US 20050073339A1 US 74231403 A US74231403 A US 74231403A US 2005073339 A1 US2005073339 A1 US 2005073339A1
Authority
US
United States
Prior art keywords
bit
differential amplifier
sense amplifier
transistor
amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/742,314
Other languages
English (en)
Inventor
Kwang Rho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RHO, KWANG MYOUNG
Publication of US20050073339A1 publication Critical patent/US20050073339A1/en
Priority to US11/144,129 priority Critical patent/US7123531B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H03K17/145—Modifications for compensating variations of physical values, e.g. of temperature in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Definitions

  • the present patent relates to a bit-line sense amplifier for sensing and amplifying data in a semiconductor memory to output them and, more particularly, to a bit-line sense amplifier capable of modifying an amplification method in a sequential manner by using switching elements controlled by switching control signals to compensate an offset voltage of the sense amplifier.
  • bit-line sense amplifier senses and amplifies data on a bit-line to output them on a data bus
  • a data bus sense amplifier senses and amplifies the data amplified by the bit-line sense amplifier again to output them to a data output buffer.
  • a cross-coupled latch type amplifier is used as the bit-line sense amplifier.
  • bit-line sense amplifier operations of the typical bit-line sense amplifier will be described with reference to FIG. 1 as follows.
  • transistors Q 1 to Q 3 are turned on depending on a bit-line precharge signal BLP, so that bit-lines Bit and /Bit are precharged by a precharge voltage (e.g., V BLP ).
  • a precharge voltage e.g., V BLP
  • a row decoder analyzes a row address input from the external to select a word-line corresponding to the row address. Then, a cell transistor connected to the selected word-line is turned on, so that a potential difference occurs between the bit-line Bit connected to the selected memory cell and the complementary bit-line /Bit, while charge sharing occurs between a cell capacitance and a bit-line capacitance.
  • a sense amplifier control signal is at a high level.
  • a sense amplifier control signal /S is at a low level, a bit-line sense amplifier operates to sense the potential difference between the bit-line Bit and the complementary bit-line /Bit and then amplify it.
  • the potential of the bit-line Bit connected to the selected cell comes to be lower than the precharge voltage, and the potential of the bit-line /Bit which is not connected to the selected cell remains at a precharge voltage, thereby generating a potential difference between two bit-lines.
  • bit-line sense amplifier corresponding to a cross-coupled latch type amplifier
  • the transistors Q 5 and Q 6 are turned on, while the transistors Q 4 and Q 7 are turned off, so that the bit-line Bit connected to the selected memory cell is at a low level by the sense amplifier control signal /S.
  • the complementary bit-line /Bit is at a low level by the sense amplifier control signal RTO.
  • a column address is analyzed by a column decoder, and then the data on the bit-line amplified by the bit-line amplifier are sent to a data bus if a column control signal corresponding to the column address is enabled at a high level.
  • bit-line sense amplifier operates at a lower voltage, the amount of charges stored in a memory cell can be reduced, so that the potential difference between the bit-line connected to a memory cell and the complementary bit-line is reduced during the charge sharing.
  • bit-line sense amplifier senses a small potential difference between the bit-line connected to the selected memory cell and the complementary bit-line
  • the sense amplifier can operate slower because the potential difference is almost the same as the offset voltage.
  • data errors can occur because the data can be incorrectly sensed if the difference is smaller than the offset voltage.
  • FIG. 2 shows a conventional bit-line sense amplifier for solving the above problems, and will be described with reference to FIG. 3 .
  • a time period T0 in FIG. 3 is a preparation stage for driving a sense amplifier.
  • a precharge signal BLP is enabled at a high level before a semiconductor memory device performs a read or a write operation, so that transistors NM 4 and NM 5 are turned on.
  • the bit-lines BL and /BL are precharged by a precharge voltage V BLP .
  • an equalization control signal EQ is enabled at a high level, so that a transistor NM 1 is turned on and the bit-lines BL and /BL are interconnected to be equalized.
  • a sense amplifier control signal /S is also precharged by the precharge voltage V BLP according to the same method.
  • a sense amplifier 40 is enabled.
  • the sense amplifier 40 is sequentially modified in each time period depending on the control signals CONA, CONB, and CONC, so as to be a negative feedback differential amplification scheme in a time period T1, a normal differential amplification scheme in a time period T2, a positive feedback differential amplification scheme in a time period T3, and a cross-coupled latch type amplification scheme in a time period T4 in that order.
  • the precharge control signal BLP is disabled at a low level and the sense amplifier control signal /S is enabled at a low level, so that the sense amplifier 40 begins to operate.
  • the switching control signals CONA and CONB are at a low level, the PMOS transistor PM 3 is turned on, so that the gate of the PMOS transistor PM 1 is commonly connected to the drain.
  • the sense amplifier 40 constitutes a differential amplifier.
  • the NMOS transistor NM 13 is turned on, so that the complementary bit-line /BL corresponding to the inverted input terminal of the sense amplifier 40 is connected to the drain to which the PMOS transistor PM 2 corresponding to an output terminal of the sense amplifier 40 and the NMOS transistor NM 9 are commonly connected.
  • the sense amplifier 40 constitutes a negative feedback differential amplifier. Accordingly, the potential of the complementary bit-line /BL is adjusted to a voltage capable of compensating the offset voltage of the sense amplifier 40 .
  • the switching control signal CONC is at a low level, so that the NMOS transistor NM 13 is turned off, and all other switching control signals CONA and CONB remain at a low level.
  • the sense amplifier 40 constitutes a normal differential amplifier.
  • the word-line WL is enabled, so that the data stored in the selected memory cell is loaded on the bit-line BL. Therefore, the data on the bit-line BL are sensed and amplified by the normal differential amplifier.
  • the switching control signal CONB comes to be a high level, and the NMOS transistor NM 11 is turned on, so that the bit-line BL corresponding to the non-inverted input terminal of the sense amplifier 40 is connected to the drain to which the PMOS transistor PM 2 corresponding to an output terminal of the sense amplifier 40 and the NMOS transistor NM 9 are commonly connected, while other switching control signals CONA and CONC remain at a low level.
  • the sense amplifier 40 constitutes a positive feedback differential amplifier. For this reason, the data on the bit-line BL is converted to a large intensity of signal by the action of the positive feedback differential amplifier.
  • the switching control signal CONA is at a high level, so that the PMOS transistor PM 3 is turned off, and the NMOS transistors NM 10 and NM 12 are turned on.
  • the switching control signal CONB is at a high level so that the NMOS transistor NM 11 is turned on, while the switching control signal CONC remains at a low level so that the NMOS transistor NM 13 remains to be turned off.
  • the sense amplifier 40 constitutes a cross-coupled latch. Therefore, it is possible to rapidly latch the data that have been amplified in the previous stage T3.
  • the column selection signal YI is enabled to be at a high level, so that the latched data are output to the data buses DB and /DB.
  • the mechanism of the offset voltage compensation in the time period T1 will be described in detail as follows. That is, the bit-line sense amplifier in FIG. 2 is temporarily modified to be a differential amplifier as shown in FIG. 4A , in the time period T1. At this moment, the offset voltage can be compensated by shorting input/output terminals of the differential amplifier for a predetermined time period. The operation of such a differential amplifier will be described in detail with reference to FIGS. 4A and 4B .
  • the differential amplifier When an inverted ( ⁇ ) input terminal and the output of the differential amplifier are shorted in an instant, the differential amplifier is modified to operate as a negative feed back differential amplifier and function in such a way that the input offset voltage can be cancelled. If a voltage gain of the differential amplifier is sufficiently large, the differential voltage between the input terminals becomes an input offset voltage of the differential amplifier in a predetermined time after the shorting, so that offset compensation can be achieved and its sensitivity can be improved.
  • the offset compensation effect of the bit-line sense amplifier is significantly affected by the difference between the precharge level (Vin, typically 1 ⁇ 2 VDD) of a differential input amplifier and the output voltage level Vo of a differential amplifier with no offset.
  • FIG. 5 shows a residual offset voltage according to a voltage gain of the differential amplifier and an output voltage level of the differential amplifier. It is possible to recognize that the residual offset can be considerably large depending on the difference between the output voltage level and the input voltage level. For example, if the voltage gain is set to 10, the difference between the input voltage and the output voltage is set to 200 mV, and an original input offset voltage is set to 50 mV, the residual offset voltage becomes 23 mV, so that 45% of the original offset voltage still remains to be not compensated.
  • FIG. 6 is a graph showing bit-line signal components in a variety of configurations and array arrangements.
  • the bit-line signals are composed of an effective read signal A, a residual offset voltage B, and a charge noise C.
  • the residual offset voltage based on design conditions is set to about 10 to 20 mV, and the original offset voltage is set to 40 mV, which correspond to 25 to 50% of the bit-line signals.
  • the output voltage level of the differential amplifier should be designed to correspond with the precharge level of the differential input.
  • the output voltage level of the differential amplifier is affected by the threshold voltage variations in the input NMOS transistor or the PMOS transistor, and geometrical variations in the channel length or width, thereby causing inconsistency with the design values.
  • the variation on the output voltage caused by such process variations significantly affects the residual offset voltage of the bit-line sense amplifier.
  • the differential amplifier comprises PMOS transistors P 1 and P 2 and NMOS transistors N 1 , N 2 , and N 3 , which constitute a current mirror.
  • the PMOS transistors P 1 and P 2 correspond to active resistors
  • the NMOS transistor N 3 corresponds to a current source.
  • the curve C 1 in FIG. 8 designates a current driving capability of the PMOS transistor based on design values
  • the curve C 2 designates a current driving capability of the PMOS transistor based on a practical case.
  • the practical current driving capability of the PMOS transistor is lower than that of the design values due to process variations. This causes a variation on the output voltage level. In other words, despite the fact that the output voltage should reach Vo2 according to the design value, the output voltage remains at Vo1 which is lower than Vo2 due to the variation on the current driving capability.
  • the present patent is directed to provide a differential amplifier capable of maintaining a constant output voltage level irrespective of the variation on the current driving capability.
  • the present patent is directed to use a differential amplifier capable of maintaining a constant output voltage level irrespective of the variation on the current driving capability as a bit-line sense amplifier in order to compensate the offset voltage.
  • One aspect of the patent is to provide a differential amplifier having a load connected between a voltage source, a first and a second output terminal; a first transistor connected between the first output terminal and a first node.
  • the differential amplifier also includes a third transistor that is turned on depending on a first input signal; a second transistor connected between the second output terminal and the first node, wherein the second transistor is turned on depending on a second input signal.
  • a MOSFET resistor is also included and is connected between the first node and a second node.
  • the MOSFET resistor has a resistance which is variable depending on a potential of the first output terminal or the second output terminal. Also included is a common current source connected to the second node.
  • a bit line sense amplifier includes switching elements for sequentially modifying the sense amplifier to a negative feedback differential amplifier, a normal differential amplifier, a positive feedback differential amplifier, and a cross-coupled latch, in that order.
  • the sense amplifier senses data on a pair of bit-lines in a semiconductor memory.
  • Also includes is a transistor connected between the differential amplifiers and a common current source, wherein the transistor has a resistance which is variable depending on a potential of an output of one of the differential amplifiers or remains constant by a different power source.
  • a bit-line sense amplifier includes switching elements to sequentially modify a sense amplifier to operate as a negative feedback differential amplifier, a normal differential amplifier, and a cross-coupled latch, in that order, depending on control signals.
  • the sense amplifier senses data on a pair of bit-lines in a semiconductor memory; and a restore means is included to rewrite the sensed data on the pair of bit-lines and a selected cell in the semiconductor memory.
  • a transistor is connected between the differential amplifiers and a common current source, the transistor having a resistance which is variable depending on a potential of an output of one of the differential amplifiers or remains constant by a different power source.
  • FIG. 1 is a circuit diagram of a conventional bit-line sense amplifier
  • FIG. 2 is a circuit diagram of another conventional bit-line sense amplifier, which is upgraded from the circuit in FIG. 1 ;
  • FIG. 3 is a waveform chart for describing operations of the circuit in FIG. 2 ;
  • FIGS. 4A and 4B show differential amplifiers for describing operations of the circuit in FIG. 2 ;
  • FIG. 5 is a graph for describing a voltage gain of the differential amplifier and the bit-line residual offset according to the output voltage level.
  • FIG. 6 is a graph for describing components of the signal on the bit-line in the read operation
  • FIG. 7 shows a conventional differential amplifier
  • FIG. 8 is a graph for describing a variation on the output voltage depending on the current driving capability of the PMOS transistor in FIG. 7 ;
  • FIG. 9 shows an embodiment of an exemplary differential amplifier
  • FIG. 10 is a detailed circuit diagram of an embodiment of an exemplary bit-line sense amplifier
  • FIG. 11 is a waveform chart for describing operations of the circuit in FIG. 10 ;
  • FIG. 12 is a detailed circuit diagram of an alternative embodiment of a bit-line sense amplifier.
  • FIG. 13 is a waveform chart for describing operations of the circuit in FIG. 12 .
  • FIG. 9 shows an embodiment of an exemplary differential amplifier.
  • the differential amplifier of FIG. 9 includes a current mirror including PMOS transistors M 3 and M 4 and a NMOS transistor, a current source having an NMOS transistor M 5 , and a MOSFET resistor having an NMOS transistor inserted between the current mirror and the current source.
  • the PMOS transistors M 3 and M 4 constitute a static voltage source, if characteristics of the NMOS transistors M 1 and M 2 are identical, the amount of the currents through the transistor M 3 and M 1 are identical to those through the transistors M 4 and M 2 , respectively.
  • a gate terminal of the NMOS transistor M 6 is connected to an output node (a) of the differential amplifier.
  • a variation ⁇ Vo on the output voltage OUT is generated due to process variations in a conventional differential amplifier into which the MOSFET resistor M 6 has not been inserted, it can be considered the situation that a current of gm3* ⁇ Vo is supplied to the node (a) of the differential amplifier in a design level which assumes no process variations. If such a current is applied to the disclosed differential amplifier, the variation on the output voltage OUT is significantly reduced due to the negative feedback operation in the MOSFET resistor M 6 .
  • the variation on the voltage at the node (a) can be expressed as the following equation.
  • the variation ⁇ V of on the output voltage level can be reduced by allowing a trans-conductance gm of the NMOS FET M 6 to be larger than the trans-conductance gm of the PMOS FET M 3 .
  • FIG. 10 is a detailed circuit diagram of a embodiment of an exemplary bit-line sense amplifier, which adopts the differential amplifier shown in FIG. 9 .
  • the configuration and the operation of the circuit shown in FIG. 10 is described in detail with reference to FIG. 11 .
  • the bit-line sense amplifier of FIG. 10 includes an equalization/precharge control unit 10 to equalize and precharge the pair of bit-lines Bit and /Bit on a constant voltage V BLP depending on the precharge control signal BLP and a sense amplifier 40 to sense and amplify the data on the pair of bit-lines Bit and /Bit.
  • the equalization/prechage control unit 10 includes an NMOS transistor 3 connected between the pair of bit-lines Bit and /Bit and a pair of NMOS transistors 1 and 2 serially connected between the pair of bit-lines Bit and /Bit.
  • the NMOS transistors 1 , 2 , and 3 are turned on depending on the precharge control signal BLP, and the bit-line precharge voltage V BLP that is supplied to the connection node in the NMOS transistors 1 and 2 .
  • the sense amplifier 40 includes the PMOS transistors 4 , 5 , 6 , and 22 and NMOS transistors 7 , 8 , 9 , 10 , 21 , and 23 .
  • the PMOS transistor 4 is connected between an internal power voltage source VDD and the node K 1 , and its gate is connected to the node K 3 .
  • the PMOS transistor 5 is connected between the internal power voltage source VDD and the node K 2 , and its gate is connected to the node K 1 .
  • the NMOS transistor 9 is connected between the bit-line Bit and the node K 2 , and its gate receives a control signal Conbprz.
  • the NMOS transistor 10 is connected between the bit-line /Bit and the node K 1 , and its gate receives a control signal Condprz.
  • the PMOS transistor 6 is connected between the node K 1 and the node K 3
  • the NMOS transistor 7 is connected between the node K 3 and the node K 2 .
  • the gates of the PMOS transistor 6 and the NMOS transistor 7 receive a control signal Conaz.
  • the NMOS transistor 11 is connected between the node K 1 and the node K 4 , and its gate is connected to the bit-line Bit.
  • the NMOS transistor 12 is connected between the node K 2 and the node K 4 , and its gate is connected to the bit-line /Bit.
  • the PMOS transistor 22 is connected between the node K 3 and the node K 5
  • the NMOS transistor 23 is connected between the node K 5 and the voltage source (e.g., V BLP ).
  • the gates of the PMOS transistor 22 and the NMOS transistor 23 receive a control signal Conaz.
  • the NMOS transistor 21 is connected between the node K 4 and the input terminal of the sense amplifier control signal Sx, and its gate is connected to the node K 5 .
  • the NMOS transistor 8 is connected between the node K 2 and the bit-line /Bit, and the transistor's gate receives a control signal Concz.
  • the PMOS transistors 4 and 5 , and the NMOS transistors 11 and 12 are basic components of the sense amplifier 40 .
  • the PMOS transistor 6 and the NMOS transistors 7 , 8 , 9 , and 10 are switching elements controlled by the control signals Conaz, Conbprz, Concz, and Condprz, which sequentially modify the amplification method of the sense amplifier 40 to a feedback differential amplification, a normal differential amplification, a positive feedback differential amplification, and a cross-coupled latch type amplification, in that order.
  • the NMOS transistor 8 is a switching element, which instantaneously shorts the input and the output of the differential amplifier for an offset compensation of the NMOS transistor 8 .
  • the NMOS transistors 21 and 23 and the PMOS transistor 22 are used as elements for improving bias stability and increasing a differential amplification gain.
  • the NMOS transistor 21 is used as an NMOS FET resistor, which operates in a linear region.
  • the PMOS transistor 22 and the NMOS transistor 23 correspond to switching elements connected to the output of the differential amplifier to improve bias stability when the offset compensation is performed on the NMOS transistor 21 , and connected to a constant voltage V BLP after the offset compensation.
  • the time period T0 shown in FIG. 11 corresponds to a preparation stage for driving the sense amplifier.
  • the precharge control signal BLP is enabled at a high level, so that the NMOS transistors 1 , 2 , and 3 are turned on.
  • the bit-lines Bit and /Bit are equalized and precharged with the precharge voltage V BLP .
  • the sense amplifier control signal /Sx is also precharged with the precharge voltage V BLP in a similar manner.
  • the sense amplifier 40 is enabled.
  • the sense amplifier 40 is sequentially modified to operate as: a negative feedback differential amplifier in the time period T1 for an offset cancellation, a normal differential amplifier in the time period T2 for a sensing operation, a positive feedback amplifier in the time period T3 for a locking operation, and a cross-coupled latch type amplifier in the time period T4 for a latching and a restoring operations, in that order, depending on the control signals Conaz, Conbprz, Concz, and Condprz.
  • the time period T5 corresponds to the time period for a bit-line precharge for the next cycle.
  • the precharge control signal BLP is disabled at a low level and the sense amplifier control signal /Sx is enabled at a low level, so that the sense amplifier 40 begins to operate.
  • the PMOS transistors 6 and 22 are turned on.
  • the gate of the NMOS transistor 21 is connected to a node K 1 . Therefore, the PMOS transistors 4 and 5 and the NMOS transistors 11 , 12 , and 21 constitute a differential amplifier.
  • the NMOS transistor 21 is operated as MOSFET resistor, and connected to the node k 1 corresponding to the first output of the differential amplifier.
  • the switching control signal Concz is at a high level, the NMOS transistor 8 is turned on. Therefore, the output node K 2 of the differential amplifier is connected to the gate of the NMOS transistor 12 corresponding to the inverted input terminal of the differential amplifier. As a result, the differential amplifier is operated as a negative feedback differential amplifier.
  • the potential in the bit-line /Bit is controlled to be the voltage capable of compensating the offset voltage of the sense amplifier 40 . Meanwhile, a variation on the output voltage of the differential amplifier caused by process variations is significantly reduced due to the negative feedback effect of the NMOS transistor, so that the residual offset after the offset compensation is significantly reduced.
  • the switching control signal Concz is at a low level
  • the NMOS transistor 8 is turned off, and other switching control signals Conaz, Conbprz, and Condprz remain at a low level.
  • the sense amplifier 40 constitutes a normal differential amplifier comprising the PMOS transistors 4 and 5 and the NMOS transistors 11 , 12 , and 21 .
  • the switching control signal Conbprz is at a high level
  • the NMOS transistor 9 is turned on
  • the bit-line Bit corresponding to the non-inverted input terminal of the sense amplifier 40 is connected to the node k 2 corresponding to the non-inverted output terminal, and other switching control signals Conaz, Concz, and Condprz remain at a low level.
  • the sense amplifier 40 operates as a positive feedback differential amplifier including the PMOS transistors 4 and 5 and the NMOS transistors 11 , 12 , and 21 .
  • the data on the bit-line Bit are converted into a larger intensity of signals due to the positive feedback differential amplification effect.
  • the switching control signal Conaz is at a high level, the PMOS transistor 6 is turned off, and the NMOS transistors 7 and 23 are turned on.
  • the bit-line precharge voltage. V BLP is supplied to the gate of the NMOS transistor 21 .
  • the switching control signals Conbprz and Condprz come to be at a high level, so that the NMOS transistors 9 and 10 are turned on.
  • the switching control signal Concz remains at a low level, so that the NMOS transistor 8 remains to be turned off.
  • the sense amplifier 40 operates as a cross-coupled latch. Therefore, the data amplified in the previous stages can be rapidly latched.
  • FIG. 12 is a detailed circuit diagram showing the bit-line sense amplifier of the second embodiment of the present invention.
  • the circuit in FIG. 12 is arranged in a similar manner to the circuit in FIG. 11 .
  • the NMOS transistors 15 and 16 for latching the sensed cell data are separated from the NMOS transistors 7 and 8 which senses the cell data, the circuit in FIG. 12 is shown to be somewhat complicated compared to the circuit in FIG. 11 .
  • the transistors 1 to 19 function as a bit-line sense amplifier similar to the circuit in FIG. 1 , and the control signals CMP, EQL, WL, RST, STC, Sx, and CSL are used to control the elements included in the bit-line sense amplifier.
  • the NMOS transistors 1 , 2 , and 3 are used to equalize and precharge the pair of bit-lines Bit and /Bit with VDD/2.
  • the PMOS transistors 13 and 14 and the NMOS transistors 15 and 16 function as a basic cross-coupled latch in the bit-line sense amplifier.
  • the NMOS transistors 7 and 8 directly sense the data on the bit-line.
  • the NMOS transistor 21 is a common current source in the differential amplifier.
  • the NMOS transistor 11 and the PMOS transistor 12 are switching elements to allow the bit-line sense amplifier to be modified to a differential amplifier in an initial step and to a cross-coupled latch type amplifier in the following step.
  • the NMOS transistors 5 and 6 are switching elements to allow the latched data to be restored in the bit-line cell 4 .
  • the NMOS transistors 10 and 19 are switching elements to short the input and the output terminals of the differential amplifier in an offset compensation step and applying a reference voltage to the input terminal of the differential amplifier, respectively.
  • the time period T0 corresponds to the preparation stage for driving the sense amplifier.
  • the equalization control signal EQL is enabled at a high level, so that the NMOS transistors 1 , 2 , and 3 are turned on.
  • the bit-lines Bit and /Bit are equalized and precharged with the precharge voltage V BLP .
  • the sense amplifier control signal /Sx is also precharged to the precharge voltage V BLP in a similar manner.
  • the sense amplifier 50 is enabled.
  • the sense amplifier 50 is modified to a negative feedback differential amplifier in the time period T1 for an offset cancellation, a normal differential amplifier in the time period T2 for the sensing, and a latch in the time period T3 for the latching, in that order, depending on the control signals.
  • the time period T4 corresponds to a restoring period.
  • the time period T5 corresponds to a precharging period for the next cycle.
  • the equalization control signal EQZ is at a low level, so that the sense amplifier 50 is enabled.
  • the control signal CMP is at a high level, so that the NMOS transistor 19 is turned on and the reference voltage V BLP is applied to the bit-line Bit.
  • the control signal LTC is at a low level, the PMOS transistors 12 and 23 are turned on, so that the PMOS transistors 13 and 14 and the NMOS transistors 7 , 8 , and 21 function as a differential amplifier.
  • the NMOS transistor 21 is operated as a MOSFET resistor, and the transistor's gate is connected to the first output node k 1 of the differential amplifier through the PMOS transistors 23 and 12 .
  • the differential amplifier is operated as a negative feedback differential amplifier.
  • the potential in the bit-line /Bit is adjusted to a voltage capable of compensating the offset voltage of the sense amplifier 50 . Meanwhile, a variation on the input voltage in the differential amplifier due to process variations is significantly reduced by a negative feedback effect of the NMOS transistor N 21 , so that the residual offset after the compensation is significantly reduced.
  • the control signal CMP is at a low level, so that the NMOS transistor 10 is turned off, and the inverted input of the differential amplifier is separated from the first input. As a result, a normal differential amplifier is formed.
  • the control signal WL is enabled at a high level, so that the data in the cell 4 is loaded on the bit-line /Bit.
  • the data on the bit-line /Bit is sensed and amplified by the sense amplifier 50 having the design of a normal differential amplifier in which an offset compensation has been accomplished.
  • the control signal LTC is at a high level, so that the NMOS transistor 11 is turned on.
  • the PMOS transistors 13 and 15 and the NMOS transistors 15 and 16 function as a latch.
  • the sense amplifier 50 has the shape of a cross-coupled latch.
  • the control signal RST is at a high level, so that the NMOS transistors 5 and 6 are turned on. As a result, the amplified cell data are rewritten to the bit-line and the cell, again.
  • the offset cancellation step is accomplished in advance of the sensing step.
  • the sense amplifier has the design of a differential amplifier, and the input and the output terminals are shorted for the offset cancellation for a certain moment.
  • the residual offset value after the offset compensation is affected by a voltage gain of the differential amplifier, and a difference between a balanced output level and a voltage level of the input signal. In other words, when the voltage gain of the differential amplifier is not sufficiently large, the residual offset value will not reach 50% of that before the offset compensation.
  • a MOSFET resistor is inserted into a common source of the differential amplifier.
  • a negative feedback effect promotes bias stability. Therefore, it is possible to restrain a variation on the balanced output voltage level in the differential amplifier caused by process variations. As a consequence, it is possible to significantly reduce the residual offset value.
  • the cell data obtained by such operations can function as a more important factor in low voltage operations in a DRAM.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Amplifiers (AREA)
  • Static Random-Access Memory (AREA)
US10/742,314 2003-10-02 2003-12-19 Differential amplifier and bit-line sense amplifier adopting the same Abandoned US20050073339A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/144,129 US7123531B2 (en) 2003-10-02 2005-06-03 Differential amplifier and bit-line sense amplifier adopting the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030068582A KR100542710B1 (ko) 2003-10-02 2003-10-02 차동 증폭기 및 이를 채용한 비트라인 센스 증폭기
KR2003-68582 2003-10-02

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/144,129 Division US7123531B2 (en) 2003-10-02 2005-06-03 Differential amplifier and bit-line sense amplifier adopting the same

Publications (1)

Publication Number Publication Date
US20050073339A1 true US20050073339A1 (en) 2005-04-07

Family

ID=34374255

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/742,314 Abandoned US20050073339A1 (en) 2003-10-02 2003-12-19 Differential amplifier and bit-line sense amplifier adopting the same
US11/144,129 Expired - Lifetime US7123531B2 (en) 2003-10-02 2005-06-03 Differential amplifier and bit-line sense amplifier adopting the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/144,129 Expired - Lifetime US7123531B2 (en) 2003-10-02 2005-06-03 Differential amplifier and bit-line sense amplifier adopting the same

Country Status (6)

Country Link
US (2) US20050073339A1 (ja)
JP (1) JP4557206B2 (ja)
KR (1) KR100542710B1 (ja)
CN (1) CN100492892C (ja)
DE (1) DE10361038B4 (ja)
TW (1) TWI281779B (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080042691A1 (en) * 2006-08-16 2008-02-21 Vijay Kumar Srinivasa Raghavan High Speed and Power Efficient Sense Amplifier With Leakage Testing and Read Debug Capability
US20090225057A1 (en) * 2007-06-22 2009-09-10 Polak Robert D Colored Morphing Apparatus for an Electronic Device
CN103778944A (zh) * 2012-10-24 2014-05-07 瑞萨电子株式会社 半导体装置
US20150236698A1 (en) * 2014-02-19 2015-08-20 Altera Corporation Stability-enhanced physically unclonable function circuitry
CN105070310A (zh) * 2015-08-11 2015-11-18 深圳芯邦科技股份有限公司 一种带失调校正的灵敏放大器
CN108352175A (zh) * 2015-11-30 2018-07-31 德州仪器公司 低功率高性能sram中的感测放大器
CN114078517A (zh) * 2020-08-12 2022-02-22 上海复旦微电子集团股份有限公司 灵敏放大器及存储器

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4965883B2 (ja) * 2006-04-07 2012-07-04 株式会社東芝 半導体集積回路装置および半導体集積回路装置のトリミング方法
KR100930400B1 (ko) * 2007-08-13 2009-12-08 주식회사 하이닉스반도체 차동 증폭기 및 이를 이용한 입력 회로
US8014218B2 (en) * 2008-12-24 2011-09-06 International Business Machines Corporation Capacitively isolated mismatch compensated sense amplifier
JP5240056B2 (ja) * 2009-05-12 2013-07-17 富士通セミコンダクター株式会社 半導体メモリおよびシステム
KR101047051B1 (ko) * 2009-05-20 2011-07-06 주식회사 하이닉스반도체 비휘발성 반도체 메모리 회로
KR101053525B1 (ko) * 2009-06-30 2011-08-03 주식회사 하이닉스반도체 감지 증폭기 및 이를 이용한 반도체 집적회로
US8125840B2 (en) * 2009-08-31 2012-02-28 International Business Machines Corporation Reference level generation with offset compensation for sense amplifier
KR20140023806A (ko) 2012-08-17 2014-02-27 삼성전자주식회사 자기 저항 메모리 장치의 배치 구조
US9691462B2 (en) * 2014-09-27 2017-06-27 Qualcomm Incorporated Latch offset cancelation for magnetoresistive random access memory
KR102288481B1 (ko) * 2015-04-22 2021-08-10 에스케이하이닉스 주식회사 반도체 장치의 센스앰프
KR20170030304A (ko) 2015-09-09 2017-03-17 삼성전자주식회사 스위처블 감지 증폭기를 갖는 메모리 장치
KR102562312B1 (ko) 2016-08-24 2023-08-01 삼성전자주식회사 비트라인 센스 앰프
KR102589761B1 (ko) * 2016-10-18 2023-10-18 에스케이하이닉스 주식회사 데이터 감지 증폭 회로 및 반도체 메모리 장치
KR20180076842A (ko) * 2016-12-28 2018-07-06 삼성전자주식회사 오프셋 제거 기능을 갖는 감지 증폭기
KR20200131550A (ko) * 2019-05-14 2020-11-24 에스케이하이닉스 주식회사 반도체 장치의 데이터 감지 회로
CN111429955B (zh) * 2020-03-10 2021-12-10 北京中科银河芯科技有限公司 读出放大器、存储数据读出方法、集成电路及电子设备
US11961551B2 (en) 2021-04-09 2024-04-16 Samsung Electronics Co., Ltd. Bitline sense amplifier and a memory device with an equalizer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276369A (en) * 1989-07-20 1994-01-04 Kabushiki Kaisha Toshiba Sense amplifier circuit having a bias current control means
US5451898A (en) * 1993-11-12 1995-09-19 Rambus, Inc. Bias circuit and differential amplifier having stabilized output swing

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0341698A (ja) * 1989-07-10 1991-02-22 Toshiba Corp センス回路
JPH05166365A (ja) * 1991-12-12 1993-07-02 Toshiba Corp ダイナミック型半導体記憶装置
US5347183A (en) * 1992-10-05 1994-09-13 Cypress Semiconductor Corporation Sense amplifier with limited output voltage swing and cross-coupled tail device feedback
JPH06236689A (ja) * 1993-02-08 1994-08-23 Hitachi Ltd 半導体集積回路
US5982673A (en) * 1997-09-30 1999-11-09 Siemens Aktiengesellschaft Secondary sense amplifier with window discriminator for self-timed operation
US6037807A (en) * 1998-05-18 2000-03-14 Integrated Device Technology, Inc. Synchronous sense amplifier with temperature and voltage compensated translator
KR100322539B1 (ko) * 1999-07-10 2002-03-18 윤종용 반도체 집적회로의 감지 증폭장치
US6466501B2 (en) * 2000-06-28 2002-10-15 Hynix Semiconductor Inc. Semiconductor memory device having sense amplifier and method for driving sense amplifier
US20020149400A1 (en) * 2001-04-16 2002-10-17 Namik Kocaman Low voltage differential to single-ended converter
JP2003100992A (ja) * 2001-06-21 2003-04-04 Toshiba Corp センスアンプ
KR100414210B1 (ko) * 2001-11-19 2004-01-13 삼성전자주식회사 반도체 메모리 장치

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276369A (en) * 1989-07-20 1994-01-04 Kabushiki Kaisha Toshiba Sense amplifier circuit having a bias current control means
US5451898A (en) * 1993-11-12 1995-09-19 Rambus, Inc. Bias circuit and differential amplifier having stabilized output swing

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080042691A1 (en) * 2006-08-16 2008-02-21 Vijay Kumar Srinivasa Raghavan High Speed and Power Efficient Sense Amplifier With Leakage Testing and Read Debug Capability
US7545694B2 (en) * 2006-08-16 2009-06-09 Cypress Semiconductor Corporation Sense amplifier with leakage testing and read debug capability
US20090225057A1 (en) * 2007-06-22 2009-09-10 Polak Robert D Colored Morphing Apparatus for an Electronic Device
CN103778944A (zh) * 2012-10-24 2014-05-07 瑞萨电子株式会社 半导体装置
US20150236698A1 (en) * 2014-02-19 2015-08-20 Altera Corporation Stability-enhanced physically unclonable function circuitry
US9577637B2 (en) * 2014-02-19 2017-02-21 Altera Corporation Stability-enhanced physically unclonable function circuitry
CN105070310A (zh) * 2015-08-11 2015-11-18 深圳芯邦科技股份有限公司 一种带失调校正的灵敏放大器
CN108352175A (zh) * 2015-11-30 2018-07-31 德州仪器公司 低功率高性能sram中的感测放大器
CN114078517A (zh) * 2020-08-12 2022-02-22 上海复旦微电子集团股份有限公司 灵敏放大器及存储器

Also Published As

Publication number Publication date
JP4557206B2 (ja) 2010-10-06
TW200514348A (en) 2005-04-16
TWI281779B (en) 2007-05-21
KR100542710B1 (ko) 2006-01-11
DE10361038A1 (de) 2005-04-21
CN1604463A (zh) 2005-04-06
KR20050032664A (ko) 2005-04-08
DE10361038B4 (de) 2014-05-28
US20050219925A1 (en) 2005-10-06
JP2005116143A (ja) 2005-04-28
CN100492892C (zh) 2009-05-27
US7123531B2 (en) 2006-10-17

Similar Documents

Publication Publication Date Title
US7123531B2 (en) Differential amplifier and bit-line sense amplifier adopting the same
US7453751B2 (en) Sample and hold memory sense amplifier
US5434821A (en) Dynamic semiconductor memory device having sense amplifier with compensated offset voltage
US8289796B2 (en) Sense amplifier having loop gain control
US9460760B2 (en) Data-dependent self-biased differential sense amplifier
US7616513B1 (en) Memory device, current sense amplifier, and method of operating the same
US6104655A (en) Semiconductor storage device
US20050281109A1 (en) SRAM memory cell and method for compensating a leakage current flowing into the SRAM memory cell
CN115691587B (zh) 灵敏放大器及控制方法
US6222780B1 (en) High-speed SRAM having a stable cell ratio
US20140354361A1 (en) Sense amplifiers including bias circuits
US6466501B2 (en) Semiconductor memory device having sense amplifier and method for driving sense amplifier
CN114400029B (zh) 读出电路及其方法
US6914836B2 (en) Sense amplifier circuits using a single bit line input
US6411559B1 (en) Semiconductor memory device including a sense amplifier
US20020118577A1 (en) Semiconductor memory device and data read method thereof
JPH0531238B2 (ja)
JP2572557B2 (ja) 低電力高速動作用センス増幅器
US6114881A (en) Current mirror type sense amplifier
JP4046364B2 (ja) 半導体記憶装置およびその動作方法
US20050135161A1 (en) Semiconductor readout circuit
US6819614B2 (en) Semiconductor memory device and sensing control method having more stable input/output line sensing control
US7233524B2 (en) Sense amplifier circuit
KR100436127B1 (ko) 센스앰프를 포함하는 반도체 메모리 장치 및 센스앰프구동 방법
JPH06314490A (ja) 半導体ｉｃチップ内蔵用のデータアンプ

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RHO, KWANG MYOUNG;REEL/FRAME:015077/0455

Effective date: 20031101

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION