US20040242132A1 - Polishing element, cmp polishing device and productionj method for semiconductor device - Google Patents

Polishing element, cmp polishing device and productionj method for semiconductor device Download PDF

Info

Publication number
US20040242132A1
US20040242132A1 US10/467,627 US46762703A US2004242132A1 US 20040242132 A1 US20040242132 A1 US 20040242132A1 US 46762703 A US46762703 A US 46762703A US 2004242132 A1 US2004242132 A1 US 2004242132A1
Authority
US
United States
Prior art keywords
polishing
mentioned
dimensions
elastic member
hard elastic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/467,627
Other languages
English (en)
Inventor
Susumu Hoshino
Yutaka Uda
Isao Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nikon Corp
Original Assignee
Nikon Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nikon Corp filed Critical Nikon Corp
Assigned to NIKON CORPORATION reassignment NIKON CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOSHINO, SUSUMU, SUGAYA, ISAO, UDA, YUTAKA
Publication of US20040242132A1 publication Critical patent/US20040242132A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/11Lapping tools
    • B24B37/20Lapping pads for working plane surfaces
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24DTOOLS FOR GRINDING, BUFFING OR SHARPENING
    • B24D13/00Wheels having flexibly-acting working parts, e.g. buffing wheels; Mountings therefor
    • B24D13/20Mountings for the wheels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation

Definitions

  • the present invention relates to a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, a polishing body which is used in this CMP polishing apparatus, and a semiconductor device manufacturing method which uses this CMP polishing apparatus.
  • FIG. 9 is a schematic diagram illustrating planarization techniques used in a semiconductor manufacturing process, and shows sectional views of a semiconductor device.
  • 31 indicates a silicon wafer
  • 32 indicates an inter-layer insulating film consisting of S i O 2
  • 33 indicates a metal film consisting of Cu
  • 34 indicates the semiconductor device.
  • FIG. 9( a ) shows an example of the planarization of an inter-layer insulating film 32 on the surface of the semiconductor device.
  • FIG. 9( b ) shows an example in which a so-called damascene is formed by polishing the metal film 33 on the surface of the semiconductor device.
  • a chemical mechanical polishing or chemical mechanical planarization (hereafter referred to as “CMP”) technique is widely used as a method for planarizing the surfaces of such semiconductor devices.
  • CMP chemical mechanical polishing or chemical mechanical planarization
  • CMP was developed on the basis of silicon wafer mirror surface polishing methods, and is performed using a CMP apparatus of the type shown in FIG. 10.
  • 35 indicates a polishing member
  • 36 indicates a member that holds the object of polishing (hereafter referred to as a “polishing head” in some instances)
  • 37 indicates a silicon wafer which is the object of polishing
  • 38 indicates a polishing agent supply part
  • 39 indicates a polishing agent.
  • the polishing member 35 has a polishing pad 41 which is attached to the surface of a polishing platen 40 .
  • a sheet-form foam polyurethane is widely used as such a polishing pad 41 .
  • the object of polishing 37 is held by the polishing head 36 , so that it is caused to oscillate while being rotated, and is pressed against the polishing pad 41 of the polishing member 35 with a specified pressure.
  • the polishing member 35 is also rotated, so that a relative motion is performed between the polishing member 35 and the object of polishing 37 .
  • the polishing agent 39 is supplied to the surface of the polishing pad 41 from the polishing agent supply part 38 .
  • the polishing agent 39 diffuses over the surface of the polishing pad 41 , and enters the space between the polishing pad 41 and the object of polishing 37 as the polishing member 35 and object of polishing 37 move relative to each other, so that the surface of the object of polishing 37 that is to be polished is polished.
  • good polishing is accomplished by a synergistic effect of the mechanical polishing caused by the relative motion of the polishing member 35 and object of polishing 37 and the chemical action of the polishing agent 39 .
  • a method has been developed in which a polishing body is formed by pasting together a polishing pad and a soft pad, and this polishing body is used instead of the polishing pad 41 shown in FIG. 10.
  • a polishing body 44 is formed by pasting together a polishing pad 42 and a pad 43 which has a low elastic modulus and a large compressive deformation rate, and this polishing body 44 is attached to the polishing platen 40 .
  • polishing of the type shown in FIG. 10 when polishing of the type shown in FIG. 10 is performed, the pad 43 is caused to undergo compressive deformation by the force that is applied to the large undulation of the wafer 37 via the polishing pad 42 , so that the polishing pad 42 also deforms in conformity to this deformation. Accordingly, polishing can be performed in which the amount of polishing is fixed in accordance with the undulation in the surface of the wafer 37 . Meanwhile, in the case of local indentations and projections, the deformation of the polishing pad 42 is relatively small; accordingly, such indentations and projections can be removed by polishing.
  • the present invention was devised in order to solve such problems.
  • the object of the present invention is to provide a polishing body which can satisfy both the requirements of “wafer global removal uniformity” and the requirements of “local pattern planarity” even in cases where wafers are polished which have patterns that use a wiring rule of 0.1 ⁇ m or less or patterns that have a severe density distribution are formed inside, a CMP polishing apparatus using this polishing body, and a semiconductor device manufacturing method using such a CMP apparatus.
  • the first invention of the present application which is used to achieve the above-mentioned object is a polishing body for a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, wherein a polishing pad, a hard elastic member and a soft member are laminated in that order, and the above-mentioned hard elastic member is constructed so that the amount of deformation of this member at the polishing load that is applied during polishing is smaller than the step difference permitted in the above-mentioned wafer in an interval corresponding to the maximum pattern of the above-mentioned semiconductor integrated circuits, and is greater than the TTV permitted in the above-mentioned wafer in the interval corresponding to one chip.
  • TTV total thickness variation
  • FIG. 1( a ) shows a sectional view of the wafer prior to polishing.
  • 1 indicates the wafer substrate
  • 2 indicates patterns consisting of circuits and wiring
  • 3 indicates an inter-layer insulating layer.
  • the patterns 2 consisting of circuits and wiring are formed on the surface of the substrate 1
  • the inter-layer insulating layer 3 is formed on top of this, so that the patterns 2 consisting of circuits and wiring are insulated from each other.
  • the interval corresponding to the maximum pattern of the semiconductor integrated circuits refers to the interval corresponding to the distance a of the recessed part of the inter-layer insulating film 3 that covers the patterns 2 of circuits and wiring that are most separated from each other within one chip.
  • the interval corresponding to the maximum pattern of such semiconductor integrated circuits is approximately 4 mm.
  • FIG. 1( b ) shows a single wafer, with a plurality of chips 5 being formed on this wafer 1 .
  • the interval corresponding to one chip refers to the interval corresponding to one side b in a case where the shape of the chip is square. Currently, this interval is approximately 20 mm. In cases where the shape of the chip is not square, or in cases where chips of different dimensions are formed on one wafer, this interval refers to the distance corresponding to the largest side.
  • the hard elastic member refers to an elastic member with a Young's modulus of 10,000 Kg/mm 2 or greater; metal members may be cited as typical examples.
  • the soft member refers to a member that has a compression rate of 10% or greater when a pressure of 1 Kg/cm 2 is applied; chloroprene rubber members containing air bubbles, or elastic nonwoven fabrics, may be cited as typical examples.
  • a hard elastic member is sandwiched between the polishing pad and a soft member. Furthermore, the amount of deformation of this hard elastic member at the load that is applied during polishing is set so that this amount of deformation is smaller than the step difference that is permitted in the above-mentioned wafer in the interval corresponding to the maximum pattern of the above-mentioned semiconductor integrated circuits. Accordingly, since the hard elastic member is not subjected to deformation exceeding the permitted step difference in the interval corresponding to the maximum pattern, “local pattern planarity” is ensured.
  • the amount of deformation of the hard elastic member at the polishing load that is applied during polishing is set so that this amount of deformation is greater than the TTV permitted in the wafer in the interval corresponding to one chip. Accordingly, the hard elastic member can deform in conformity to the step difference over the distance corresponding to one chip, and the polishing pad also shows a corresponding deformation in conformity to these step differences, so that a uniform amount of polishing can be performed in accordance with these step differences. Consequently, “wafer global removal uniformity” is ensured.
  • the second invention of the present application that is used to achieve the above-mentioned object is the polishing body of the first invention, wherein the above-mentioned hard elastic member is constructed from a metal plate that will not dissolve in the polishing agent.
  • the material of the above-described hard elastic member there are no particular stipulations regarding the material of the above-described hard elastic member. Accordingly, a hard plastic or hard rubber, for example, can be used. However, a hard plastic or hard rubber, etc., has a small Young's modulus; accordingly, if such a material is used in the above-described first invention, the thickness of the member must be set at a large value. If this thickness is increased, the degree of parallel orientation of the two surfaces deteriorates; furthermore, irregularities in thermal expansion occur as a result of temperature irregularities caused by the heat generated during polishing, and such irregularities cause a deterioration in planarity.
  • the above-described hard elastic member is formed from a metal, the Young's modulus of the hard elastic member is high; accordingly, the thickness of this member can be reduced. Consequently, the degree of parallel orientation of the two surfaces can be maintained at a favorable value, and irregularities in thermal expansion can be reduced, so that the planarity can be maintained at a favorable value. Furthermore, the reason that the type of metal used is limited to a metal that will not dissolve in the polishing agent is as follows: specifically, if the metal dissolves in the polishing agent, there may be cases in which this has a deleterious effect on the semiconductor integrated circuits that are formed on the wafer. Stainless steel and titanium may be cited as examples of metals that will not dissolve in commonly used polishing agents.
  • the third invention of the present application that is used to achieve the above-mentioned object is the polishing body of the above-mentioned second invention, wherein the above-mentioned metal plate is a stainless steel plate, and the thickness h of this plate is such that 0.1 mm ⁇ h ⁇ 0.94 mm.
  • the effect described in the above-mentioned first means can be obtained; furthermore, the effect described in the above-mentioned second means can also be obtained.
  • a stainless steel plate is readily available, and is less expensive than other materials.
  • the fourth invention of the present application that is used to achieve the above-mentioned object is a polishing body for a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, wherein a polishing pad, a hard elastic member and a soft member are laminated in that order, and these parts are constructed so that the combined amount of deformation of the polishing pad, hard elastic member and soft member at the polishing load that is applied during polishing is smaller than the height of the indentations and projections of the above-mentioned maximum pattern in the interval corresponding to the maximum pattern of the above-mentioned semiconductor integrated circuits, and is greater than five times the TTV that is permitted in the above-mentioned wafer.
  • the term “height of the indentations and projections of the maximum pattern” refers to the depth of the recessed part corresponding to portion a in FIG. 1( a ).
  • a hard elastic member is sandwiched between the polishing pad and a soft member. Furthermore, the combined amount of deformation of the polishing pad, hard elastic member and soft member at the polishing load that is applied during polishing is smaller than the height of the indentations and projections of the above-mentioned maximum pattern in the interval corresponding to the maximum pattern of the above-mentioned semiconductor integrated circuits. Accordingly, since the polishing body is not subjected to deformation exceeding the height of the indentations and projections of the maximum pattern in the interval corresponding to the maximum pattern, the step difference between patterns following polishing can be suppressed to a difference that is less than the height of the indentations and projections of the maximum pattern. Consequently, “local pattern planarity” is ensured.
  • the combined amount of deformation of the polishing pad, hard elastic member and soft member at the polishing load that is applied during polishing is set so that this amount of deformation is greater than five times the TTV that is permitted in the wafer in the interval corresponding to one chip.
  • the amount of deformation of the polishing body must be five times the required TTV or greater if “wafer global removal uniformity” is to be obtained.
  • the polishing pad As a result of the combined amount of deformation of the polishing pad, hard elastic member and soft member being set so that this amount of deformation is greater than five times the TTV that is permitted in the wafer in the interval corresponding to one chip, the polishing pad also deforms in conformity to the step differences in cases where there are step differences in the distance corresponding to one chip. Accordingly, a uniform amount of polishing can be performed in accordance with these step differences. Consequently, “wafer global removal uniformity” is ensured.
  • the fifth invention of the present application that is used to achieve the above-mentioned object is the polishing body of the above-mentioned fourth invention, wherein the above-mentioned hard elastic member is constructed from a metal plate that will not dissolve in the polishing agent.
  • the material of the above-mentioned hard elastic member there are no particular stipulations regarding the material of the above-mentioned hard elastic member. Accordingly, a hard plastic or hard rubber, for example, can be used. However, since hard plastics and hard rubbers, etc., have a small Young's modulus, the thickness must be increased if such materials are used in the above-mentioned fourth means. When the thickness increases, the degree of parallel orientation of the two surfaces deteriorates; furthermore, irregularities in thermal expansion occur as a result of temperature irregularities caused by the heat generated during polishing, and such irregularities cause a deterioration in planarity.
  • the Young's modulus is high; accordingly, the thickness of the member can be reduced. Consequently, the degree of parallel orientation of the two surfaces can be maintained at a favorable value, and irregularities in thermal expansion can also be reduced, so that the planarity can be maintained at a favorable value.
  • the reason that the type of metal used is limited to a metal that will not dissolve in the polishing agent is as follows: specifically, if the metal dissolves in the polishing agent, there are cases in which this has a deleterious effect on the semiconductor integrated circuits that are formed on the wafer. Examples of metals that will not dissolve in commonly used polishing agents include stainless steel and titanium.
  • the sixth invention of the present application that is used to achieve the above-mentioned object is the polishing body of the fifth invention, wherein the above-mentioned polishing pad consists of a urethane foam material, the above-mentioned metal plate is a stainless steel plate, the thickness of the above-mentioned polishing pad is 0.1 to 3 mm, the thickness of the above-mentioned metal body is 0.05 to 0.6 mm, and the thickness of the above-mentioned soft member is 0.5 to 2.5 mm.
  • the above-mentioned polishing pad consists of a urethane foam material
  • the above-mentioned metal plate is a stainless steel plate
  • the thickness of the above-mentioned polishing pad is 0.1 to 3 mm
  • the thickness of the above-mentioned metal body is 0.05 to 0.6 mm
  • the thickness of the above-mentioned soft member is 0.5 to 2.5 mm.
  • a urethane foam material is superior as the material of a polishing pad; furthermore, a stainless steel plate is easy to obtain, and is less expensive than other materials. In cases where such materials are used, as will be described in the embodiments later, the requirements of both “wafer global removal uniformity” and “local pattern planarity” can be satisfied under advantageous conditions by setting the thicknesses of the polishing pad, metal plate and soft member as described above.
  • the thickness of the polishing pad is less than 0.1 mm, the grooves used to conduct the slurry, which are ordinarily formed in the polishing pad, are eliminated.
  • the thickness of the polishing pad is limited to a thickness of 0.1 mm or greater. Furthermore, even if the thickness of the polishing pad exceeds 3 mm, no particular advantage is gained, and there is no great difference between such a polishing body and a polishing body in which no metal plate is sandwiched between the other parts as described above; accordingly, in the present means, the thickness of the polishing pad is limited to a thickness of 3 mm or less.
  • the thickness of the metal body is limited to a thickness of 0.05 mm or greater.
  • the thickness of the metal body exceeds 0.6 mm, the limiting conditions of the above-mentioned fourth invention cannot be realized in the case of a wafer with a TTV of 1 ⁇ m; accordingly, in the present means, the thickness of the metal body is limited to a thickness of 0.6 mm or less.
  • the thickness of the soft member does not greatly affect the “wafer global removal uniformity” or “local pattern planarity.”
  • an experiment (simulation) for the purpose of deriving the limits on the above-mentioned respective numerical values in the present invention was conducted in the range of 0.5 to 2.5 mm, the thickness is limited to this range.
  • the seventh invention of the present application that is used to achieve the above-mentioned object is the polishing body of any of the above-mentioned first through sixth inventions, wherein the above-mentioned soft member has a torsional strength which is such that this member is not damaged when the member rotates with a load applied during polishing.
  • the above-mentioned soft member has a torsional strength which is such that this member is not damaged when the member rotates with a load applied during polishing; accordingly, polishing can be performed smoothly.
  • the eighth invention of the present application that is used to achieve the above-mentioned object is the polishing body of any of the above-mentioned first through seventh inventions, wherein the above-mentioned hard elastic member and soft member are fastened by bonding, and the above-mentioned hard elastic member and polishing pad are fastened by vacuum suction.
  • the polishing pad can easily be replaced when the polishing pad becomes worn.
  • the ninth invention of the present application that is used to achieve the above-mentioned object is the polishing body of any of the above-mentioned first through seventh inventions, wherein the above-mentioned hard elastic member and soft member are fastened by bonding means with a strong peeling strength, and the above-mentioned hard elastic member and polishing pad are fastened by bonding means with a weak peeling strength.
  • the polishing pad can be peeled from the hard elastic member in a state in which the hard elastic member and soft member remain bonded. Accordingly, the polishing pad can easily be replaced when the polishing pad becomes worn.
  • the tenth invention of the present application that is used to achieve the above-mentioned object is a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, and which has the polishing body of any of the above-mentioned first through ninth inventions.
  • the eleventh invention of the present application that is used to achieve the above-mentioned object is a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, and which has the polishing body of the above-mentioned eighth or ninth invention, wherein the dimensions of the above-mentioned polishing pad are set so that these dimensions are smaller than the dimensions of the wafer that is being polished.
  • CMP polishing apparatuses There are two types of CMP polishing apparatuses, i.e., apparatuses in which the dimensions of the polishing pad are larger than the dimensions of the wafer that is being polished, and apparatuses in which the dimensions of the polishing pad are smaller than the dimensions of the wafer that is being polished.
  • the polishing body of the above-mentioned eighth or ninth invention is used in the latter type of apparatus. Accordingly, since the size of the polishing body pad is small, attachment by vacuum suction can easily be accomplished, so that the polishing pad can be securely fastened to the hard elastic member. Furthermore, in such a CMP apparatus, since the polishing pad is small, frequent replacement of the polishing pad is necessary. Accordingly, an especially great effect is obtained by using the polishing body of the above-mentioned eighth or ninth invention, in which replacement of the polishing pad is easy.
  • the twelfth invention of the present application that is used to achieve the above-mentioned object is a CMP polishing apparatus which is used to polish wafers that have semiconductor integrated circuits formed inside, and which has the polishing body of the above-mentioned seventh invention, wherein the dimensions of the above-mentioned polishing pad are set so that these dimensions are smaller than the dimensions of the wafer that is being polished, and the permissible shear stress of the above-mentioned soft member is greater than 0.5 Kg/cm 2 .
  • the above-mentioned soft member can be endowed with a torsional strength which is such the member is not damaged when the member rotates with a load applied during polishing, by setting the permissible shear stress of the above-mentioned soft member at a value that is greater than 0.5 Kg/cm 2 .
  • the thirteenth invention of the present application that is used to achieve the above-mentioned object is a semiconductor device manufacturing method which is characterized in that this method has a process in which the polishing of wafers is performed using the CMP polishing apparatus of any of the abovementioned tenth through twelfth inventions.
  • wafers can be polished while satisfying the requirements of both “wafer global removal uniformity” and “local pattern planarity,” which are required in the polishing of wafers that have semiconductor devices formed inside. Accordingly, a semiconductor exposure apparatus which has a shallow focal depth can be used, and semiconductor devices that have fine patterns can be manufactured with a good yield.
  • FIG. 1 is a diagram which shows the interval corresponding to the maximum pattern of the semiconductor integrated circuits, and the interval corresponding to one chip.
  • FIG. 2 is a diagram which shows an outline of a CMP polishing apparatus and polishing body constituting one example of a working configuration of the present invention.
  • FIG. 3 is a graph which shows the relationship between the surface pressure (polishing pressure) p and the maximum shear stress ⁇ max of the soft member in one working configuration of the present invention.
  • FIG. 4 is a diagram which shows an outline (sectional view) of a polishing body constituting another working configuration of the present invention.
  • FIG. 5 is a flow chart which shows a semiconductor device manufacturing process constituting one example of a working configuration of the present invention.
  • FIG. 6 is a diagram which shows an outline of a polishing body used in a simulation model in embodiments of the present invention and comparative examples.
  • FIG. 7 is a graph which shows one example of the results obtained in a simulation of the “local pattern planarity.”
  • FIG. 8 is a graph which shows one example of the results obtained in a simulation of the “wafer global removal uniformity.”
  • FIG. 9 is a schematic diagram of the planarization technique in a semiconductor manufacturing process.
  • FIG. 10 is a diagram which shows an outline of a CMP apparatus.
  • FIG. 11 is a diagram which shows an example in which a polishing body is formed by pasting together a polishing pad and a soft pad.
  • FIG. 2( a ) is a diagram which shows an outline of a CMP polishing apparatus and a polishing body constituting one example of a working configuration of the present invention.
  • FIG. 2( b ) is an enlarged view of the portion labeled A in FIG. 2( a ).
  • the size of the polishing pad is smaller than the size of the wafer, unlike the case of the conventional CMP apparatus shown in FIG. 10.
  • the wafer 11 that is the object of polishing is held by a polishing head 12 , and rotates together with the polishing head 12 .
  • a polishing body 14 is attached to the polishing member 13 by bonding using an adhesive agent or two-sided adhesive tape, etc.
  • the polishing body 14 is constructed by laminating a soft member 15 , a hard elastic member 16 and a polishing pad 17 .
  • the soft member 15 , hard elastic member 16 and polishing pad 17 are bonded by means of an adhesive agent or two-sided adhesive tape, etc.
  • the polishing body 14 rotates together with the polishing member 13 , and swings at the same time; as a result, the polishing pad 17 polishes the entire surface of the wafer 11 .
  • a polishing agent is supplied to the area between the wafer 11 and the polishing pad 17 ; however, this is not shown in the figures.
  • the thickness of the hard elastic member 16 is determined so that the amount of deformation of the hard elastic member 16 caused by the load during polishing is smaller than the step difference that is permitted in the wafer in the interval corresponding to the maximum pattern of the semiconductor integrated circuits, and is larger than the TTV that is permitted in the wafer in the interval corresponding to one chip.
  • the maximum amount of deformation w can be expressed as follows by universally known calculations for a beam:
  • the thickness h that satisfies the above-mentioned conditions is a thickness which is such that 0.20 mm ⁇ h ⁇ 0.62 mm. If a hard plastic with a Young's modulus E of 400 Kg/mm 2 is used instead of stainless steel, the thickness h is such that 0.74 mm ⁇ h ⁇ 2.32 mm. If the thickness is too great, there are many inconveniences as described above; accordingly, it is desirable to use a metal which allows a small thickness as the hard elastic member.
  • Table 1 shows the relationship between the surface pressure during polishing and the limiting conditions on the thickness h in a cases where stainless steel is used as the material of the hard elastic member 16 .
  • the permitted step difference in the case of a 0.35 ⁇ m wiring rule is set at 0.35 ⁇ m, and the TTV is set at 5 ⁇ m.
  • a member which has a large compressive deformation and which tends not to undergo plastic deformation is desirable to use as the soft member 15 .
  • a chloroprene rubber, etc., which has air bubbles inside can be used as the material of this member.
  • this material it is desirable that this material have a torsional strength which is such that the member is not damaged when the member rotates with a load applied during polishing.
  • the polishing pad 17 will conform to large undulations corresponding to one chip, so that polishing in which the amount of polishing is fixed can be performed, with the polishing pad 17 showing almost no deformation in the case of local indentations and projections with a spacing corresponding to the maximum spacing of the wiring pattern; accordingly, the requirements of both “wafer global removal uniformity” and “local pattern planarity” can be satisfied.
  • stainless steel can be used as the material of the hard elastic member 16 , and the thicknesses of the respective members can be determined so that the combined deformation of the polishing pad 17 , hard elastic member 16 and soft member 15 caused by the load during polishing is smaller than the height of the indentations and projections of the maximum pattern in the interval corresponding to the maximum pattern of the semiconductor integrated circuits, and greater than five times the TTV permitted in the wafer in the interval corresponding to one chip in this working configuration.
  • a member which shows a large compressive deformation and which tends not to undergo plastic deformation is desirable as the soft member 15 .
  • a chloroprene rubber which has air bubbles inside, or an elastic nonwoven fabric, etc. can be used.
  • the polishing pad 17 will conform to large undulations corresponding to one chip, so that polishing in which the amount of polishing is fixed can be performed, with the polishing body 14 showing almost no deformation in the case of local indentations and projections with a spacing corresponding to the maximum spacing of the wiring pattern; accordingly, the requirements of both “wafer global removal uniformity” and “local pattern planarity” can be satisfied.
  • the graph in FIG. 3 shows the results obtained when the relationship between the surface pressure (polishing pressure) p (kg/cm 2 ) and the maximum shear stress ⁇ max (kg/cm 2 ) was determined by calculation in a cases where a polishing pad with an external diameter D of 170 mm and an internal diameter d of 60 mm was used in the CMP polishing apparatus shown in FIG. 2, and the coefficient of friction k was 0.35.
  • a polishing pad with an external diameter D of 170 mm and an internal diameter d of 60 mm was used in the CMP polishing apparatus shown in FIG. 2, and the coefficient of friction k was 0.35.
  • FIG. 3 in a CMP polishing apparatus of the type shown in FIG.
  • the soft member 15 can be endowed with a torsional strength which is such that the soft member 15 is not damaged under ordinary polishing conditions (polishing pressure: 1.0 Kg/cm 2 ) if the maximum shear stress E max permitted in the soft member 15 is greater than 0.5 Kg/cm 2 .
  • FIG. 4 shows an outline (sectional view) of a polishing body constituting another working configuration of the present invention.
  • constituent elements that are the same as constituent elements shown in FIG. 2 are labeled with the same symbols, and a description of such elements is omitted.
  • the working configuration shown in FIG. 4 as well, the basic construction and the materials of the soft member 15 , hard elastic member 16 and polishing pad 17 are the same as those shown in FIG. 1.
  • the soft member 15 is bonded to the polishing member 13 by an adhesive agent or two-sided adhesive tape
  • the hard elastic member 16 is bonded to the soft member 15 by an adhesive tape or two-sided adhesive tape.
  • the hard elastic member 16 and the polishing pad 17 are not bonded.
  • holes 18 are formed which pass through the polishing member 13 , soft member 15 and hard elastic member 16 , and the polishing pad 17 is fastened to the hard elastic member 16 through vacuum suction by setting the pressure inside these holes 18 at a low pressure that is close to a vacuum in a state in which the polishing pad 17 is pressed against the hard elastic member 16 .
  • the polishing pad 17 can easily be removed merely by releasing the vacuum state in cases where the polishing pad 17 is to be replaced as a result of wear, so that replacement is easy.
  • the number of holes 18 required is small, so that a vacuum suction mechanism can easily be provided; accordingly, such a construction is effective.
  • the frequency of replacement is high; accordingly, the construction shown in FIG. 4 is effective in this respect as well.
  • the polishing pad 17 can easily be peeled from the hard elastic member 16 by using bonding means with a strong peeling strength between the polishing member 13 and soft member 15 and between the soft member 15 and hard elastic member 16 , and using bonding means with a weak peeling strength between the hard elastic member 16 and polishing pad 17 .
  • the worn polishing pad 17 can easily be replaced in the same manner as in the above-mentioned working configuration in which a vacuum suction attachment mechanism was provided.
  • the 180° peeling adhesive strength of the adhesive layers between the polishing member 13 and soft member 15 and between the soft member 15 and the hard elastic member 16 be greater than 1500 g/25 mm, and that the 180° peeling adhesive strength of the adhesive layer between the hard elastic member 16 and the polishing pad 17 be smaller than 1000 g/25 mm.
  • FIG. 5 is a flow chart which shows a semiconductor device manufacturing process constituting one example of a working configuration of the present invention. After the semiconductor device manufacturing process is started, the appropriate processing step is first selected in step S 100 from the steps S 101 through S 104 described below. In accordance with this selection, the processing proceeds to one of the steps S 101 through S 104 .
  • Step S 101 is an oxidation step in which the surface of the silicon wafer is oxidized.
  • Step S 102 is a CVD step in which an insulating film is formed on the surface of the silicon wafer by CVD, etc.
  • Step S 103 is an electrode formation step in which electrodes are formed on the silicon wafer by a process such as vacuum evaporation.
  • Step S 104 is an ion injection step in which ions are injected into the silicon wafer.
  • step S 105 a judgement is made as to whether or not a CMP process is to be performed, and in cases where such a process is to be performed, the processing proceeds to the CMP process of step S 106 . In cases where a CMP process is not to be performed, step S 106 is bypassed.
  • the CMP process the flattening of inter-layer insulation films, or the formation of a damascene by the polishing of metal films on the surfaces of semiconductor devices, etc., is performed using the polishing apparatus of the present invention.
  • Step S 107 is a photolithographic step.
  • the silicon wafer is coated with a resist, circuit patterns are burned onto the silicon wafer by exposure using an exposure apparatus, and the exposed silicon wafer is developed.
  • the next step S 108 is an etching step in which the portions other than the developed resist image are removed by etching, the resist is then peeled away, and the resist that has become unnecessary following etching is removed.
  • step S 109 a judgement is made as to whether or not all of the necessary steps have been completed. If these steps have not been completed, the processing returns to step S 100 , and the subsequent steps are repeated, so that circuit patterns are formed on the silicon wafer. If it is judged in step S 109 that all of the steps have been completed, the process is ended.
  • FIG. 6( a ) shows the polishing body that was used as the simulation model.
  • a body having the shape of a rectangular solid was envisioned as the polishing body.
  • SUBA 22 an elastic nonwoven fabric
  • SUS plate 23 stainless steel
  • IC 1000 24 a foam urethane
  • the IC 1000 corresponds to the polishing pad
  • the SUS corresponds to the hard elastic member
  • the SUBA corresponds to the soft member.
  • the polishing surface had a square shape with dimensions of 2 L on a side, and it was envisioned that this type of polishing body was pressed against the object of polishing with a commonly used pressure of 200 gf/cm 2 .
  • the amount of recession of the IC 1000 (amount of recession of the pad) ⁇ h shown in FIG. 5( b ) was calculated with the thicknesses of the IC 1000 , SUS plate and SUBA varied. Furthermore, in a case where the “wafer global removal uniformity” was evaluated with the thickness of the Al fixed at 15 mm, L was set equal to 20 mm. This envisioned an extreme case in which the entire pattern of a typical chip constituted a recessed part. Furthermore, when the “local pattern planarity” was evaluated, L was set equal to 4 mm. The reason for this is that the envisioned maximum pattern interval was approximately 4 mm.
  • FIG. 7 shows one example of the results of a simulation of the “local pattern planarity.”
  • the horizontal axis in the figure shows the thickness of the IC 1000
  • the vertical axis shows the amount of recession of the IC 1000 (amount of recession of the pad) Ah.
  • the curve indicated by a represents data for a case (single layer) in which the IC 1000 was pasted directly to the Al base without installing an SUS plate or SUBA.
  • the curve indicated by b represents data for a case (two layers) in which an SUBA was pasted to the Al base, and the IC 1000 was pasted directly to the SUBA without installing an SUS plate.
  • the curves indicated by c(x) represent data for cases (three layers) in which an SUBA was pasted to the Al base, an SUS plate with a thickness of x mm was pasted to the surface of the SUBA, and the IC 1000 was pasted to the surface of the SUS plate. In cases where an SUBA was installed, the thickness was 1.27 mm in all instances.
  • “Local pattern planarity” is considered to be improved as the amount of recession of the pad is smaller. In the case of a single layer, extremely good data are obtained. On the other hand, in the case of two layers, the amount of recession of the pad is large, and shows an abrupt increase especially in cases where the thickness of the IC 1000 is small, which is undesirable. In the case of three layers, the amount of recession of the pad decreases as the thickness of the SUS plate is increased.
  • FIG. 8 shows one example of the results of a simulation of “wafer global removal uniformity.”
  • the horizontal axis and vertical axis of the figure and the meanings of the curves in the figure are the same as in FIG. 7. Furthermore, in cases where an SUBA was installed, the thickness was 1.27 mm in all instances.
  • the thickness of the IC 1000 is set at 3 mm or less as described above, this standard clearly cannot be satisfied in the case of a single layer, and even in cases where three layers are formed, this standard cannot be satisfied if the thickness of the IC 1000 is small, unless the thickness of the SUS plate is 0.6 mm or less. Accordingly, it is desirable that the thickness of the SUS plate be set at 0.6 mm or less.
  • FIGS. 7 and 8 are data that were obtained in a case where the thickness of the SUBA was set at 1.27 mm as described above. In the simulation, the thickness of the SUBA was varied from 0.5 to 2.5 mm; however, the variation in the amount of recession of the pad caused by this variation in thickness was small. It is thought that the reason for this is as follows: specifically, since SUBA is a soft material, there is little effect on the amount of recession of the pad even if the thickness of the SUBA is varied.
  • the polishing body and CMP polishing apparatus of the present invention can be used to polish wafers that have semiconductor circuit patterns in a semiconductor device manufacturing process. Furthermore, the semiconductor manufacturing method of the present invention can be used to manufacture semiconductor devices that have fine patterns.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
US10/467,627 2001-07-19 2002-07-04 Polishing element, cmp polishing device and productionj method for semiconductor device Abandoned US20040242132A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001-219431 2001-07-19
JP2001219431 2001-07-19
PCT/JP2002/006780 WO2003009362A1 (fr) 2001-07-19 2002-07-04 Element de polissage, dispositif de polissage mecano-chimique (cmp) et procede de production de dispositif a semi-conducteur

Publications (1)

Publication Number Publication Date
US20040242132A1 true US20040242132A1 (en) 2004-12-02

Family

ID=19053436

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/467,627 Abandoned US20040242132A1 (en) 2001-07-19 2002-07-04 Polishing element, cmp polishing device and productionj method for semiconductor device

Country Status (7)

Country Link
US (1) US20040242132A1 (ko)
EP (1) EP1408538A4 (ko)
JP (1) JPWO2003009362A1 (ko)
KR (1) KR100564125B1 (ko)
CN (1) CN1224082C (ko)
TW (1) TW537945B (ko)
WO (1) WO2003009362A1 (ko)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060219662A1 (en) * 2005-03-30 2006-10-05 Fujitsu Limited Fabrication process of semiconductor device and polishing method
US20070218288A1 (en) * 2006-03-14 2007-09-20 Harald Richter Adapter plate for supporting a vacuum suction device
US9118395B2 (en) 2010-09-09 2015-08-25 Infineon Technologies Ag Chip comprising a radio frequency switch arrangement, circuit arrangement and method for producing a radio frequency circuit arrangement
JP2018051679A (ja) * 2016-09-28 2018-04-05 株式会社ディスコ 研磨ユニット

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004023009A (ja) 2002-06-20 2004-01-22 Nikon Corp 研磨体、研磨装置、半導体デバイス及び半導体デバイス製造方法
JP4937538B2 (ja) * 2005-07-13 2012-05-23 ニッタ・ハース株式会社 研磨布固定用の両面粘着テープおよびこれを備えた研磨布
KR101247065B1 (ko) * 2006-01-30 2013-03-25 엠이엠씨 일렉트로닉 머티리얼즈, 인크. 양면 웨이퍼 그라인더 및 가공물 나노토폴로지 평가 방법
JP4998824B2 (ja) * 2007-06-12 2012-08-15 株式会社ニコン 研磨パッドのサイズ設定方法
KR100901982B1 (ko) * 2007-07-12 2009-06-08 주식회사 실트론 접착강도 시험장치
EP2242614A4 (en) * 2007-12-31 2013-01-16 Innopad Inc CHEMICAL MECHANICAL PLANARIZATION CUSHION
KR101596561B1 (ko) * 2014-01-02 2016-03-07 주식회사 엘지실트론 웨이퍼 연마 장치
CN105500186A (zh) * 2016-01-21 2016-04-20 苏州新美光纳米科技有限公司 晶片抛光用抛光垫及抛光垫的自吸附方法
JP6986930B2 (ja) 2017-11-07 2021-12-22 株式会社荏原製作所 基板研磨装置および研磨方法
WO2020115867A1 (ja) * 2018-12-06 2020-06-11 三菱電機株式会社 Osr貼り付け装置及びosr貼り付け方法
CN109648463B (zh) * 2018-12-14 2021-04-23 厦门大学 一种半导体晶片光电化学机械抛光加工方法
CN113414717A (zh) * 2021-08-05 2021-09-21 燕山大学 一种复合杯形抛光轮及其抛光方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287663A (en) * 1992-01-21 1994-02-22 National Semiconductor Corporation Polishing pad and method for polishing semiconductor wafers
US5564965A (en) * 1993-12-14 1996-10-15 Shin-Etsu Handotai Co., Ltd. Polishing member and wafer polishing apparatus
US5882251A (en) * 1997-08-19 1999-03-16 Lsi Logic Corporation Chemical mechanical polishing pad slurry distribution grooves
US5921856A (en) * 1997-07-10 1999-07-13 Sp3, Inc. CVD diamond coated substrate for polishing pad conditioning head and method for making same
US5931724A (en) * 1997-07-11 1999-08-03 Applied Materials, Inc. Mechanical fastener to hold a polishing pad on a platen in a chemical mechanical polishing system
US5944582A (en) * 1993-11-16 1999-08-31 Applied Materials, Inc. Chemical mechanical polishing with a small polishing pad
US6077153A (en) * 1996-11-29 2000-06-20 Sumitomo Metal Industries, Limited Polishing pad and apparatus for polishing a semiconductor wafer
US6099954A (en) * 1995-04-24 2000-08-08 Rodel Holdings, Inc. Polishing material and method of polishing a surface
US6402591B1 (en) * 2000-03-31 2002-06-11 Lam Research Corporation Planarization system for chemical-mechanical polishing
US6561889B1 (en) * 2000-12-27 2003-05-13 Lam Research Corporation Methods for making reinforced wafer polishing pads and apparatuses implementing the same
US6616520B1 (en) * 1998-08-28 2003-09-09 Nitta Corporation Polishing cloth and method for attaching/detaching the polishing cloth to/from polishing machine base plate

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2891083B2 (ja) * 1993-12-14 1999-05-17 信越半導体株式会社 シート状研磨部材およびウエーハ研磨装置
JPH0950974A (ja) * 1995-08-07 1997-02-18 Sony Corp 研磨布及び半導体装置の製造方法
US5692950A (en) * 1996-08-08 1997-12-02 Minnesota Mining And Manufacturing Company Abrasive construction for semiconductor wafer modification
JP3152188B2 (ja) * 1997-11-28 2001-04-03 日本電気株式会社 研磨パッド
JP2001054859A (ja) * 1999-08-20 2001-02-27 Nikon Corp 研磨装置及び研磨部材
JP2001160545A (ja) * 1999-12-02 2001-06-12 Okamoto Machine Tool Works Ltd 半導体基板上の白金層の化学機械研磨方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287663A (en) * 1992-01-21 1994-02-22 National Semiconductor Corporation Polishing pad and method for polishing semiconductor wafers
US5944582A (en) * 1993-11-16 1999-08-31 Applied Materials, Inc. Chemical mechanical polishing with a small polishing pad
US5564965A (en) * 1993-12-14 1996-10-15 Shin-Etsu Handotai Co., Ltd. Polishing member and wafer polishing apparatus
US6099954A (en) * 1995-04-24 2000-08-08 Rodel Holdings, Inc. Polishing material and method of polishing a surface
US6077153A (en) * 1996-11-29 2000-06-20 Sumitomo Metal Industries, Limited Polishing pad and apparatus for polishing a semiconductor wafer
US5921856A (en) * 1997-07-10 1999-07-13 Sp3, Inc. CVD diamond coated substrate for polishing pad conditioning head and method for making same
US5931724A (en) * 1997-07-11 1999-08-03 Applied Materials, Inc. Mechanical fastener to hold a polishing pad on a platen in a chemical mechanical polishing system
US5882251A (en) * 1997-08-19 1999-03-16 Lsi Logic Corporation Chemical mechanical polishing pad slurry distribution grooves
US6616520B1 (en) * 1998-08-28 2003-09-09 Nitta Corporation Polishing cloth and method for attaching/detaching the polishing cloth to/from polishing machine base plate
US6402591B1 (en) * 2000-03-31 2002-06-11 Lam Research Corporation Planarization system for chemical-mechanical polishing
US6561889B1 (en) * 2000-12-27 2003-05-13 Lam Research Corporation Methods for making reinforced wafer polishing pads and apparatuses implementing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060219662A1 (en) * 2005-03-30 2006-10-05 Fujitsu Limited Fabrication process of semiconductor device and polishing method
US7348276B2 (en) 2005-03-30 2008-03-25 Fujitsu, Limited Fabrication process of semiconductor device and polishing method
US20080146128A1 (en) * 2005-03-30 2008-06-19 Fujitsu Limited Fabrication process of semiconductor device and polishing method
US7597606B2 (en) 2005-03-30 2009-10-06 Fujitsu Microelectronics Limited Fabrication process of semiconductor device and polishing method
US20070218288A1 (en) * 2006-03-14 2007-09-20 Harald Richter Adapter plate for supporting a vacuum suction device
US9118395B2 (en) 2010-09-09 2015-08-25 Infineon Technologies Ag Chip comprising a radio frequency switch arrangement, circuit arrangement and method for producing a radio frequency circuit arrangement
JP2018051679A (ja) * 2016-09-28 2018-04-05 株式会社ディスコ 研磨ユニット

Also Published As

Publication number Publication date
CN1224082C (zh) 2005-10-19
KR20040010566A (ko) 2004-01-31
CN1494734A (zh) 2004-05-05
EP1408538A4 (en) 2008-07-09
TW537945B (en) 2003-06-21
JPWO2003009362A1 (ja) 2004-11-11
KR100564125B1 (ko) 2006-03-27
WO2003009362A1 (fr) 2003-01-30
EP1408538A1 (en) 2004-04-14

Similar Documents

Publication Publication Date Title
US20040242132A1 (en) Polishing element, cmp polishing device and productionj method for semiconductor device
US5287663A (en) Polishing pad and method for polishing semiconductor wafers
US6277008B1 (en) Polishing apparatus
US6580128B2 (en) Semiconductor substrate, semiconductor device, and processes of production of same
CN117476547A (zh) 用于混合接合的化学机械抛光
JP3152188B2 (ja) 研磨パッド
JPH10138123A (ja) 半導体装置の研磨装置及び研磨方法
US20060079159A1 (en) Chemical mechanical polish with multi-zone abrasive-containing matrix
KR100552435B1 (ko) 반도체 웨이퍼 상의 유전체층을 평탄화하는 방법
US6942549B2 (en) Two-sided chemical mechanical polishing pad for semiconductor processing
JP3115025B2 (ja) 半導体ウエハの研磨用パッド及び研磨方法
US20080064308A1 (en) Polishing apparatus and manufacturing method of an electronic apparatus
US7189155B2 (en) Polishing body, polishing apparatus, semiconductor device, and semiconductor device manufacturing method
JPH0950974A (ja) 研磨布及び半導体装置の製造方法
JP3463345B2 (ja) 研磨装置および研磨方法と張り合わせ方法
US6503811B1 (en) Substrate having a semiconductor layer, and method for fabricating the same
JP2000354952A (ja) 研磨部材、研磨方法、研磨装置、半導体デバイス製造方法、及び半導体デバイス
US7252736B1 (en) Compliant grinding wheel
JP2001079755A (ja) 研磨体及び研磨方法
US8403727B1 (en) Pre-planarization system and method
JP2007305745A (ja) 研磨体、研磨装置、これを用いた半導体デバイス製造方法およびこの方法により製造される半導体デバイス
JP2003007656A (ja) 半導体装置の製造方法
JP2003068843A (ja) 半導体装置の製造方法
KR100587601B1 (ko) 반도체소자의 평탄화방법
WO2004105113A1 (ja) Cmp研磨用研磨体、cmp研磨装置、cmp研磨方法、及び半導体デバイスの製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: NIKON CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HOSHINO, SUSUMU;UDA, YUTAKA;SUGAYA, ISAO;REEL/FRAME:015601/0213

Effective date: 20030624

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION