KR20040010566A - 연마체, 화학 기계적 연마 장치 및 반도체 디바이스의제조 방법 - Google Patents
연마체, 화학 기계적 연마 장치 및 반도체 디바이스의제조 방법 Download PDFInfo
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- KR20040010566A KR20040010566A KR10-2003-7007085A KR20037007085A KR20040010566A KR 20040010566 A KR20040010566 A KR 20040010566A KR 20037007085 A KR20037007085 A KR 20037007085A KR 20040010566 A KR20040010566 A KR 20040010566A
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- 238000005498 polishing Methods 0.000 title claims abstract description 253
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims description 14
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- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 claims description 4
- 238000001179 sorption measurement Methods 0.000 claims description 3
- 239000004088 foaming agent Substances 0.000 claims description 2
- 239000003082 abrasive agent Substances 0.000 claims 1
- 239000002390 adhesive tape Substances 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
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- 229920001084 poly(chloroprene) Polymers 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/11—Lapping tools
- B24B37/20—Lapping pads for working plane surfaces
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24D—TOOLS FOR GRINDING, BUFFING OR SHARPENING
- B24D13/00—Wheels having flexibly-acting working parts, e.g. buffing wheels; Mountings therefor
- B24D13/20—Mountings for the wheels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
Description
재질스테인레스(E=21000㎏/㎟) | 경질 시트 두께 h | |||
0.35㎛ 배선 룰(허용 단차=0.35㎛;TTV=5㎛) | 0.10㎛ 배선 룰(허용 단차=0.10㎛;TTV=2㎛) | |||
L=4㎜ | L=20㎜ | L=4㎜ | L=20㎜ | |
면압 하중 | (w<0.35㎛) | (w>5㎛) | (w<0.1㎛) | (w>2㎛) |
100g/㎠ | 0.10㎜ | 0.36㎜ | 0.16㎜ | 0.49㎜ |
200g/㎠ | 0.13㎜ | 0.46㎜ | 0.20㎜ | 0.62㎜ |
300g/㎠ | 0.15㎜ | 0.52㎜ | 0.23㎜ | 0.71㎜ |
400g/㎠ | 0.16㎜ | 0.58㎜ | 0.25㎜ | 0.78㎜ |
500g/㎠ | 0.18㎜ | 0.62㎜ | 0.27㎜ | 0.84㎜ |
600g/㎠ | 0.19㎜ | 0.66㎜ | 0.28㎜ | 0.89㎜ |
700g/㎠ | 0.20㎜ | 0.69㎜ | 0.30㎜ | 0.94㎜ |
Claims (13)
- 내부에 반도체 집적 회로가 형성된 웨이퍼의 연마에 이용되는 CMP 연마 장치용 연마체로서,연마 패드와, 경질 탄성 부재와, 연질 부재를 이 순서로 적층하여 이루어지고,상기 경질 탄성 부재는 연마 중에 걸리는 연마 하중에 대한 변형량이, 상기 반도체 집적 회로의 최대 패턴에 상당하는 간격 사이에서는 상기 웨이퍼에 허용되는 단차보다 작아지고, 한 개의 칩에 상당하는 간격 사이에서는 상기 웨이퍼에 허용되는 TTV보다 커지도록 구성되어 있는 것을 특징으로 하는 연마체.
- 제1항에 있어서, 상기 경질 탄성 부재가 연마제에 용해되지 않는 금속판으로 구성되어 있는 것을 특징으로 하는 연마체.
- 제2항에 있어서, 상기 금속판이 스테인레스판이고, 그 두께(h)가 0.1 mm<h<0.94 mm로 되어 있는 것을 특징으로 하는 연마체.
- 내부에 반도체 집적 회로가 형성된 웨이퍼의 연마에 이용되는 CMP 연마 장치용 연마체로서, 연마 패드와, 경질 탄성 부재와, 연질 부재를 그 순서대로 적층하여 이루어지고, 연마 중에 걸리는 연마 하중에 대하여 그들의 연마 패드와, 경질탄성 부재와, 연질 부재를 합한 변형량이 상기 반도체 집적 회로의 최대 패턴에 해당하는 간격에서는 상기 최대 패턴의 요철의 높이보다 작고, 1칩에 상당하는 간격사이에서는 상기 웨이퍼에 허용되는 TTV의 5배보다 커지도록 구성되는 것을 특징으로 하는 연마체.
- 제4항에 있어서, 상기 경질 탄성 부재가 연마제에 용해되지 않는 금속판으로 구성되는 것을 특징으로 하는 연마체.
- 제5항에 있어서, 상기 연마 패드가 우레탄 발포제이고, 상기 금속판이 스테인레스판이며, 상기 연마 패드의 두께는 0.1 ∼ 3㎜이고, 상기 금속체의 두께는 0.05 ∼ 0.6㎜이며, 상기 연질 부재의 두께는 0.5 ∼ 2.5㎜인 것을 특징으로 하는 연마체.
- 제1항 내지 제6항 중 어느 한 항에 있어서, 상기 연질 부재는 연마 중에 하중을 걸어 회전할 때에, 파손되지 않도록 비틀림 강도를 갖는 것을 특징으로 하는 연마체.
- 제1항 내지 제7항 중 어느 한 항에 있어서, 상기 경질 탄성부재와 연질 부재는 접착에 의해 고정되고, 상기 경질 탄성 부재와 연마 패드는 진공 흡착에 의해 고정되는 것을 특징으로 하는 연마체.
- 제1항 내지 제7항 중 어느 한 항에 있어서, 상기 경질 탄성 부재와 연질 부재는 박리 강도가 강한 접착 수단에 의해 고정되고, 상기 경질 탄성 부재와 연마 패드는 박리 강도가 약한 접착 수단에 의해 고정되는 것을 특징으로 하는 연마체.
- 내부에 반도체 집적 회로가 형성된 웨이퍼의 연마에 이용되는 CMP 연마 장치로서, 청구항 제1항 내지 제9항 중 어느 한 항에 기재한 연마체를 갖는 것을 특징으로 하는 CMP 연마 장치
- 내부에 반도체 집적 회로가 형성된 웨이퍼의 연마에 이용되는 CMP 연마 장치로서, 청구항 제8항 또는 제9항에 기재되어 있는 연마체를 구비하여 이루어지고, 상기 연마 패드의 치수는 연마되는 웨이퍼의 치수보다 작게 형성되는 것을 특징으로 하는 CMP 연마 장치.
- 내부에 반도체 집적 회로가 형성된 웨이퍼의 연마에 이용되는 CMP 연마 장치용 연마체로서, 청구항 제7항에 기재한 연마체를 구비하여 이루어지고, 상기 연마 패드의 치수는 연마되는 웨이퍼의 치수보다 작게 형성되어, 상기 연질 부재의 허용 전단 응력이 0.5㎏/㎠ 보다 큰 것을 특징으로 하는 CMP 연마 장치.
- 청구항 제10항 내지 제12항 중 어느 한 항이 제1항 기재의 CMP 연마 장치를사용하여 웨이퍼의 연마를 행하는 공정을 갖는 것을 특징으로 하는 반도체 디바이스 제조 방법.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP2001219431 | 2001-07-19 | ||
JPJP-P-2001-00219431 | 2001-07-19 | ||
PCT/JP2002/006780 WO2003009362A1 (fr) | 2001-07-19 | 2002-07-04 | Element de polissage, dispositif de polissage mecano-chimique (cmp) et procede de production de dispositif a semi-conducteur |
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KR20040010566A true KR20040010566A (ko) | 2004-01-31 |
KR100564125B1 KR100564125B1 (ko) | 2006-03-27 |
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KR1020037007085A KR100564125B1 (ko) | 2001-07-19 | 2002-07-04 | 연마체, 화학 기계적 연마 장치 및 반도체 디바이스의제조 방법 |
Country Status (7)
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US (1) | US20040242132A1 (ko) |
EP (1) | EP1408538A4 (ko) |
JP (1) | JPWO2003009362A1 (ko) |
KR (1) | KR100564125B1 (ko) |
CN (1) | CN1224082C (ko) |
TW (1) | TW537945B (ko) |
WO (1) | WO2003009362A1 (ko) |
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JP2004023009A (ja) | 2002-06-20 | 2004-01-22 | Nikon Corp | 研磨体、研磨装置、半導体デバイス及び半導体デバイス製造方法 |
US7348276B2 (en) | 2005-03-30 | 2008-03-25 | Fujitsu, Limited | Fabrication process of semiconductor device and polishing method |
JP4937538B2 (ja) * | 2005-07-13 | 2012-05-23 | ニッタ・ハース株式会社 | 研磨布固定用の両面粘着テープおよびこれを備えた研磨布 |
MY149762A (en) * | 2006-01-30 | 2013-10-14 | Memc Electronic Materials | Double side wafer grinder and methods for assessing workpiece nanotopology |
DE202006004193U1 (de) * | 2006-03-14 | 2006-06-08 | Richter, Harald | Adapterplatte für einen Vakuumsauger |
JP4998824B2 (ja) * | 2007-06-12 | 2012-08-15 | 株式会社ニコン | 研磨パッドのサイズ設定方法 |
US8430721B2 (en) * | 2007-12-31 | 2013-04-30 | Innopad, Inc. | Chemical-mechanical planarization pad |
DE102010040512B4 (de) | 2010-09-09 | 2016-03-10 | Infineon Technologies Ag | Chip mit einer Hochfrequenzschalteranordnung und Schaltungsanordnung, Verfahren zur Herstellung einer Hochfrequenzschaltungsanordnung |
KR101596561B1 (ko) * | 2014-01-02 | 2016-03-07 | 주식회사 엘지실트론 | 웨이퍼 연마 장치 |
CN105500186A (zh) * | 2016-01-21 | 2016-04-20 | 苏州新美光纳米科技有限公司 | 晶片抛光用抛光垫及抛光垫的自吸附方法 |
JP6765267B2 (ja) * | 2016-09-28 | 2020-10-07 | 株式会社ディスコ | 研磨ユニット |
JP6986930B2 (ja) | 2017-11-07 | 2021-12-22 | 株式会社荏原製作所 | 基板研磨装置および研磨方法 |
WO2020115867A1 (ja) * | 2018-12-06 | 2020-06-11 | 三菱電機株式会社 | Osr貼り付け装置及びosr貼り付け方法 |
CN109648463B (zh) * | 2018-12-14 | 2021-04-23 | 厦门大学 | 一种半导体晶片光电化学机械抛光加工方法 |
CN113414717A (zh) * | 2021-08-05 | 2021-09-21 | 燕山大学 | 一种复合杯形抛光轮及其抛光方法 |
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2002
- 2002-07-04 KR KR1020037007085A patent/KR100564125B1/ko active IP Right Grant
- 2002-07-04 CN CNB028059743A patent/CN1224082C/zh not_active Expired - Lifetime
- 2002-07-04 JP JP2003514607A patent/JPWO2003009362A1/ja active Pending
- 2002-07-04 US US10/467,627 patent/US20040242132A1/en not_active Abandoned
- 2002-07-04 WO PCT/JP2002/006780 patent/WO2003009362A1/ja active IP Right Grant
- 2002-07-04 EP EP02743826A patent/EP1408538A4/en not_active Withdrawn
- 2002-07-19 TW TW091116079A patent/TW537945B/zh not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100901982B1 (ko) * | 2007-07-12 | 2009-06-08 | 주식회사 실트론 | 접착강도 시험장치 |
Also Published As
Publication number | Publication date |
---|---|
WO2003009362A1 (fr) | 2003-01-30 |
CN1224082C (zh) | 2005-10-19 |
CN1494734A (zh) | 2004-05-05 |
EP1408538A4 (en) | 2008-07-09 |
KR100564125B1 (ko) | 2006-03-27 |
EP1408538A1 (en) | 2004-04-14 |
TW537945B (en) | 2003-06-21 |
US20040242132A1 (en) | 2004-12-02 |
JPWO2003009362A1 (ja) | 2004-11-11 |
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