TWI765077B - 多層膜之蝕刻方法 - Google Patents

多層膜之蝕刻方法 Download PDF

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Publication number
TWI765077B
TWI765077B TW107125955A TW107125955A TWI765077B TW I765077 B TWI765077 B TW I765077B TW 107125955 A TW107125955 A TW 107125955A TW 107125955 A TW107125955 A TW 107125955A TW I765077 B TWI765077 B TW I765077B
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TW
Taiwan
Prior art keywords
gas
multilayer film
etching
plasma
mask
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Application number
TW107125955A
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English (en)
Chinese (zh)
Other versions
TW201911411A (zh
Inventor
後平拓
Original Assignee
日商東京威力科創股份有限公司
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Publication of TW201911411A publication Critical patent/TW201911411A/zh
Application granted granted Critical
Publication of TWI765077B publication Critical patent/TWI765077B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW107125955A 2017-08-01 2018-07-27 多層膜之蝕刻方法 TWI765077B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-149186 2017-08-01
JP2017149186A JP6948181B2 (ja) 2017-08-01 2017-08-01 多層膜をエッチングする方法

Publications (2)

Publication Number Publication Date
TW201911411A TW201911411A (zh) 2019-03-16
TWI765077B true TWI765077B (zh) 2022-05-21

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW107125955A TWI765077B (zh) 2017-08-01 2018-07-27 多層膜之蝕刻方法

Country Status (6)

Country Link
US (1) US20190043721A1 (enExample)
JP (1) JP6948181B2 (enExample)
KR (1) KR102531961B1 (enExample)
CN (1) CN109326517B (enExample)
SG (1) SG10201806550PA (enExample)
TW (1) TWI765077B (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11171011B2 (en) * 2018-08-21 2021-11-09 Lam Research Corporation Method for etching an etch layer
JP7228413B2 (ja) * 2019-03-11 2023-02-24 東京エレクトロン株式会社 プラズマ処理方法、及び、プラズマ処理装置
US12469693B2 (en) * 2019-09-17 2025-11-11 Asm Ip Holding B.V. Method of forming a carbon-containing layer and structure including the layer
JP7308110B2 (ja) * 2019-09-17 2023-07-13 東京エレクトロン株式会社 シリコン酸化膜をエッチングする方法及びプラズマ処理装置
JP7292163B2 (ja) * 2019-09-19 2023-06-16 株式会社ディスコ 被加工物の加工方法
JP7604145B2 (ja) * 2019-11-25 2024-12-23 東京エレクトロン株式会社 基板処理方法及びプラズマ処理装置
JP7641170B2 (ja) * 2021-05-07 2025-03-06 東京エレクトロン株式会社 基板処理装置及び基板処理方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017018256A1 (ja) * 2015-07-29 2017-02-02 東京エレクトロン株式会社 多層膜をエッチングする方法
JP2017118091A (ja) * 2015-12-18 2017-06-29 東京エレクトロン株式会社 エッチング方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3347909B2 (ja) * 1994-06-13 2002-11-20 松下電器産業株式会社 プラズマ発生加工方法およびその装置
JPH0936103A (ja) * 1995-07-18 1997-02-07 Ulvac Japan Ltd 半導体ウェハのエッチング及びレジスト除去のための方法並びに装置
JP2001102362A (ja) * 1999-09-30 2001-04-13 Advanced Display Inc コンタクトホールの形成方法およびその形成方法を用いて製造された液晶表示装置
JP2003229411A (ja) * 2002-02-01 2003-08-15 Toshiba Corp 薄膜トランジスタの製造方法
JP2005277375A (ja) * 2004-02-27 2005-10-06 Nec Electronics Corp 半導体装置の製造方法
JP2009105279A (ja) * 2007-10-24 2009-05-14 Fujitsu Microelectronics Ltd 半導体装置の製造方法及び半導体装置
KR102034556B1 (ko) * 2012-02-09 2019-10-21 도쿄엘렉트론가부시키가이샤 플라즈마 처리 방법
JP5968130B2 (ja) * 2012-07-10 2016-08-10 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
JP6207947B2 (ja) * 2013-09-24 2017-10-04 東京エレクトロン株式会社 被処理体をプラズマ処理する方法
JP2015079793A (ja) * 2013-10-15 2015-04-23 東京エレクトロン株式会社 プラズマ処理方法
JP6267953B2 (ja) * 2013-12-19 2018-01-24 東京エレクトロン株式会社 半導体装置の製造方法
JP6230930B2 (ja) * 2014-02-17 2017-11-15 東京エレクトロン株式会社 半導体装置の製造方法
JP6454492B2 (ja) * 2014-08-08 2019-01-16 東京エレクトロン株式会社 多層膜をエッチングする方法
JP6328524B2 (ja) * 2014-08-29 2018-05-23 東京エレクトロン株式会社 エッチング方法
JP6408903B2 (ja) 2014-12-25 2018-10-17 東京エレクトロン株式会社 エッチング処理方法及びエッチング処理装置
JP2016157793A (ja) * 2015-02-24 2016-09-01 東京エレクトロン株式会社 エッチング方法
JP6339961B2 (ja) * 2015-03-31 2018-06-06 東京エレクトロン株式会社 エッチング方法
US9613824B2 (en) * 2015-05-14 2017-04-04 Tokyo Electron Limited Etching method
JP6541439B2 (ja) * 2015-05-29 2019-07-10 東京エレクトロン株式会社 エッチング方法
JP6494424B2 (ja) * 2015-05-29 2019-04-03 東京エレクトロン株式会社 エッチング方法
JP6604833B2 (ja) * 2015-12-03 2019-11-13 東京エレクトロン株式会社 プラズマエッチング方法
US20180286707A1 (en) * 2017-03-30 2018-10-04 Lam Research Corporation Gas additives for sidewall passivation during high aspect ratio cryogenic etch

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017018256A1 (ja) * 2015-07-29 2017-02-02 東京エレクトロン株式会社 多層膜をエッチングする方法
JP2017118091A (ja) * 2015-12-18 2017-06-29 東京エレクトロン株式会社 エッチング方法

Also Published As

Publication number Publication date
JP2019029561A (ja) 2019-02-21
JP6948181B2 (ja) 2021-10-13
KR20190013663A (ko) 2019-02-11
KR102531961B1 (ko) 2023-05-12
CN109326517B (zh) 2023-07-28
TW201911411A (zh) 2019-03-16
SG10201806550PA (en) 2019-03-28
CN109326517A (zh) 2019-02-12
US20190043721A1 (en) 2019-02-07

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