JP6948181B2 - 多層膜をエッチングする方法 - Google Patents
多層膜をエッチングする方法 Download PDFInfo
- Publication number
- JP6948181B2 JP6948181B2 JP2017149186A JP2017149186A JP6948181B2 JP 6948181 B2 JP6948181 B2 JP 6948181B2 JP 2017149186 A JP2017149186 A JP 2017149186A JP 2017149186 A JP2017149186 A JP 2017149186A JP 6948181 B2 JP6948181 B2 JP 6948181B2
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- JP
- Japan
- Prior art keywords
- gas
- multilayer film
- mask
- plasma
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Plasma Technology (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017149186A JP6948181B2 (ja) | 2017-08-01 | 2017-08-01 | 多層膜をエッチングする方法 |
| TW107125955A TWI765077B (zh) | 2017-08-01 | 2018-07-27 | 多層膜之蝕刻方法 |
| US16/050,455 US20190043721A1 (en) | 2017-08-01 | 2018-07-31 | Method of etching multilayered film |
| SG10201806550PA SG10201806550PA (en) | 2017-08-01 | 2018-07-31 | Method of etching multilayered film |
| KR1020180089239A KR102531961B1 (ko) | 2017-08-01 | 2018-07-31 | 다층막을 에칭하는 방법 |
| CN201810862184.0A CN109326517B (zh) | 2017-08-01 | 2018-08-01 | 对多层膜进行蚀刻的方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017149186A JP6948181B2 (ja) | 2017-08-01 | 2017-08-01 | 多層膜をエッチングする方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019029561A JP2019029561A (ja) | 2019-02-21 |
| JP2019029561A5 JP2019029561A5 (enExample) | 2020-06-25 |
| JP6948181B2 true JP6948181B2 (ja) | 2021-10-13 |
Family
ID=65230491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017149186A Active JP6948181B2 (ja) | 2017-08-01 | 2017-08-01 | 多層膜をエッチングする方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20190043721A1 (enExample) |
| JP (1) | JP6948181B2 (enExample) |
| KR (1) | KR102531961B1 (enExample) |
| CN (1) | CN109326517B (enExample) |
| SG (1) | SG10201806550PA (enExample) |
| TW (1) | TWI765077B (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11171011B2 (en) * | 2018-08-21 | 2021-11-09 | Lam Research Corporation | Method for etching an etch layer |
| JP7228413B2 (ja) * | 2019-03-11 | 2023-02-24 | 東京エレクトロン株式会社 | プラズマ処理方法、及び、プラズマ処理装置 |
| US12469693B2 (en) * | 2019-09-17 | 2025-11-11 | Asm Ip Holding B.V. | Method of forming a carbon-containing layer and structure including the layer |
| JP7308110B2 (ja) * | 2019-09-17 | 2023-07-13 | 東京エレクトロン株式会社 | シリコン酸化膜をエッチングする方法及びプラズマ処理装置 |
| JP7292163B2 (ja) * | 2019-09-19 | 2023-06-16 | 株式会社ディスコ | 被加工物の加工方法 |
| JP7604145B2 (ja) * | 2019-11-25 | 2024-12-23 | 東京エレクトロン株式会社 | 基板処理方法及びプラズマ処理装置 |
| JP7641170B2 (ja) * | 2021-05-07 | 2025-03-06 | 東京エレクトロン株式会社 | 基板処理装置及び基板処理方法 |
Family Cites Families (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3347909B2 (ja) * | 1994-06-13 | 2002-11-20 | 松下電器産業株式会社 | プラズマ発生加工方法およびその装置 |
| JPH0936103A (ja) * | 1995-07-18 | 1997-02-07 | Ulvac Japan Ltd | 半導体ウェハのエッチング及びレジスト除去のための方法並びに装置 |
| JP2001102362A (ja) * | 1999-09-30 | 2001-04-13 | Advanced Display Inc | コンタクトホールの形成方法およびその形成方法を用いて製造された液晶表示装置 |
| JP2003229411A (ja) * | 2002-02-01 | 2003-08-15 | Toshiba Corp | 薄膜トランジスタの製造方法 |
| JP2005277375A (ja) * | 2004-02-27 | 2005-10-06 | Nec Electronics Corp | 半導体装置の製造方法 |
| JP2009105279A (ja) * | 2007-10-24 | 2009-05-14 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法及び半導体装置 |
| KR102034556B1 (ko) * | 2012-02-09 | 2019-10-21 | 도쿄엘렉트론가부시키가이샤 | 플라즈마 처리 방법 |
| JP5968130B2 (ja) * | 2012-07-10 | 2016-08-10 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
| JP6207947B2 (ja) * | 2013-09-24 | 2017-10-04 | 東京エレクトロン株式会社 | 被処理体をプラズマ処理する方法 |
| JP2015079793A (ja) * | 2013-10-15 | 2015-04-23 | 東京エレクトロン株式会社 | プラズマ処理方法 |
| JP6267953B2 (ja) * | 2013-12-19 | 2018-01-24 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| JP6230930B2 (ja) * | 2014-02-17 | 2017-11-15 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| JP6454492B2 (ja) * | 2014-08-08 | 2019-01-16 | 東京エレクトロン株式会社 | 多層膜をエッチングする方法 |
| JP6328524B2 (ja) * | 2014-08-29 | 2018-05-23 | 東京エレクトロン株式会社 | エッチング方法 |
| JP6408903B2 (ja) | 2014-12-25 | 2018-10-17 | 東京エレクトロン株式会社 | エッチング処理方法及びエッチング処理装置 |
| JP2016157793A (ja) * | 2015-02-24 | 2016-09-01 | 東京エレクトロン株式会社 | エッチング方法 |
| JP6339961B2 (ja) * | 2015-03-31 | 2018-06-06 | 東京エレクトロン株式会社 | エッチング方法 |
| US9613824B2 (en) * | 2015-05-14 | 2017-04-04 | Tokyo Electron Limited | Etching method |
| JP6541439B2 (ja) * | 2015-05-29 | 2019-07-10 | 東京エレクトロン株式会社 | エッチング方法 |
| JP6494424B2 (ja) * | 2015-05-29 | 2019-04-03 | 東京エレクトロン株式会社 | エッチング方法 |
| JP2017033982A (ja) * | 2015-07-29 | 2017-02-09 | 東京エレクトロン株式会社 | 多層膜をエッチングする方法 |
| JP6604833B2 (ja) * | 2015-12-03 | 2019-11-13 | 東京エレクトロン株式会社 | プラズマエッチング方法 |
| JP6498152B2 (ja) * | 2015-12-18 | 2019-04-10 | 東京エレクトロン株式会社 | エッチング方法 |
| US20180286707A1 (en) * | 2017-03-30 | 2018-10-04 | Lam Research Corporation | Gas additives for sidewall passivation during high aspect ratio cryogenic etch |
-
2017
- 2017-08-01 JP JP2017149186A patent/JP6948181B2/ja active Active
-
2018
- 2018-07-27 TW TW107125955A patent/TWI765077B/zh active
- 2018-07-31 KR KR1020180089239A patent/KR102531961B1/ko active Active
- 2018-07-31 US US16/050,455 patent/US20190043721A1/en not_active Abandoned
- 2018-07-31 SG SG10201806550PA patent/SG10201806550PA/en unknown
- 2018-08-01 CN CN201810862184.0A patent/CN109326517B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2019029561A (ja) | 2019-02-21 |
| KR20190013663A (ko) | 2019-02-11 |
| KR102531961B1 (ko) | 2023-05-12 |
| TWI765077B (zh) | 2022-05-21 |
| CN109326517B (zh) | 2023-07-28 |
| TW201911411A (zh) | 2019-03-16 |
| SG10201806550PA (en) | 2019-03-28 |
| CN109326517A (zh) | 2019-02-12 |
| US20190043721A1 (en) | 2019-02-07 |
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