TWI712106B - 用於製作包含中介層之半導體結構之方法 - Google Patents
用於製作包含中介層之半導體結構之方法 Download PDFInfo
- Publication number
- TWI712106B TWI712106B TW106117418A TW106117418A TWI712106B TW I712106 B TWI712106 B TW I712106B TW 106117418 A TW106117418 A TW 106117418A TW 106117418 A TW106117418 A TW 106117418A TW I712106 B TWI712106 B TW I712106B
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- Prior art keywords
- temporary support
- layer
- semiconductor
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- Prior art date
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Classifications
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- H10W74/019—
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- H10P54/00—
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- H10P72/74—
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- H10P90/1906—
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- H10W10/181—
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- H10W70/05—
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- H10W70/611—
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- H10W70/685—
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- H10W74/014—
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- H10W74/114—
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- H10P30/204—
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- H10P30/208—
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- H10P72/7412—
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- H10P72/7426—
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- H10P72/743—
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- H10P72/7438—
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- H10P72/744—
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- H10W70/60—
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- H10W70/66—
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- H10W72/01255—
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- H10W72/01257—
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- H10W72/0198—
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- H10W72/072—
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- H10W72/07207—
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- H10W72/07307—
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- H10W72/07337—
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- H10W72/241—
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- H10W72/244—
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- H10W72/344—
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- H10W72/922—
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- H10W80/211—
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- H10W80/301—
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- H10W90/00—
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- H10W90/722—
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- H10W90/724—
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- H10W90/732—
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- H10W90/792—
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- H10W90/794—
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- H10W99/00—
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1654831 | 2016-05-30 | ||
| FR1654831A FR3051971B1 (fr) | 2016-05-30 | 2016-05-30 | Procede de fabrication d'une structure semi-conductrice comprenant un interposeur |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201742189A TW201742189A (zh) | 2017-12-01 |
| TWI712106B true TWI712106B (zh) | 2020-12-01 |
Family
ID=56684055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW106117418A TWI712106B (zh) | 2016-05-30 | 2017-05-25 | 用於製作包含中介層之半導體結構之方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US11114314B2 (enExample) |
| KR (1) | KR102397140B1 (enExample) |
| CN (1) | CN109196627B (enExample) |
| DE (1) | DE112017002718T5 (enExample) |
| FR (1) | FR3051971B1 (enExample) |
| SG (2) | SG10201913072VA (enExample) |
| TW (1) | TWI712106B (enExample) |
| WO (1) | WO2017207390A1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW202038266A (zh) * | 2018-11-26 | 2020-10-16 | 瑞典商斯莫勒科技公司 | 具有離散的能量儲存構件之半導體組件 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100109169A1 (en) * | 2008-04-29 | 2010-05-06 | United Test And Assembly Center Ltd | Semiconductor package and method of making the same |
| US20130214423A1 (en) * | 2011-03-31 | 2013-08-22 | Soitec | Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices |
| US20140339706A1 (en) * | 2013-05-17 | 2014-11-20 | Nvidia Corporation | Integrated circuit package with an interposer formed from a reusable carrier substrate |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
| KR100484962B1 (ko) | 1996-07-12 | 2005-04-25 | 후지쯔 가부시끼가이샤 | 반도체 장치의 제조 방법 및 반도체 장치 |
| JP3809733B2 (ja) * | 1998-02-25 | 2006-08-16 | セイコーエプソン株式会社 | 薄膜トランジスタの剥離方法 |
| JP2001102523A (ja) * | 1999-09-28 | 2001-04-13 | Sony Corp | 薄膜デバイスおよびその製造方法 |
| FR2809867B1 (fr) * | 2000-05-30 | 2003-10-24 | Commissariat Energie Atomique | Substrat fragilise et procede de fabrication d'un tel substrat |
| US6794273B2 (en) * | 2002-05-24 | 2004-09-21 | Fujitsu Limited | Semiconductor device and manufacturing method thereof |
| JP4651924B2 (ja) * | 2003-09-18 | 2011-03-16 | シャープ株式会社 | 薄膜半導体装置および薄膜半導体装置の製造方法 |
| FR2898430B1 (fr) * | 2006-03-13 | 2008-06-06 | Soitec Silicon On Insulator | Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede |
| FR2928031B1 (fr) * | 2008-02-25 | 2010-06-11 | Soitec Silicon On Insulator | Procede de transfert d'une couche mince sur un substrat support. |
| FR2936357B1 (fr) * | 2008-09-24 | 2010-12-10 | Commissariat Energie Atomique | Procede de report de puces sur un substrat. |
| US8728863B2 (en) * | 2011-08-09 | 2014-05-20 | Soitec | Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods |
| WO2013095544A1 (en) | 2011-12-22 | 2013-06-27 | Intel Corporation | 3d integrated circuit package with window interposer |
| US8685761B2 (en) * | 2012-02-02 | 2014-04-01 | Harris Corporation | Method for making a redistributed electronic device using a transferrable redistribution layer |
| TWI517274B (zh) * | 2012-03-21 | 2016-01-11 | 矽品精密工業股份有限公司 | 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法 |
| US8963285B2 (en) * | 2013-03-08 | 2015-02-24 | Infineon Technologies Ag | Semiconductor device and method of manufacturing thereof |
| US9209142B1 (en) * | 2014-09-05 | 2015-12-08 | Skorpios Technologies, Inc. | Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal |
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2016
- 2016-05-30 FR FR1654831A patent/FR3051971B1/fr active Active
-
2017
- 2017-05-24 SG SG10201913072VA patent/SG10201913072VA/en unknown
- 2017-05-24 WO PCT/EP2017/062556 patent/WO2017207390A1/en not_active Ceased
- 2017-05-24 CN CN201780032360.1A patent/CN109196627B/zh active Active
- 2017-05-24 KR KR1020187034604A patent/KR102397140B1/ko active Active
- 2017-05-24 DE DE112017002718.7T patent/DE112017002718T5/de active Pending
- 2017-05-24 US US16/305,695 patent/US11114314B2/en active Active
- 2017-05-24 SG SG11201810104VA patent/SG11201810104VA/en unknown
- 2017-05-25 TW TW106117418A patent/TWI712106B/zh active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100109169A1 (en) * | 2008-04-29 | 2010-05-06 | United Test And Assembly Center Ltd | Semiconductor package and method of making the same |
| US20130214423A1 (en) * | 2011-03-31 | 2013-08-22 | Soitec | Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices |
| US20140339706A1 (en) * | 2013-05-17 | 2014-11-20 | Nvidia Corporation | Integrated circuit package with an interposer formed from a reusable carrier substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| US11114314B2 (en) | 2021-09-07 |
| FR3051971A1 (enExample) | 2017-12-01 |
| KR20190015707A (ko) | 2019-02-14 |
| US20200328094A1 (en) | 2020-10-15 |
| TW201742189A (zh) | 2017-12-01 |
| SG11201810104VA (en) | 2018-12-28 |
| CN109196627B (zh) | 2023-08-08 |
| WO2017207390A1 (en) | 2017-12-07 |
| CN109196627A (zh) | 2019-01-11 |
| SG10201913072VA (en) | 2020-03-30 |
| FR3051971B1 (fr) | 2019-12-13 |
| KR102397140B1 (ko) | 2022-05-16 |
| DE112017002718T5 (de) | 2019-02-28 |
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