CN106992144A - 半导体装置的制作方法 - Google Patents

半导体装置的制作方法 Download PDF

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CN106992144A
CN106992144A CN201610210325.1A CN201610210325A CN106992144A CN 106992144 A CN106992144 A CN 106992144A CN 201610210325 A CN201610210325 A CN 201610210325A CN 106992144 A CN106992144 A CN 106992144A
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赖敬华
施健鸿
邱定中
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Micron Technology Inc
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Abstract

本发明公开了一种半导体装置的制作方法，包含：提供一晶圆，具有一正面与一背面；于所述正面形成多数个穿板通孔；于所述多数个穿板通孔上形成一重分布层；将所述晶圆与一载板接合；于所述背面进行一晶背抛光工艺，薄化所述晶圆；进行一退火工艺，使所述穿板通孔再结晶；以及进行一化学机械抛光工艺，抛光所述晶圆的所述背面。

Description

半导体装置的制作方法
技术领域
本发明涉及一种半导体装置的制作方法，特别是涉及一种穿板通孔(through substrate via，TSV)(或穿硅通孔)中介层的制作方法。
背景技术
穿板通孔中介层是一种设置在一个或多个集成电路芯片与一安装基板之间的半导体装置，其中包含有复数个导电通孔。这些导电通孔可允许集成电路芯片与安装基板之间的电连接。
根据公知技术，上述导电通孔的制作方法是先在一硅基板的正面形成孔洞，接着在孔洞的侧壁形成绝缘结构，然后以电镀方式于孔洞内填入导电金属，例如铜，再抛光硅基板的背面以暴露出导电通孔的另一端面，用来提供进一步连结使用。
然而，上述现有技术仍有许多缺点。例如，自硅基板的背面暴露出来的导电通孔的另一端面上常会有铜挤出(copper extrusion)现象。有鉴于此，本技术领域仍需要一种改良的半导体装置的制作方法，可以解决上述现有技术面临的问题。
发明内容
根据本发明实施例，本发明公开一种半导体装置的制作方法，包含：提供一晶圆，具有一正面与一背面；于所述正面形成多数个穿板通孔(throughsubstrate via，穿板通孔)；于所述多数个穿板通孔上形成一重分布层；将所述晶圆接合一载板；于所述背面进行一晶背抛光工艺，薄化所述晶圆；进行一退火工艺，使所述穿板通孔再结晶；以及进行一化学机械抛光工艺，抛光所述晶圆的所述背面。
毋庸置疑的，本领域的技术人员读完接下来本发明优选实施例的详细描述与附图后，均可了解本发明的目的。
附图说明
图1到图6是根据本发明一实施例所绘示的一种半导体装置的制作方法的剖面示意图。
其中，附图标记说明如下：
100 晶圆
100a 正面
100b 背面
101 穿板通孔
102 铜金属层
103 硅氧层
110 重分布层
112 介电层
114 金属层
116 凸块
130 铜挤出缺陷
200 载板
300 退火工艺
具体实施方式
接下来的详细叙述须参考相关附图所示内容，用来说明可根据本发明具体实行的实施例。这些实施例提供足够的细节，可使本领域中的技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
因此，接下来的详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具同等意义者，也应属本发明涵盖的范围。本发明实施例所参考的附图为示意图，并未按比例绘制，且相同或类似的特征通常以相同的附图标记描述。
在本说明书中，“晶圆”与“基板”意指任何包含一暴露面，可根据本发明实施例的描述在其上沉积材料，制作集成电路结构的结构物，例如重分布层。须了解的是“基板”包含半导体晶圆，但并不限于此。"基板"在工艺中也意指包含制作于其上的材料层的半导体结构物。
请参考图1到图6，是根据本发明一实施例所绘示的一种半导体装置的制作方法的剖面示意图。
如图1所示，首先，提供一晶圆100。晶圆100可以是例如一硅中介层晶圆(silicon interposer wafer)，但不限于此。晶圆100可以具有一初始厚度，例如介于600至800微米之间。根据本发明一实施例，晶圆100的厚度可以是770微米。晶圆100具有一正面100a以及一背面100b。
接着，在所述晶圆100的正面100a形成深入到晶圆100内部的多数个穿板通孔(through substrate vias，TSV)101。可以用本领域公知技术形成上述穿板通孔101。例如，要形成上述穿板通孔101，可以于晶圆100的正面100a上形成穿板通孔孔洞，至晶圆100一主表面以下的一预定深度。接着，形成一介电层，例如硅氧层103，作为穿板通孔孔洞内的绝缘内壁。接着，于穿板通孔孔洞内填入金属，其可以包括，但不限于，扩散阻障层及铜金属层102。之后，可以选择对晶圆100的正面100a进行一抛光工艺以及一退火工艺。
如图2所示，根据所述实施例，接着在晶圆100的正面100a上形成一重分布层(redistribution layer，RDL)110。所述重分布层110可以包含至少一介电层112以及至少一金属层114。上述穿板通孔101可以电连接到金属层114。接着，在所述重分布层110上形成多数个凸块116，例如，微凸块，用来提供进一步连接使用。所述凸块116可以是直接形成在位于金属层114中的相对应的接触垫上。
本领域的技术人员应可理解，附图中的重分布层110结构仅为例示说明。在其它实施例中，重分布层110可以包含复数层介电层以及形成在所述复数层介电层内的复数层金属内连线结构或绕线。在其它实施例中，可以进一步在晶圆100的正面100a上设置半导体晶粒(图未示)，再由一模塑料(图未示)包覆起来。
如图3所示，接着，以凸块116面向一载板200的方位，将晶圆100黏贴至载板200上。载板200可以是，例如，玻璃载板、硅载板等，但不限于此。凸块116接触到载板200。可以选择使用一黏着层(图未示)，将晶圆100黏贴至载板200上。
如图4所示，将晶圆100黏贴至载板200之后，接着对晶圆100的背面100b进行一晶背抛光工艺，以薄化晶圆100。部分的晶圆100从其背面100b被去除。根据本发明实施例，可选择利用一化学机械抛光(chemical mechanicalpolishing，CMP)工艺抛光晶圆100的背面100b，使穿板通孔101的一端从晶圆100的背面100b暴露出来。
如图5所示，接着可以对晶圆100的背面100b进行一退火工艺300，使穿板通孔101的铜金属层102再结晶。根据一优选实施例，退火工艺300是在约200℃的温度下进行。根据所述实施例，在穿板通孔101暴露出来的一端面上，可能产生铜挤出缺陷130。
如图6所示，接着可以对晶圆100的背面100b进行另一化学机械抛光工艺，用来抛光移除上述铜挤出缺陷130。接着，可以选择性的在晶圆100的背面100b上形成一钝化层(图未示)，也可以选择性的在晶圆100的背面100b上形成另一重分布层(图未示)。之后，将晶圆100与载板200分离。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (7)

1.一种半导体装置的制作方法，其特征在于，包含：
提供一晶圆，具有一正面与一背面；
于所述正面形成多数个穿板通孔；
于所述多数个穿板通孔上形成一重分布层；
将所述晶圆与一载板接合；
于所述背面进行一晶背抛光工艺，薄化所述晶圆；
进行一退火工艺，使所述穿板通孔再结晶；以及
进行一化学机械抛光工艺，抛光所述晶圆的所述背面。
2.根据权利要求1所述的半导体装置的制作方法，其特征在于，于所述正面形成多数个穿板通孔是包含：
于所述正面形成多数个穿板通孔孔洞至所述晶圆一主表面以下的一预定深度；
形成一介电层，做为所述穿板通孔孔洞内的绝缘内壁；以及
于所述穿板通孔孔洞内填入金属。
3.根据权利要求1所述的半导体装置的制作方法，其特征在于，所述化学机械抛光工艺是在所述退火工艺之后进行。
4.根据权利要求1所述的半导体装置的制作方法，其特征在于，所述退火工艺是在200℃的温度下进行。
5.根据权利要求1所述的半导体装置的制作方法，其特征在于，所述重分布层包含至少一介电层及至少一金属层。
6.根据权利要求1所述的半导体装置的制作方法，其特征在于，另包含于所述重分布层上形成多数个凸块。
7.根据权利要求1所述的半导体装置的制作方法，其特征在于，在完成所述化学机械抛光工艺之后，另包含将所述晶圆与所述载板分离。
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US15/002,404 US9899260B2 (en) 2016-01-21 2016-01-21 Method for fabricating a semiconductor device
US15/002,404 2016-01-21

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