TWI606528B - 半導體裝置的製作方法 - Google Patents

半導體裝置的製作方法 Download PDF

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TWI606528B
TWI606528B TW105107836A TW105107836A TWI606528B TW I606528 B TWI606528 B TW I606528B TW 105107836 A TW105107836 A TW 105107836A TW 105107836 A TW105107836 A TW 105107836A TW I606528 B TWI606528 B TW I606528B
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wafer
semiconductor device
fabricating
layer
forming
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TW201727783A (zh
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賴敬華
施健鴻
邱定中
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美光科技公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body

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Description

半導體裝置的製作方法
本發明係有關於一種半導體裝置，特別是有關於一種穿板通孔（through substrate via，TSV）（或穿矽通孔）中介層及其製作方法。
穿板通孔中介層係一種設置在一或多個積體電路晶片與一安裝基板之間的半導體裝置，其上具有導電通孔。這些導電通孔可允許積體電路晶片電連接至安裝基板。
已知，上述導電通孔的製作係先在一矽基板的正面形成孔洞，接著使孔洞的側壁絕緣，接著於孔洞內以電鍍方式填入導電金屬，例如銅等，再研磨矽晶板的背面以顯露出導電通孔的另一端，以供進一步連結使用。
然而，上述先前技藝仍有諸多缺點。例如，在矽基板的背面上所顯露出來的導電通孔端面上常會有銅擠出（copper extrusion）現象。因此，該技術領域仍需要一種改良的半導體裝置的製作方法，以解決先前技藝的不足。
根據本發明實施例，本發明揭露一種半導體裝置的製作方法，包含：提供一晶圓，具有一正面與一背面；於該正面形成複數個穿板通孔（through substrate via，TSV）；於該複數個TSV上形成一重佈線層；將該晶圓接合一載板；於該背面進行一晶背研磨製程，薄化該晶圓；進行一回火製程，再結晶該TSV；以及進行一化學機械研磨製程，研磨該晶圓的該背面。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述須參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，可做結構、邏輯和電性上的修改應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者，也應屬本發明涵蓋的範圍。本發明實施例所參照的附圖為示意圖，並未按比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層。須了解的是“基板”包含半導體晶圓，但並不限於此。"基板"在製程中也意指包含製作於其上的材料層的半導體結構物。
請參閱第1圖至第6圖，其為依據本發明一實施例所繪示的一種半導體裝置的製作方法的剖面示意圖。
如第1圖所示，首先，提供一晶圓100。晶圓100可以是例如一矽中介層晶圓（silicon interposer wafer），但不限於此。晶圓100可以具有一初始厚度，其介於600至800微米之間，例如，770微米。所述晶圓100具有一正面100a以及一背面100b。
接著，於所述晶圓100的正面100a上形成深入到晶圓100內的複數個穿板通孔（through substrate vias，TSV）101。形成上述穿板通孔101的方法乃週知技藝。舉例來說，要形成上述穿板通孔101，可以於晶圓100的正面100a上形成TSV孔洞，至晶圓100一主表面以下的一預定深度。接著，利用一介電層，例如矽氧層103，於TSV孔洞內形成絕緣內壁。接著，於TSV孔洞內填入金屬，其可以包括，但不限於，擴散阻障層及銅金屬層102。後續還可以選擇對晶圓100的正面100a進行一研磨製程以及一回火製程。
如第2圖所示，根據所例示的實施例，接著在晶圓100的正面100a上形成一重佈線層（redistribution layer，RDL）110。所述重佈線層110可以包含至少一介電層112以及至少一金屬層114。上述穿板通孔101可以連接至金屬層114。接著，於所述重佈線層110上形成複數個凸塊116，例如，微凸塊，以供進一步連結使用。所述凸塊116可以直接形成在金屬層114中的相對應的接觸墊上。
熟習該項技藝者應理解圖式中的重佈線層結構僅為例示說明。在其它實施例中，重佈線層110可以包含複數層介電層以及形成在該複數層介電層內的複數層金屬內連結結構或繞線。在其它實施例中，可以進一步在晶圓100的正面100a上設置半導體晶粒（圖未示），再由一成型模料（圖未示）包覆起來。
如第3圖所示，接著，將晶圓100黏貼至一載板200。例如，載板200可以是一玻璃載板、矽載板等等，但不限於此。凸塊116係面向，並且接觸到，所述載板200。在將晶圓100黏貼至載板200時，可以選擇使用一黏著層（圖未示）。
如第4圖所示，在形成載板200之後，接著，對晶圓100的背面100b進行一晶背研磨製程，以薄化晶圓100。部分的晶圓100從其背面100b被去除。根據本發明實施例，可選擇利用一化學機械研磨（chemical mechanical polishing，CMP）製程研磨晶圓100的背面100b，使穿板通孔101的一端從晶圓100的背面100b顯露出來。
如第5圖所示，接著可以繼續對晶圓100的背面100b進行一回火製程300，以使穿板通孔101的銅金屬層102再結晶。根據所例示的實施例，所述回火製程較佳係在約200℃下進行。根據所例示的實施例，在顯露出來的穿板通孔101的一端面上，可能產生銅擠出缺陷130。
如第6圖所示，可以繼續對晶圓100的背面100b進行另一化學機械研磨製程，以研磨掉上述銅擠出缺陷130。接著，可以選擇於晶圓100的背面100b上形成一鈍化層（圖未示）。重佈線層可選擇形成在晶圓100的背面100b上。最後，將載板200去除。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100‧‧‧晶圓 100a‧‧‧正面 100b‧‧‧背面 101‧‧‧穿板通孔 102‧‧‧銅金屬層 103‧‧‧矽氧層 110‧‧‧重佈線層 112‧‧‧介電層 114‧‧‧金屬層 116‧‧‧凸塊 130‧‧‧銅擠出缺陷 200‧‧‧載板 300‧‧‧回火製程
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。 第1圖至第6圖為依據本發明一實施例所繪示的一種半導體裝置的製作方法的剖面示意圖。
100‧‧‧晶圓
100a‧‧‧正面
100b‧‧‧背面
101‧‧‧穿板通孔
102‧‧‧銅金屬層
103‧‧‧矽氧層
110‧‧‧重佈線層
112‧‧‧介電層
114‧‧‧金屬層
116‧‧‧凸塊
130‧‧‧銅擠出缺陷
200‧‧‧載板
300‧‧‧回火製程

Claims (6)

  1. 一種半導體裝置的製作方法，包含：提供一晶圓，具有一正面與一背面；於該正面形成複數個穿板通孔(through substrate via，TSV)；於該複數個TSV上形成一重佈線層；將該晶圓接合一載板；於該背面進行一晶背研磨製程，薄化該晶圓，並使該TSV的一端從該背面顯露出來；進行一回火製程，再結晶該TSV；以及在該回火製程之後，進行一化學機械研磨製程，研磨該晶圓的該背面。
  2. 如申請專利範圍第1項所述的半導體裝置的製作方法，其中於該正面形成複數個穿板通孔係包含：於該正面形成複數個TSV孔洞至該晶圓一主表面以下的一預定深度；利用一介電層於該TSV孔洞內形成絕緣內壁；以及於該TSV孔洞內填入金屬。
  3. 如申請專利範圍第1項所述的半導體裝置的製作方法，其中該回火製程係在200℃下進行。
  4. 如申請專利範圍第1項所述的半導體裝置的製作方法，其中該重佈線層包含至少一介電層及至少一金屬層。
  5. 如申請專利範圍第1項所述的半導體裝置的製作方法，其中另包含於 該重佈線層上形成複數個凸塊。
  6. 如申請專利範圍第1項所述的半導體裝置的製作方法，其中在完成該化學機械研磨製程之後，另包含分離該載板。
TW105107836A 2016-01-21 2016-03-15 半導體裝置的製作方法 TWI606528B (zh)

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US15/002,404 US9899260B2 (en) 2016-01-21 2016-01-21 Method for fabricating a semiconductor device

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