FR3051971A1 - - Google Patents

Download PDF

Info

Publication number
FR3051971A1
FR3051971A1 FR1654831A FR1654831A FR3051971A1 FR 3051971 A1 FR3051971 A1 FR 3051971A1 FR 1654831 A FR1654831 A FR 1654831A FR 1654831 A FR1654831 A FR 1654831A FR 3051971 A1 FR3051971 A1 FR 3051971A1
Authority
FR
France
Prior art keywords
contact pads
layer
semiconductor
temporary support
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR1654831A
Other languages
English (en)
French (fr)
Other versions
FR3051971B1 (fr
Inventor
Bich-Yen Nguyen
Ludovic Ecarnot
Mohamed Nadia Ben
Christophe Maleville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1654831A priority Critical patent/FR3051971B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/EP2017/062556 priority patent/WO2017207390A1/en
Priority to CN201780032360.1A priority patent/CN109196627B/zh
Priority to DE112017002718.7T priority patent/DE112017002718T5/de
Priority to SG11201810104VA priority patent/SG11201810104VA/en
Priority to SG10201913072VA priority patent/SG10201913072VA/en
Priority to KR1020187034604A priority patent/KR102397140B1/ko
Priority to US16/305,695 priority patent/US11114314B2/en
Priority to TW106117418A priority patent/TWI712106B/zh
Publication of FR3051971A1 publication Critical patent/FR3051971A1/fr
Application granted granted Critical
Publication of FR3051971B1 publication Critical patent/FR3051971B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H10W74/019
    • H10P54/00
    • H10P72/74
    • H10P90/1906
    • H10W10/181
    • H10W70/05
    • H10W70/611
    • H10W70/685
    • H10W74/014
    • H10W74/114
    • H10P30/204
    • H10P30/208
    • H10P72/7412
    • H10P72/7426
    • H10P72/743
    • H10P72/7438
    • H10P72/744
    • H10W70/60
    • H10W70/66
    • H10W72/01255
    • H10W72/01257
    • H10W72/0198
    • H10W72/072
    • H10W72/07207
    • H10W72/07307
    • H10W72/07337
    • H10W72/241
    • H10W72/244
    • H10W72/344
    • H10W72/922
    • H10W80/211
    • H10W80/301
    • H10W90/00
    • H10W90/722
    • H10W90/724
    • H10W90/732
    • H10W90/792
    • H10W90/794
    • H10W99/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
FR1654831A 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur Active FR3051971B1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR1654831A FR3051971B1 (fr) 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
CN201780032360.1A CN109196627B (zh) 2016-05-30 2017-05-24 包含无任何贯通孔的内插层的半导体结构的制造方法
DE112017002718.7T DE112017002718T5 (de) 2016-05-30 2017-05-24 Verfahren zur Herstellung einer Halbleiterstruktur mit einer Zwischenlage, die keine Kontaktdurchführung aufweist
SG11201810104VA SG11201810104VA (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via
PCT/EP2017/062556 WO2017207390A1 (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via
SG10201913072VA SG10201913072VA (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via
KR1020187034604A KR102397140B1 (ko) 2016-05-30 2017-05-24 임의의 관통 비아가 없는 인터포저를 포함하는 반도체 구조의 제조 방법
US16/305,695 US11114314B2 (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via
TW106117418A TWI712106B (zh) 2016-05-30 2017-05-25 用於製作包含中介層之半導體結構之方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1654831 2016-05-30
FR1654831A FR3051971B1 (fr) 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur

Publications (2)

Publication Number Publication Date
FR3051971A1 true FR3051971A1 (enExample) 2017-12-01
FR3051971B1 FR3051971B1 (fr) 2019-12-13

Family

ID=56684055

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1654831A Active FR3051971B1 (fr) 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur

Country Status (8)

Country Link
US (1) US11114314B2 (enExample)
KR (1) KR102397140B1 (enExample)
CN (1) CN109196627B (enExample)
DE (1) DE112017002718T5 (enExample)
FR (1) FR3051971B1 (enExample)
SG (2) SG10201913072VA (enExample)
TW (1) TWI712106B (enExample)
WO (1) WO2017207390A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202038266A (zh) * 2018-11-26 2020-10-16 瑞典商斯莫勒科技公司 具有離散的能量儲存構件之半導體組件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851A1 (fr) * 1996-05-15 1997-11-21 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
EP1014452A1 (en) * 1998-02-25 2000-06-28 Seiko Epson Corporation Method of detaching thin-film device, method of transferring thin-film device, thin-film device, active matrix substrate, and liquid crystal display
US6503778B1 (en) * 1999-09-28 2003-01-07 Sony Corporation Thin film device and method of manufacturing the same
US20030219969A1 (en) * 2002-05-24 2003-11-27 Fujitsu Limited Semiconductor device and manufacturing method thereof
EP1517363A2 (en) * 2003-09-18 2005-03-23 Sharp Kabushiki Kaisha Thin film semiconductor device and fabrication method therefor
FR2928031A1 (fr) * 2008-02-25 2009-08-28 Soitec Silicon On Insulator Procede de transfert d'une couche mince sur un substrat support.

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484962B1 (ko) 1996-07-12 2005-04-25 후지쯔 가부시끼가이샤 반도체 장치의 제조 방법 및 반도체 장치
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
FR2898430B1 (fr) * 2006-03-13 2008-06-06 Soitec Silicon On Insulator Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede
US20100109169A1 (en) 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
FR2936357B1 (fr) * 2008-09-24 2010-12-10 Commissariat Energie Atomique Procede de report de puces sur un substrat.
US8970045B2 (en) * 2011-03-31 2015-03-03 Soitec Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
US8728863B2 (en) * 2011-08-09 2014-05-20 Soitec Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods
WO2013095544A1 (en) 2011-12-22 2013-06-27 Intel Corporation 3d integrated circuit package with window interposer
US8685761B2 (en) * 2012-02-02 2014-04-01 Harris Corporation Method for making a redistributed electronic device using a transferrable redistribution layer
TWI517274B (zh) * 2012-03-21 2016-01-11 矽品精密工業股份有限公司 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法
US8963285B2 (en) * 2013-03-08 2015-02-24 Infineon Technologies Ag Semiconductor device and method of manufacturing thereof
US20140339706A1 (en) * 2013-05-17 2014-11-20 Nvidia Corporation Integrated circuit package with an interposer formed from a reusable carrier substrate
US9209142B1 (en) * 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851A1 (fr) * 1996-05-15 1997-11-21 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
EP1014452A1 (en) * 1998-02-25 2000-06-28 Seiko Epson Corporation Method of detaching thin-film device, method of transferring thin-film device, thin-film device, active matrix substrate, and liquid crystal display
US6503778B1 (en) * 1999-09-28 2003-01-07 Sony Corporation Thin film device and method of manufacturing the same
US20030219969A1 (en) * 2002-05-24 2003-11-27 Fujitsu Limited Semiconductor device and manufacturing method thereof
EP1517363A2 (en) * 2003-09-18 2005-03-23 Sharp Kabushiki Kaisha Thin film semiconductor device and fabrication method therefor
FR2928031A1 (fr) * 2008-02-25 2009-08-28 Soitec Silicon On Insulator Procede de transfert d'une couche mince sur un substrat support.

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BENGTSSON S ET AL (EDS.): "Semiconductor Wafer Bonding VII: Science, Technology, and Applications, Proceedings of the International Symposium, April/May 2003, Paris, France, Electrochemical Society Proceedings", vol. 19, 2003, THE ELECTROCHEMICAL SOCIETY, INC., article LAGAHE-BLANCHARD C ET AL: "Hydrogen and helium implantation to achieve layer transfer", pages: 346 - 358, XP009193304 *

Also Published As

Publication number Publication date
US11114314B2 (en) 2021-09-07
KR20190015707A (ko) 2019-02-14
US20200328094A1 (en) 2020-10-15
TW201742189A (zh) 2017-12-01
SG11201810104VA (en) 2018-12-28
CN109196627B (zh) 2023-08-08
WO2017207390A1 (en) 2017-12-07
CN109196627A (zh) 2019-01-11
SG10201913072VA (en) 2020-03-30
FR3051971B1 (fr) 2019-12-13
TWI712106B (zh) 2020-12-01
KR102397140B1 (ko) 2022-05-16
DE112017002718T5 (de) 2019-02-28

Similar Documents

Publication Publication Date Title
EP2054929B1 (fr) Procede de fabrication collective de modules electroniques 3d
EP1576658B1 (fr) Procede de realisation de substrats mixtes et structure ainsi obtenue
FR2966283A1 (fr) Procede pour realiser une structure de collage
EP2960937B1 (fr) Circuit integre comportant un dissipateur de chaleur
EP2053646A1 (fr) Procede d'interconnexion verticale au sein de modules electroniques 3D utilisant des vias
EP2192612A2 (fr) Procédé pour empiler et interconnecter des circuits intégrés
FR3007403A1 (fr) Procede de realisation d'un dispositif microelectronique mecaniquement autonome
EP3593376B1 (fr) Procédé d'auto-assemblage de composants microélectroniques
FR2960346B1 (fr) Procede de fabrication d'une batterie en couche mince et batterie ainsi realisee
EP3579286B1 (fr) Puce photonique traversée par un via
EP3261116B1 (fr) Procede de fabrication collective de modules electroniques 3d
FR2969664A1 (fr) Procede de clivage d'un substrat
FR2943177A1 (fr) Procede de fabrication d'une structure multicouche avec report de couche circuit
FR2983638A1 (fr) Procede de formation d'un circuit integre
FR2990297A1 (fr) Empilement de structures semi-conductrices et procede de fabrication correspondant
EP3948940A1 (fr) Procédé de transfert de paves d'un substrat donneur sur un substrat receveur
FR2973938A1 (fr) Procédés de formation de structures semi-conductrices collées, et structures semi-conductrices formées par ces procédés
FR3051971A1 (enExample)
WO2024132489A1 (fr) Procédé de collage de deux couches réduisant les contraintes
FR2910704A1 (fr) Procede de realisation d'un dispositif a circuit integre interconnecte
EP2791969A1 (fr) Formation d'une connexion electrique du type via
EP3776642B1 (fr) Procédé de fabrication d'un substrat donneur pour la réalisation d'une structure intégrée en trois dimensions et procédé de fabrication d'une telle structure intégrée
FR2978296A1 (fr) Puce electronique comportant des piliers de connexion, et procede de fabrication
FR2993398A1 (fr) Structures semi-conductrices comprenant des microcanaux fluidiques pour le refroidissement et procédés associés.
FR3160266A1 (fr) Substrat semi-conducteur pour separation par laser et procédé de fabrication de structures semi-conductrices en trois dimensions

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20171201

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

PLFP Fee payment

Year of fee payment: 9

PLFP Fee payment

Year of fee payment: 10