FR2898430B1 - Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede - Google Patents

Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede

Info

Publication number
FR2898430B1
FR2898430B1 FR0602178A FR0602178A FR2898430B1 FR 2898430 B1 FR2898430 B1 FR 2898430B1 FR 0602178 A FR0602178 A FR 0602178A FR 0602178 A FR0602178 A FR 0602178A FR 2898430 B1 FR2898430 B1 FR 2898430B1
Authority
FR
France
Prior art keywords
epitaxia
producing
thin layer
support substrate
amorphous material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0602178A
Other languages
English (en)
Other versions
FR2898430A1 (fr
Inventor
Xavier Hebras
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0602178A priority Critical patent/FR2898430B1/fr
Priority to US11/504,256 priority patent/US7585749B2/en
Priority to JP2008558811A priority patent/JP5133908B2/ja
Priority to KR1020087021287A priority patent/KR101015159B1/ko
Priority to CN2007800089418A priority patent/CN101421837B/zh
Priority to PCT/EP2007/052372 priority patent/WO2007104767A1/fr
Priority to EP07726870.4A priority patent/EP2005466B1/fr
Publication of FR2898430A1 publication Critical patent/FR2898430A1/fr
Application granted granted Critical
Publication of FR2898430B1 publication Critical patent/FR2898430B1/fr
Priority to US12/535,056 priority patent/US8212249B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
FR0602178A 2006-03-13 2006-03-13 Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede Active FR2898430B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0602178A FR2898430B1 (fr) 2006-03-13 2006-03-13 Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede
US11/504,256 US7585749B2 (en) 2006-03-13 2006-08-14 Methods of forming a layer of material on a substrate and structures formed therefrom
KR1020087021287A KR101015159B1 (ko) 2006-03-13 2007-03-13 지지 기판에 에피탁시에 의해 수득된 비결정질 물질의 하나이상의 박층을 포함하는 구조물을 제조하는 방법 및 이러한 방법에 따라 수득된 구조물
CN2007800089418A CN101421837B (zh) 2006-03-13 2007-03-13 在支撑衬底上通过外延获得的非晶材料中制造包括至少一个薄层的结构的方法和根据该方法获得的结构
JP2008558811A JP5133908B2 (ja) 2006-03-13 2007-03-13 エピタキシによって支持基板上に得られる、非晶質材料の少なくとも１層の薄層を備える構造を製作する方法、およびその方法により得られた構造
PCT/EP2007/052372 WO2007104767A1 (fr) 2006-03-13 2007-03-13 procédé de fabrication d'une structure comprenant au moins une mince couche DE matériau amorphe obtenu par épitaxie sur un substrat support et structure obtenue selon ledit procédé
EP07726870.4A EP2005466B1 (fr) 2006-03-13 2007-03-13 Procede de fabrication d'une structure comprenant au moins une couche mince de materiau amorphe obtenue par epitaxie sur un substrat support
US12/535,056 US8212249B2 (en) 2006-03-13 2009-08-04 Methods of forming a layer of material on a substrate and structures formed therefrom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0602178A FR2898430B1 (fr) 2006-03-13 2006-03-13 Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede

Publications (2)

Publication Number Publication Date
FR2898430A1 FR2898430A1 (fr) 2007-09-14
FR2898430B1 true FR2898430B1 (fr) 2008-06-06

Family

ID=37103175

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0602178A Active FR2898430B1 (fr) 2006-03-13 2006-03-13 Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede

Country Status (7)

Country Link
US (2) US7585749B2 (fr)
EP (1) EP2005466B1 (fr)
JP (1) JP5133908B2 (fr)
KR (1) KR101015159B1 (fr)
CN (1) CN101421837B (fr)
FR (1) FR2898430B1 (fr)
WO (1) WO2007104767A1 (fr)

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DE102007052626B4 (de) 2007-11-05 2018-05-30 Robert Bosch Gmbh Verfahren zur Herstellung von porösen Strukturen in auf Silizium basierenden Halbleiterstrukturen
EP2281307A4 (fr) * 2008-05-28 2011-06-29 Sarnoff Corp Imageur rétroéclairé au silicium ultra mince sur substrats isolants
FR2935067B1 (fr) 2008-08-14 2011-02-25 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice plan de masse enterre
EP2200084A1 (fr) * 2008-12-22 2010-06-23 S.O.I. TEC Silicon Procédé de fabrication d'un capteur d'image rétro-éclairé
US20100216295A1 (en) * 2009-02-24 2010-08-26 Alex Usenko Semiconductor on insulator made using improved defect healing process
JP2012033750A (ja) * 2010-07-30 2012-02-16 Toshiba Corp 半導体装置及びその製造方法
FR2978603B1 (fr) * 2011-07-28 2013-08-23 Soitec Silicon On Insulator Procede de transfert d'une couche semi-conductrice monocristalline sur un substrat support
US8669135B2 (en) * 2012-08-10 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for fabricating a 3D image sensor structure
US9490201B2 (en) * 2013-03-13 2016-11-08 Intel Corporation Methods of forming under device interconnect structures
US9111996B2 (en) * 2013-10-16 2015-08-18 Taiwan Semiconductor Manufacturing Company Limited Semiconductor-on-insulator structure and method of fabricating the same
US9385022B2 (en) * 2014-05-21 2016-07-05 Globalfoundries Inc. Silicon waveguide on bulk silicon substrate and methods of forming
WO2016006663A1 (fr) * 2014-07-10 2016-01-14 株式会社豊田自動織機 Substrat semi-conducteur et procédé de fabrication de substrat semi-conducteur
KR102365963B1 (ko) 2015-06-23 2022-02-23 삼성디스플레이 주식회사 박막 트랜지스터, 이의 제조 방법 및 이를 갖는 액정 표시 장치
FR3045934B1 (fr) 2015-12-22 2018-02-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d’un empilement de dispositifs electroniques
FR3045935B1 (fr) 2015-12-22 2018-02-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d’un empilement de dispositifs electroniques.
FR3051971B1 (fr) * 2016-05-30 2019-12-13 Soitec Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
US10840080B2 (en) * 2017-09-20 2020-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming SOI substrates
FR3077924B1 (fr) * 2018-02-13 2020-01-17 Soitec Structure demontable et procede de demontage utilisant ladite structure
US10790145B2 (en) 2018-09-05 2020-09-29 Micron Technology, Inc. Methods of forming crystallized materials from amorphous materials
US10707298B2 (en) 2018-09-05 2020-07-07 Micron Technology, Inc. Methods of forming semiconductor structures
US11018229B2 (en) 2018-09-05 2021-05-25 Micron Technology, Inc. Methods of forming semiconductor structures
FR3091620B1 (fr) * 2019-01-07 2021-01-29 Commissariat Energie Atomique Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture
US12009252B2 (en) * 2021-04-05 2024-06-11 Alexander Yuri Usenko Method of making a silicon on insulator wafer

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05251292A (ja) * 1992-03-06 1993-09-28 Nec Corp 半導体装置の製造方法
JPH07231073A (ja) * 1994-02-17 1995-08-29 Canon Inc 半導体基板及びその製造方法
JPH07283381A (ja) * 1994-04-08 1995-10-27 Canon Inc 貼合わせ半導体基体の製造方法
JP3257624B2 (ja) * 1996-11-15 2002-02-18 キヤノン株式会社 半導体部材の製造方法
JPH1174209A (ja) * 1997-08-27 1999-03-16 Denso Corp 半導体基板の製造方法
JP2000349266A (ja) * 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
US6333217B1 (en) * 1999-05-14 2001-12-25 Matsushita Electric Industrial Co., Ltd. Method of forming MOSFET with channel, extension and pocket implants
EP1212787B1 (fr) * 1999-08-10 2014-10-08 Silicon Genesis Corporation Procede de clivage permettant de fabriquer des substrats multicouche a l'aide de faibles doses d'implantation
US7183177B2 (en) * 2000-08-11 2007-02-27 Applied Materials, Inc. Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement
JP2002305293A (ja) * 2001-04-06 2002-10-18 Canon Inc 半導体部材の製造方法及び半導体装置の製造方法
US20050026432A1 (en) * 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
US6696352B1 (en) * 2001-09-11 2004-02-24 Silicon Wafer Technologies, Inc. Method of manufacture of a multi-layered substrate with a thin single crystalline layer and a versatile sacrificial layer
US20030096490A1 (en) * 2001-11-16 2003-05-22 John Borland Method of forming ultra shallow junctions
ITTO20011129A1 (it) * 2001-12-04 2003-06-04 Infm Istituto Naz Per La Fisi Metodo per la soppressione della diffusione anomala transiente di droganti in silicio.
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US6638872B1 (en) * 2002-09-26 2003-10-28 Motorola, Inc. Integration of monocrystalline oxide devices with fully depleted CMOS on non-silicon substrates
US20040262686A1 (en) * 2003-06-26 2004-12-30 Mohamad Shaheen Layer transfer technique
US7109099B2 (en) * 2003-10-17 2006-09-19 Chartered Semiconductor Manufacturing Ltd. End of range (EOR) secondary defect engineering using substitutional carbon doping

Also Published As

Publication number Publication date
US8212249B2 (en) 2012-07-03
KR20080100222A (ko) 2008-11-14
US20100044706A1 (en) 2010-02-25
JP5133908B2 (ja) 2013-01-30
JP2009529800A (ja) 2009-08-20
CN101421837B (zh) 2011-06-15
US20070210307A1 (en) 2007-09-13
KR101015159B1 (ko) 2011-02-16
EP2005466A1 (fr) 2008-12-24
FR2898430A1 (fr) 2007-09-14
EP2005466B1 (fr) 2013-07-17
CN101421837A (zh) 2009-04-29
WO2007104767A1 (fr) 2007-09-20
US7585749B2 (en) 2009-09-08

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