FR3051971B1 - Procede de fabrication d'une structure semi-conductrice comprenant un interposeur - Google Patents

Procede de fabrication d'une structure semi-conductrice comprenant un interposeur Download PDF

Info

Publication number
FR3051971B1
FR3051971B1 FR1654831A FR1654831A FR3051971B1 FR 3051971 B1 FR3051971 B1 FR 3051971B1 FR 1654831 A FR1654831 A FR 1654831A FR 1654831 A FR1654831 A FR 1654831A FR 3051971 B1 FR3051971 B1 FR 3051971B1
Authority
FR
France
Prior art keywords
temporary support
semiconductor structure
interposer
manufacturing
structure including
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1654831A
Other languages
English (en)
French (fr)
Other versions
FR3051971A1 (enExample
Inventor
Bich-Yen Nguyen
Ludovic Ecarnot
Nadia Ben Mohamed
Christophe Maleville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR1654831A priority Critical patent/FR3051971B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/EP2017/062556 priority patent/WO2017207390A1/en
Priority to CN201780032360.1A priority patent/CN109196627B/zh
Priority to DE112017002718.7T priority patent/DE112017002718T5/de
Priority to SG11201810104VA priority patent/SG11201810104VA/en
Priority to SG10201913072VA priority patent/SG10201913072VA/en
Priority to KR1020187034604A priority patent/KR102397140B1/ko
Priority to US16/305,695 priority patent/US11114314B2/en
Priority to TW106117418A priority patent/TWI712106B/zh
Publication of FR3051971A1 publication Critical patent/FR3051971A1/fr
Application granted granted Critical
Publication of FR3051971B1 publication Critical patent/FR3051971B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H10W74/019—
    • H10P54/00—
    • H10P72/74—
    • H10P90/1906—
    • H10W10/181—
    • H10W70/05—
    • H10W70/611—
    • H10W70/685—
    • H10W74/014—
    • H10W74/114—
    • H10P30/204—
    • H10P30/208—
    • H10P72/7412—
    • H10P72/7426—
    • H10P72/743—
    • H10P72/7438—
    • H10P72/744—
    • H10W70/60—
    • H10W70/66—
    • H10W72/01255—
    • H10W72/01257—
    • H10W72/0198—
    • H10W72/072—
    • H10W72/07207—
    • H10W72/07307—
    • H10W72/07337—
    • H10W72/241—
    • H10W72/244—
    • H10W72/344—
    • H10W72/922—
    • H10W80/211—
    • H10W80/301—
    • H10W90/00—
    • H10W90/722—
    • H10W90/724—
    • H10W90/732—
    • H10W90/792—
    • H10W90/794—
    • H10W99/00—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
FR1654831A 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur Active FR3051971B1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR1654831A FR3051971B1 (fr) 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
CN201780032360.1A CN109196627B (zh) 2016-05-30 2017-05-24 包含无任何贯通孔的内插层的半导体结构的制造方法
DE112017002718.7T DE112017002718T5 (de) 2016-05-30 2017-05-24 Verfahren zur Herstellung einer Halbleiterstruktur mit einer Zwischenlage, die keine Kontaktdurchführung aufweist
SG11201810104VA SG11201810104VA (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via
PCT/EP2017/062556 WO2017207390A1 (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via
SG10201913072VA SG10201913072VA (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via
KR1020187034604A KR102397140B1 (ko) 2016-05-30 2017-05-24 임의의 관통 비아가 없는 인터포저를 포함하는 반도체 구조의 제조 방법
US16/305,695 US11114314B2 (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via
TW106117418A TWI712106B (zh) 2016-05-30 2017-05-25 用於製作包含中介層之半導體結構之方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1654831 2016-05-30
FR1654831A FR3051971B1 (fr) 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur

Publications (2)

Publication Number Publication Date
FR3051971A1 FR3051971A1 (enExample) 2017-12-01
FR3051971B1 true FR3051971B1 (fr) 2019-12-13

Family

ID=56684055

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1654831A Active FR3051971B1 (fr) 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur

Country Status (8)

Country Link
US (1) US11114314B2 (enExample)
KR (1) KR102397140B1 (enExample)
CN (1) CN109196627B (enExample)
DE (1) DE112017002718T5 (enExample)
FR (1) FR3051971B1 (enExample)
SG (2) SG10201913072VA (enExample)
TW (1) TWI712106B (enExample)
WO (1) WO2017207390A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202038266A (zh) * 2018-11-26 2020-10-16 瑞典商斯莫勒科技公司 具有離散的能量儲存構件之半導體組件

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
KR100484962B1 (ko) 1996-07-12 2005-04-25 후지쯔 가부시끼가이샤 반도체 장치의 제조 방법 및 반도체 장치
JP3809733B2 (ja) * 1998-02-25 2006-08-16 セイコーエプソン株式会社 薄膜トランジスタの剥離方法
JP2001102523A (ja) * 1999-09-28 2001-04-13 Sony Corp 薄膜デバイスおよびその製造方法
FR2809867B1 (fr) * 2000-05-30 2003-10-24 Commissariat Energie Atomique Substrat fragilise et procede de fabrication d'un tel substrat
US6794273B2 (en) * 2002-05-24 2004-09-21 Fujitsu Limited Semiconductor device and manufacturing method thereof
JP4651924B2 (ja) * 2003-09-18 2011-03-16 シャープ株式会社 薄膜半導体装置および薄膜半導体装置の製造方法
FR2898430B1 (fr) * 2006-03-13 2008-06-06 Soitec Silicon On Insulator Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede
FR2928031B1 (fr) * 2008-02-25 2010-06-11 Soitec Silicon On Insulator Procede de transfert d'une couche mince sur un substrat support.
US20100109169A1 (en) 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
FR2936357B1 (fr) * 2008-09-24 2010-12-10 Commissariat Energie Atomique Procede de report de puces sur un substrat.
US8970045B2 (en) * 2011-03-31 2015-03-03 Soitec Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
US8728863B2 (en) * 2011-08-09 2014-05-20 Soitec Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods
WO2013095544A1 (en) 2011-12-22 2013-06-27 Intel Corporation 3d integrated circuit package with window interposer
US8685761B2 (en) * 2012-02-02 2014-04-01 Harris Corporation Method for making a redistributed electronic device using a transferrable redistribution layer
TWI517274B (zh) * 2012-03-21 2016-01-11 矽品精密工業股份有限公司 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法
US8963285B2 (en) * 2013-03-08 2015-02-24 Infineon Technologies Ag Semiconductor device and method of manufacturing thereof
US20140339706A1 (en) * 2013-05-17 2014-11-20 Nvidia Corporation Integrated circuit package with an interposer formed from a reusable carrier substrate
US9209142B1 (en) * 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal

Also Published As

Publication number Publication date
US11114314B2 (en) 2021-09-07
FR3051971A1 (enExample) 2017-12-01
KR20190015707A (ko) 2019-02-14
US20200328094A1 (en) 2020-10-15
TW201742189A (zh) 2017-12-01
SG11201810104VA (en) 2018-12-28
CN109196627B (zh) 2023-08-08
WO2017207390A1 (en) 2017-12-07
CN109196627A (zh) 2019-01-11
SG10201913072VA (en) 2020-03-30
TWI712106B (zh) 2020-12-01
KR102397140B1 (ko) 2022-05-16
DE112017002718T5 (de) 2019-02-28

Similar Documents

Publication Publication Date Title
MY195790A (en) Wafer Producing Method and Wafer Producing Apparatus
WO2018217696A3 (en) ARTICLES WITH INTERCONNECTION HOLES HAVING GEOMETRIC ATTRIBUTES AND METHODS OF MANUFACTURING THE SAME
FR2967204B1 (fr) Procede de fabrication d'un composant utilisant un revetement fugitif
SG11201810783UA (en) Device for Handling a Semiconductor Wafer in an Epitaxy Reactor and Method for Producing a Semiconductor Wafer Having an Epitaxial Layer
MY181116A (en) Wafer producing method
TW200710980A (en) Method for manufacturing semiconductor device
SG10201908095TA (en) Pretreatment of nickel and cobalt liners for electrodeposition of copper into through silicon vias
SG10201805702QA (en) Method of forming an integrated circuit and related integrated circuit
EP3352207A4 (en) METHOD FOR DISCONNECTING A SEMICONDUCTOR SUBSTRATE BODY FROM A FUNCTION LAYER THEREOF
WO2015038367A3 (en) Forming through wafer vias in glass
GB2488908A (en) Tunnel junction via
SG10201803755PA (en) Method for uniform flow behavior in an electroplating cell
GB2555269A (en) Structure and fabrication method for electromigration immortal nanoscale interconnects
JP2015173168A (ja) チップ整列方法
CL2017001878A1 (es) Pilote para cimentación, procedimiento de inyección de dicho pilote y procedimiento de fabricación del mismo.
FR3045678B1 (fr) Procede de fabrication d'une couche piezoelectrique monocristalline et dispositif microelectronique, photonique ou optique comprenant une telle couche
TW201612364A (en) Plating method
FR3031394B1 (fr) Procede de fabrication d'un substrat pour diffusion raman exaltee de surface
FR3051971B1 (fr) Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
MA46333A (fr) Plancher en béton, kit pour la réalisation d'un plancher en béton et procédé de réalisation d'un plancher en béton
SG11201807344RA (en) Method for determining a suitable implanting energy in a donor substrate and process for fabricating a structure of semiconductor–on–insulator type
WO2017164816A8 (en) A through silicon interposer wafer and method of manufacturing the same
FR3076170B1 (fr) Procede de report de structures electroluminescentes
FR3091032B1 (fr) Procédé de transfert d’une couche superficielle sur des cavités
FR3054930B1 (fr) Utilisation d'un champ electrique pour detacher une couche piezo-electrique a partir d'un substrat donneur

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20171201

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

PLFP Fee payment

Year of fee payment: 9

PLFP Fee payment

Year of fee payment: 10