JP2015173168A - チップ整列方法 - Google Patents
チップ整列方法 Download PDFInfo
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- JP2015173168A JP2015173168A JP2014047928A JP2014047928A JP2015173168A JP 2015173168 A JP2015173168 A JP 2015173168A JP 2014047928 A JP2014047928 A JP 2014047928A JP 2014047928 A JP2014047928 A JP 2014047928A JP 2015173168 A JP2015173168 A JP 2015173168A
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- H01L2224/95143—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium
- H01L2224/95146—Passive alignment, i.e. self alignment, e.g. using surface energy, chemical reactions, thermal equilibrium by surface tension
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- Physics & Mathematics (AREA)
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Abstract
Description
本実施の形態では、大きさが同じ複数のチップをウェーハ上に整列させるチップ整列方法について説明する。本実施の形態のチップ整列方法では、まず、チップを整列させるウェーハの表面側に、チップ載置領域を区画する複数の溝を形成する溝形成ステップを実施する。
本実施の形態では、大きさが異なる複数のチップ19をウェーハ11上に整列させるチップ整列方法について説明する。なお、本実施の形態に係るチップ整列方法は、多くの点において実施の形態1に係るチップ整列方法と共通している。よって、本実施の形態では、共通する部分についての詳細な説明を省略する。
11a 表面
11b 裏面
13 溝
15 チップ載置領域
15a 第1のチップ載置領域
15b 第2のチップ載置領域
17 液体
19 チップ
19a 第1のチップ
19b 第2のチップ
2 ノズル
Claims (3)
- 複数のチップをウェーハ上に整列させるチップ整列方法であって、
ウェーハの表面側にチップ載置領域をそれぞれ区画する交差した複数の溝を形成する溝形成ステップと、
該チップ載置領域に液体を供給する液体供給ステップと、
該液体供給ステップを実施した後、該液体上にチップを載置して該液体の表面張力でチップを該チップ載置領域に位置付けるチップ載置ステップと、
該チップ載置ステップを実施した後、該液体を除去することで該ウェーハ上に複数のチップを整列させる液体除去ステップと、を備えたことを特徴とするチップ整列方法。 - 該液体除去ステップは、複数のチップが該液体を介して載置されたウェーハを真空中に載置することで実施されることを特徴とする請求項1に記載のチップ整列方法。
- 該液体は、チップを該ウェーハ上に固定する接着剤成分を含むことを特徴とする請求項1又は請求項2に記載のチップ整列方法。
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JP2014047928A JP6278760B2 (ja) | 2014-03-11 | 2014-03-11 | チップ整列方法 |
TW104104246A TWI649814B (zh) | 2014-03-11 | 2015-02-09 | Wafer alignment method |
KR1020150030235A KR102210294B1 (ko) | 2014-03-11 | 2015-03-04 | 칩 정렬 방법 |
CN201510101174.1A CN104916556B (zh) | 2014-03-11 | 2015-03-06 | 芯片排列方法 |
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KR102349884B1 (ko) * | 2016-03-17 | 2022-01-12 | 도쿄엘렉트론가부시키가이샤 | 액체를 사용해서 기판에 대한 칩 부품의 얼라인먼트를 행하는 방법 |
JP2018064077A (ja) * | 2016-10-14 | 2018-04-19 | 株式会社ディスコ | デバイスチップ、収容トレイ、及び、デバイスチップの収容方法 |
JP6887722B2 (ja) * | 2016-10-25 | 2021-06-16 | 株式会社ディスコ | ウェーハの加工方法及び切削装置 |
KR101902566B1 (ko) | 2017-07-25 | 2018-09-28 | 엘지디스플레이 주식회사 | 발광 표시 장치 및 이의 제조 방법 |
CN110854057B (zh) * | 2019-11-14 | 2022-07-12 | 京东方科技集团股份有限公司 | 一种转移基板及其制作方法、转移方法 |
CN112992759B (zh) * | 2020-10-16 | 2022-04-19 | 重庆康佳光电技术研究院有限公司 | 一种器件转移设备及其制备方法、器件转移方法 |
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