CN109196627A - 包含无任何贯通孔的内插层的半导体结构的制造方法 - Google Patents

包含无任何贯通孔的内插层的半导体结构的制造方法 Download PDF

Info

Publication number
CN109196627A
CN109196627A CN201780032360.1A CN201780032360A CN109196627A CN 109196627 A CN109196627 A CN 109196627A CN 201780032360 A CN201780032360 A CN 201780032360A CN 109196627 A CN109196627 A CN 109196627A
Authority
CN
China
Prior art keywords
interconnection layer
temporary support
chip
layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201780032360.1A
Other languages
English (en)
Other versions
CN109196627B (zh
Inventor
比什-因·阮
卢多维克·埃卡尔诺
纳迪娅·本默罕默德
C·马勒维尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of CN109196627A publication Critical patent/CN109196627A/zh
Application granted granted Critical
Publication of CN109196627B publication Critical patent/CN109196627B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H01L2224/02313—Subtractive methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2902—Disposition
    • H01L2224/29024—Disposition the layer connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80003—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/80006—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及一种形成半导体结构的方法，所述方法包括：在选定条件下将氢物种和氦物种(例如离子)引入临时支撑件(1)，以便在其中预定深度处形成弱化平面(2)，并定义所述临时支撑件(1)的表面层(3)和剩余部分(4)；在所述临时支撑件(1)上形成互连层(5)；将至少一个半导体芯片(6)放置在所述互连层(5)上；将加固件(8)组装在所述至少一个半导体芯片(6)的背面上；和对所述临时支撑件(1)提供热能，以便分离所述剩余部分(4)并提供所述半导体结构。互连层(5)形成无任何贯通孔的内插层。

Description

包含无任何贯通孔的内插层的半导体结构的制造方法
技术领域
本发明涉及制造包含内插层的半导体结构的方法。
背景技术
内插层通常被用作被动元件，其允许半导体芯片或晶粒并排堆叠，使它们互相连接并与外部环境连接。内插层使具有不同功能(处理单元、内存、输入/输出)的芯片或晶粒能够混合，以形成呈现高带宽构造和紧凑形状因子的封装半导体装置。其避免在晶粒水平上集成所有功能元件，并加速了装置开发时间。
US2013/0214423揭示了内插层通常由足够厚的刚性材料层(例如大约200微米以上)形成，在其相对的面上呈现用于连接至半导体芯片和/或外部连接件的接触垫。内插层还包括贯穿该内插层的通孔，以便电连接在其相对面上的接触垫。
通常难以形成具有高深宽比(其定义为通孔的长度除以其截面的尺寸)(例如该比大于5)的通孔。因此，通孔具有通常大于20微米的最小横截面尺寸。这样的尺寸限制了在内插层的给定表面中可形成的通孔数目，从而限制了最终封装半导体装置的集成密度。不够紧凑的装置本身是问题的，因为其无法被放置在小尺寸的物品(智能手机、连网手表等)中。不够紧凑的装置也限制了性能，因为所需的较长连接线路可能影响传播信号的带宽和延迟。
新内插层方法，例如US2014/0191419中描述的不需要贯通孔的新内插层方法日益受到重视。
例如，US20030219969公开了一种封装有有微细结构的内插层的半导体装置的制造方法，该内插层使用硅基材形成。该方法包括以下步骤：在硅基材上形成可剥离的树脂层，在可剥离的树脂层上形成配线层，在配线基材上安装半导体芯片，通过用密封树脂密封多个半导体芯片形成半导体装置，通过从密封树脂侧切割该半导体装置但保留硅基材而获得单个的半导体装置，并且将单个的导体装置各自从硅基材上剥离。
该制造方法特别难以实施。其要求精细地控制结构中连续界面处的粘附力，使得当在装置上施加牵引力时能够在树脂层处精确地从基材上移除完整装置。同时，在该制造方法的最初阶段中，树脂层应提供足够的粘附以将不同层一起保持在硅基材上。
本发明的目的
本发明的目的在于形成这样的半导体装置：其包含至少一个半导体芯片或晶粒，和按路线发送来自该至少一个半导体芯片的导电部件的电信号/将电信号按路线发送至该至少一个半导体芯片的导电部件的内插层。该内插层无任何贯通孔，并且制造方法简单易行。
发明内容
为此目的，本发明涉及一种形成半导体结构的方法，所述方法包括：
·在选定植入条件下将氢离子和氦离子植入临时支撑件中，以便在其中预定深度处形成弱化平面，并定义所述临时支撑件的表面层和剩余部分；
·在所述临时支撑件上形成互连层，所述互连层包含接触垫和在所述接触垫之间的导电路径；
·将至少一个半导体芯片放置在所述互连层上以便将所述芯片的导电部件与所述互连层的接触垫电耦合；
·将加固件组装在所述至少一个半导体芯片的背面上；
·对所述临时支撑件提供热能和可选的机械能，以便分离所述剩余部分并提供所述半导体结构。
对该临时支撑件提供热能的步骤进一步弱化该弱化平面，且可同时增强该加固件对所述结构其余部分的粘合力。其有利于该支撑件的剩余部分的分离和通过施加适中的力移除该剩余部分，而没有使该加固件从所述结构其余部分分离的风险。
不论单独或以任何技术可行的组合实施，根据本发明另外的非限制性特征：
·引入所述氦物种的所述选定条件包括以1至2 1016at/cm3的剂量和以40keV至200keV的植入能量植入氦离子；
·引入所述氢物种的所述选定条件包括以0.5至1.5 1016at/cm3的剂量和以25keV至200keV的植入能量植入氢离子；
·所述互连层具有在所述半导体芯片一侧上的第一表面以及与所述第一表面相对的第二表面，并且其中所述接触垫同时设置在所述第一表面和第二表面上；
·所述方法包括在分离所述剩余部分后移除所述表面层，以便暴露所述互连层的第二表面的至少一些接触垫；
·所述方法包括在所述第一表面的所述接触垫上形成凸出部件，例如微凸块或金属凸点，以利于所述半导体芯片的导电部件与所述接触垫的电耦合；
·所述方法包括在所述表面层上和/或在所述表面层中形成基本器件；
·所述表面层呈现的厚度小于约10微米，优选小于1微米，更优选为50至600nm；
·分离两个并置的接触垫的距离为0.2微米至2微米；
·所述组装步骤在将所述至少一个半导体芯片放置在所述互连层上的步骤之前或之后进行；
·所述组装步骤还包括底料填充的步骤，以便在所述至少一个芯片周围的自由空间中提供填充材料；
·所述方法包括切割所述半导体结构以提供至少一个未加工半导体装置的步骤，和封装所述至少一个未加工半导体装置以形成最终半导体装置的步骤；
·所述互连层呈现的厚度为200nm至20微米；
·与形成所述互连层相关联的热预算为在低于250℃下4小时，或在350℃下少于20分钟；
·提供热能的步骤包括施加200℃至450℃的温度，持续10分钟至2小时的时间
附图说明
当结合附图考虑时，通过阅读以下详细描述，本发明的许多其它特征和优点将变得显而易见，其中：
-图1和2示出可通过本发明的方法制造的半导体结构；
-图3示出将氢物种和氦物种引入临时支撑件的步骤；
-图4示出形成互联层的步骤；
-图5示出将至少一个半导体芯片放置在互连层上的步骤；
-图6示出组装加固件的步骤；
-图7示出对临时支撑件提供能量以分离剩余部分的步骤；
-图8示出临时支撑件的剩余部分移除后的半导体结构。
具体实施方式
为了简化以下描述，对将要描述的本发明的不同实施方式中相同元件或实现相同功能的元件使用相同的附图标记。
图1示出可通过本发明的方法制造的半导体结构10。
半导体结构10包含由互连层5构成的内插层。互连层5包含优选地设置在其两侧表面上的接触垫5a，以及位于接触垫5a之间的导电路径5b。互连层5的厚度可呈现为200nm至20微米，通常为5至10微米。一些接触垫5a电耦合到至少一个半导体芯片6的导电部件6a。其它接触垫5a，尤其是设置在互连层5的暴露表面上的那些接触垫，可提供该半导体结构10的外部输入/输出连接。
如图1所示，接触垫5a可以较大密度设置在互连层5的各表面上。例如，两个并置的垫5a之间的距离可为0.2至2微米。
优选地，多个半导体芯片6设置并电耦合至互连层5。芯片6可具有不同尺寸，具有不同功能，且根据不同技术制成。例如，一个芯片6可为14nm技术CPU，而另一芯片6可为0.25微米技术输入/输出芯片。每个芯片6可为例如DRAM或SRAM内存芯片、CPU、GPU、微控制器或输入/输出芯片。
可选地，半导体结构10可包含设置在互连层5的暴露表面上的额外芯片6(图1未示出)。
互连层5允许将具有不同功能的那些不同芯片共同集成，以实现功能性半导体装置。互连层5的导电路径5b允许不同芯片6的导电部件6a电连接在一起，以使它们可以在功能上合作。为允许复杂的互连方案，互连层5可由多个堆叠的互连子层(例如2至4个子层)构成。
为促进芯片6的导电部件6a与互连层5的接触垫5a之间的电耦合，接触垫和/或导电部件6a可设置有凸出部件7a,7b，例如微凸块。
图1的半导体结构10还包括设置在芯片6背面的加固件8，以为该结构提供刚性支撑。加固件8可由任何适当的材料制成，例如硅或环氧树脂材料。芯片6、加固件8和互连层5之间的自由空间可填充有绝缘填充材料(例如二氧化硅)以保护半导体结构10并提高其刚性。
可选地，如图2所示，半导体结构10可在其与芯片6相对的表面上包括表面层3，表面层3位于互连层5上方或部分地位于互连层5上方。表面层3可包括与互连层5的一些接触垫5a耦合的基本器件11。基本器件11可为芯片6提供额外功能。它们可对应于例如薄膜晶体管、PN二极管或光子装置。
图1或图2的半导体结构10可以切割以形成未加工半导体装置，其随后可封装而形成本领域通常的最终半导体装置。封装可包括在设置在互连层5的暴露表面上的一些接触垫5a上形成接合引线(wire bond)以便对所述装置提供外部连接。
本发明涉及制造半导体结构10，例如图1或2所示的半导体结构10的方法。
参照图3，所述方法包括将氢物种和氦物种(例如氢离子和氦离子)引入临时支撑件1的步骤，以在该支撑件1的预定深度处形成弱化平面2。所述氢物种和氦物种可通过植入方式引入。弱化平面2定义该临时支撑件1的表面层3和剩余部分4。
出于成本和可用性的原因，该支撑件可对应于圆形的标准化尺寸的硅晶片。例如，该硅晶片可呈现200或300mm的直径和300至900微米的厚度。但本发明的方法不限于此种材料、形状和尺寸的临时支撑件。一般而言，该临时支撑件被选择成提供廉价、刚性且可自支撑的材料件。临时支撑件1可涂覆有一种或多种表面层材料，例如半导体材料、导体材料或绝缘材料。因此，表面层3也可包括临时支撑件1的一个或多个表面层。
取决于将在说明书的以下部分中更详细描述的植入条件，表面层3的厚度可呈现为小于约10微米，或小于1微米。优选地，该厚度为50至600nm。在某些情况中，表面层3会完全从最终结构中移除，因此其厚度不是特别重要。不过较薄的表面层3有利于其移除。
表面层厚度通常比剩余部分4的厚度低一个或两个10倍。因此，剩余部分4的厚度与临时支撑件1的厚度非常接近。
提供弱化平面2以允许且有利于在制造半导体结构10的方法的后续分离步骤中移除临时支撑件(更准确为临时支撑件1的剩余部分4)。
因此，在剩余部分4移除之前，应精确控制弱化平面2以使其在工序的后续步骤中保持足够稳定。平面2的弱化特别会受到这些后续步骤中涉及的热预算(thermal budget)影响。“足够稳定”是指平面2的弱化或弱化平面2在分离前的所述方法的后续步骤中的任何其它演变不应发展成表面层3的变形(例如通过经植入表面的起泡造成的变形)，也不应引起剩余部分4的过早分离。
然而，弱化平面2应被足够弱化，从而在分离步骤中提供合理的能量就能够移除剩余部分4。
根据本发明，过选定氢物种和氦物种的引入(即植入)条件而精确控制平面2的弱化程度。选择应考虑临时支撑件1的材料(其可能影响平面2的弱化演变)，还应考虑与分离步骤之前对临时支撑件施加的处理步骤相关的热预算(更广泛而言为能量预算)。
例如，氢离子和氦离子的植入可在下述植入条件下进行，特别是在硅临时支撑件中进行：
·氢剂量为0.5至1.5 1016at/cm3；植入能量为25keV，或更通常为10keV至200keV，或者10keV至80keV。
·氦剂量为1至2 1016at/cm3；植入能量为40keV，或更通常为10keV至200keV，或者10keV至80keV。
氢离子和氦离子可相继植入临时支撑件1，例如首先植入氦离子。也可以首先植入氢离子。一般而言，在所提出的范围内选择氦物种和氢物种的植入能量，由此在沿着临时支撑件深度的其各自的分布曲线的峰值彼此靠近，即小于150nm。
通过这些植入物种源和植入条件，显示出临时支撑件可接受与在250℃下处理大约4小时等价的热预算，而不会出现表面变形或引起剩余部分4分离的情况。“等价的热预算”意味着也可对临时支撑件1施加较短时间的较高温度；或者较长时间的较低温度。
还要注意的是，该热预算适用于在没有为经植入表面提供加固件的情况下的临时支撑件。因此，就相同的植入条件和所施加的热预算而言，起泡发展的动力学不同于已经设置有加固件的经植入基材的断裂动力学。
本发明的发明人观察到，可接受的热预算(即不会引起表面变形和/或过早分离)比可施加于设有已经单独由氢物种、单独由氦物种或由任何其它物种源所形成的弱化平面的临时支撑件的热预算更宽。发明人特别注意到，可以施用在250℃(或更低)进行4小时的处理的热预算或在350℃进行20分钟(或更短)的处理的热预算，而不会展现出表面变形或剩余部分4的过早分离。
在某些情况中，本发明的方法可包括在表面层3中和/或在表面层3上形成基本器件11的步骤。该步骤可在弱化平面2形成之前或之后进行。基本器件11可对应于例如薄膜晶体管、PN二极管或光子装置。基本器件优选地执行简单的电或光引导功能，而不需高性能水平，因为表面层3的材料质量可能因弱化平面2的形成而变差。
基本器件可通过半导体产业的任何已知技术形成，例如沉积、蚀刻、掺杂物植入或扩散等。
基本器件11可在弱化平面2形成后形成，但优选基本器件11在之前形成，使得基本器件的形成对于可由临时支撑件1接收的可接受的热预算没有影响。
在基本器件11是在弱化平面2形成后形成的情况中，与基本器件11的形成相关联的热预算应远低于可接受的热预算，换言之，例如，远低于约250℃达4小时，或远低于约350℃达20分钟。
如图4所示，本发明的方法还包括在临时支撑件1上形成互连层5的步骤，该互连层5包括接触垫5a和在接触垫5a之间的导电路径5b。
在所述方法的此阶段，互连层5呈现与临时支撑件1接触的第一表面，以及暴露的第二表面。优选地，接触垫5a设置在互连层5的两个表面上。
互连层5可利用诸如金属化或双镶嵌(dual damascene)等常规技术形成。其可包括介电沉积、依照定义的光刻胶图案进行蚀刻、屏障沉积、铝或铜沉积(例如通过电镀)和平坦化(例如通过化学机械平坦化)的连续步骤。互连层5可由多个堆叠的互连子层(例如2至4个子层)构成，以产生更复杂的互连方案。互连方案被设计成使半导体结构10的芯片6在功能上互相耦合并连到外部连接件。
与互连层5的形成相关的热预算通常为低于250℃达数小时，取决于构成互连层5的子层的数目。结合分离步骤之前的所有其它热预算，热预算不应超过可接受的热预算，例如在250℃处理4小时。
由于接触垫5a和导电路径5b基本上是通过沉积技术形成，因此互连层5不需要在厚的刚性材料中形成通孔。在第一或第二表面上的接触垫5a的密度可以非常高。例如，两个并置的接触垫5a之间的距离可为0.2微米至2微米。各接触垫(其表面部分)的尺寸可具有相同大小，为0.2微米至2微米。该尺寸比传统内插层方法中必需的常规通孔的尺寸小至少5倍。
形成互连层5的此步骤也可包括在暴露表面的至少一些接触垫5a上形成凸出部件7a，以促进与芯片6的导电部件6a的耦合。接触垫5a上的凸出部件7a可由微凸块构成。此种微凸块7a可通过在接触垫6a上的选择性金属生长而形成。作为另一选择，可通过蚀刻垫6a周围的绝缘材料使它们凸出于暴露表面，然后使凸起的金属熔融以形成凸点，从而形成金属凸点。
如果形成凸出部件7a的过程涉及显著的热预算，那么在分离步骤之前施加于弱化平面2的全部热预算不应超过可接受的热预算，例如在250℃处理4小时或在350℃处理20分钟。
如图5所示，制造半导体结构10的方法还包括将至少一个芯片6放置在互连层5上并将芯片8的导电部件8a与接触垫5a电耦合的步骤。
芯片6可包括凸出部件7b，其类似于针对在接触垫5a上形成凸出部件7a，例如微凸块或金属凸点，从而促进其与互连层5的电连接。芯片6的凸出部件7b可与互连层5的凸出部件7a接触(如图5所示)或直接与接触垫5a接触。
作为另一选择，可在芯片6的导电部件8a与接触垫5a之间通过诸如两个元件之间的直接“分子”结合或粘附结合形成直接接触。
优选地，放置至少一个芯片6的步骤包括放置多个芯片6。这可通过公知的“拾取和放置”技术实现。
此步骤优选在室温下进行，使得对分离步骤之前的可接受的热预算不会造成显著影响。
如上所述，芯片6可具有不同尺寸、技术和功能。每个芯片6可以是DRAM或SRAM内存、CPU、GPU、微控制器或输入/输出装置。
可将选择的芯片组如DRAM芯片、GPU芯片和I/O芯片放置于其在互连层5上的期望位置处，并通过互连层5以功能性方式电耦合在一起。
半导体结构10可由多个此类芯片组组成，使得在切割和封装后可共同制造多个半导体装置。
一旦将芯片6放置在互连层5上，则可用绝缘填充材料9填充在互连层5之上的芯片6周围的自由空间，以保护和强固组装件。填充材料可由二氧化硅构成，其以旋涂式玻璃技术设置在互连层5上和芯片6周围。如果填充材料呈现低密度，则有利于其沉积和底料填充。
还优选地，并且如图6所示，本发明的方法包括将加固件8组装在芯片6背面的步骤。加固件8由足够厚度的刚性材料制成，使得一旦移除临时支撑件1，半导体材料10能够自支撑。
加固件8可由例如硅晶片或一块环氧材料制成。其尺寸应至少对应于临时支撑件1的尺寸。
组装可通过粘附结合、直接结合或其它技术进行。优选地，选择的技术不包括暴露于高于室温的温度，以避免影响弱化平面2和引起临时支撑件1的剩余部分4的过早分离。
在替代方式中，可首先将芯片6的背面定位并固定在加固件8的预定位置上，然后将由芯片6与加固件8形成的组装件放置在连接层6上方，并使芯片6的所有导电部件6a与接触垫5a电耦合。
不论选择以何种方式将芯片6放置在互连层5上并组装加固件8，该过程都产生图6所示的构造。
如果组装加固件的过程，或用绝缘材料9底料填充芯片6周围空间的步骤涉及显著的热预算，那么在分离步骤之前施加于弱化平面2的全部热预算不应超过可接受的热预算，例如在250℃处理4小时。
制造半导体结构10的方法还包括对临时支撑件1(特别是对弱化平面2)提供能量的步骤，以分离剩余部分4并提供半导体结构10。此步骤如图7所示。
所提供的能量可为热能，例如在约400℃(更通常为200℃至450℃)进行10分钟至约2小时的时间的退火。导致剩余部分4从临时支撑件1分离的任何其它热处理可以是适宜的。除热处理外(或某些情况下作为热能的替代方案)，所提供的能量为机械能，例如在临时支撑件1的弱化平面2水平处插入刀片。
不论其形式为何，所施加的能量，加上在之前步骤中弱化平面所接受的能量，会造成支撑件1的剩余部分4分离，从而获得图8所示的半导体结构10。
对临时支撑件1提供热能的步骤是特别有利的，因为其进一步弱化了弱化平面，并同时强化了加固件对结构体其余部分的粘附。因此，其有利于支撑件1的剩余部分4的分离，以及通过施加适中的力而对该剩余部分的移除，且没有使加固件8从结构体其余部分分离的风险。
在可选的后续步骤中，表面层3可被完全移除(如果前一步骤中没有形成基本器件11)或部分移除(以保留基本器件11)。移除可通过选择性的干式或湿式蚀刻进行，例如在临时支撑件为硅的情况下使用KOH。
可由所公开的方法获得的半导体结构10在图1和2中示出。
显然，本发明不限于已描述的方法的具体实施方式。本发明还包括所附权利要求范围内的所有替代实施方式或额外步骤。
例如，基本器件11或额外基本器件11也可在提供能量并分离临时支撑件1的剩余部分4的步骤之后在表面层3中形成。
在可于分离步骤后进行的可选步骤中，可将额外的芯片6放置在互连层5的暴露表面上，并使其与接触垫5a电耦合。
如上所述，半导体结构10可以切割以形成未加工半导体装置，其随后可封装形成本领域通常的最终半导体装置。封装可包括在设置在互连层5的暴露表面上的一些接触垫5a上形成接合引线以便对所述装置提供外部连接。

Claims (16)

1.一种形成半导体结构(10)的方法，所述方法包括：
·在选定条件下将氢物种和氦物种引入临时支撑件(1)，以便在其中预定深度处形成弱化平面(2)，并定义所述临时支撑件(1)的表面层(3)和剩余部分(4)；
·在所述临时支撑件(1)上形成互连层(5)，所述互连层包含接触垫(5a)和在所述接触垫(5a)之间的导电路径(5b)；
·将至少一个半导体芯片(6)放置在所述互连层(5)上以使所述芯片的导电部件(6a)与所述互连层(5)的接触垫(5a)电耦合；
·将加固件(8)组装在所述至少一个半导体芯片(6)的背面上；
·对所述临时支撑件(1)提供热能和可选的机械能，以分离所述剩余部分(4)并提供所述半导体结构(10)。
2.如权利要求1所述的方法，其中，引入所述氦物种的所述选定条件包括以1至21016at/cm3的剂量和以40keV至200keV的植入能量植入氦离子。
3.如前述权利要求中任一项所述的方法，其中，引入所述氢物种的所述选定条件包括以0.5至1.5 1016at/cm3的剂量和以25keV至200keV的植入能量植入氢离子。
4.如前述权利要求中任一项所述的方法，其中，所述互连层(5)具有在所述半导体芯片(6)一侧上的第一表面以及与所述第一表面相对的第二表面，并且其中所述接触垫(5a)同时设置在所述第一表面和第二表面上。
5.如权利要求4所述的方法，所述方法还包括在分离所述剩余部分(4)后至少部分地移除所述表面层(3)，以暴露出所述互连层(5)的第二表面的至少一些接触垫(5a)。
6.如权利要求4或5所述的方法，所述方法还包括在所述第一表面的所述接触垫(5a)上形成凸出部件(7a)，例如微凸块或金属凸点，以利于所述半导体芯片(6)的导电部件(6a)与所述接触垫(5a)的电耦合。
7.如前述权利要求中任一项所述的方法，所述方法还包括在所述表面层(3)上和/或在所述表面层(3)中形成基本器件(11)的步骤。
8.如前述权利要求中任一项所述的方法，其中，所述表面层(3)呈现的厚度小于约10微米，优选小于1微米，更优选为50至600nm。
9.如前述权利要求中任一项所述的方法，其中，两个并置的接触垫(5a)之间的距离为0.2微米至2微米。
10.如权利要求1所述的方法，其中，所述组装步骤在将所述至少一个半导体芯片(6)放置在所述互连层(5)上的步骤之后进行。
11.如权利要求1所述的方法，其中，所述组装步骤在将所述至少一个半导体芯片(6)放置在所述互连层(5)上的步骤之后进行。
12.如前述两项权利要求所述的方法，其中，所述组装步骤还包括底料填充步骤，以在所述至少一个芯片(6)周围的自由空间中提供填充材料(9)。
13.如前述权利要求中任一项所述的方法，所述方法还包括切割所述半导体结构(10)以提供至少一个未加工半导体装置的步骤，和封装所述至少一个未加工半导体装置以形成最终半导体装置的步骤。
14.如前述权利要求中任一项所述的方法，其中，所述互连层(5)呈现的厚度为200nm至20微米。
15.如前述权利要求中任一项所述的方法，其中，与形成所述互连层(5)相关联的热预算为在低于250℃下4小时，或在350℃下少于20分钟。
16.如前述权利要求中任一项所述的方法，其中，提供热能的步骤包括施加200℃至450℃的温度，持续10分钟至2小时的时间。
CN201780032360.1A 2016-05-30 2017-05-24 包含无任何贯通孔的内插层的半导体结构的制造方法 Active CN109196627B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR1654831A FR3051971B1 (fr) 2016-05-30 2016-05-30 Procede de fabrication d'une structure semi-conductrice comprenant un interposeur
FR1654831 2016-05-30
PCT/EP2017/062556 WO2017207390A1 (en) 2016-05-30 2017-05-24 Method for fabrication of a semiconductor structure including an interposer free from any through via

Publications (2)

Publication Number Publication Date
CN109196627A true CN109196627A (zh) 2019-01-11
CN109196627B CN109196627B (zh) 2023-08-08

Family

ID=56684055

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201780032360.1A Active CN109196627B (zh) 2016-05-30 2017-05-24 包含无任何贯通孔的内插层的半导体结构的制造方法

Country Status (8)

Country Link
US (1) US11114314B2 (zh)
KR (1) KR102397140B1 (zh)
CN (1) CN109196627B (zh)
DE (1) DE112017002718T5 (zh)
FR (1) FR3051971B1 (zh)
SG (2) SG11201810104VA (zh)
TW (1) TWI712106B (zh)
WO (1) WO2017207390A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202038266A (zh) * 2018-11-26 2020-10-16 瑞典商斯莫勒科技公司 具有離散的能量儲存構件之半導體組件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030077885A1 (en) * 2000-05-30 2003-04-24 Bernard Aspar Embrittled substrate and method for making same
US20100075461A1 (en) * 2008-09-24 2010-03-25 Commissariat A L'energie Atomique Method for transferring chips onto a substrate
US20140339706A1 (en) * 2013-05-17 2014-11-20 Nvidia Corporation Integrated circuit package with an interposer formed from a reusable carrier substrate
CN104485316A (zh) * 2013-03-08 2015-04-01 英飞凌科技股份有限公司 半导体器件及其制造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2748851B1 (fr) * 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
EP0853337B1 (en) 1996-07-12 2004-09-29 Fujitsu Limited Method for manufacturing semiconductor device
JP3809733B2 (ja) * 1998-02-25 2006-08-16 セイコーエプソン株式会社 薄膜トランジスタの剥離方法
JP2001102523A (ja) * 1999-09-28 2001-04-13 Sony Corp 薄膜デバイスおよびその製造方法
US6794273B2 (en) * 2002-05-24 2004-09-21 Fujitsu Limited Semiconductor device and manufacturing method thereof
JP4651924B2 (ja) * 2003-09-18 2011-03-16 シャープ株式会社 薄膜半導体装置および薄膜半導体装置の製造方法
FR2898430B1 (fr) * 2006-03-13 2008-06-06 Soitec Silicon On Insulator Procede de realisation d'une structure comprenant au moins une couche mince en materiau amorphe obtenue par epitaxie sur un substrat support et structure obtenue suivant ledit procede
FR2928031B1 (fr) * 2008-02-25 2010-06-11 Soitec Silicon On Insulator Procede de transfert d'une couche mince sur un substrat support.
US20100109169A1 (en) * 2008-04-29 2010-05-06 United Test And Assembly Center Ltd Semiconductor package and method of making the same
US8970045B2 (en) 2011-03-31 2015-03-03 Soitec Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
US8728863B2 (en) * 2011-08-09 2014-05-20 Soitec Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods
JP6014907B2 (ja) 2011-12-22 2016-10-26 インテル・コーポレーション ウィンドウインタポーザを有する３ｄ集積回路パッケージ
US8685761B2 (en) * 2012-02-02 2014-04-01 Harris Corporation Method for making a redistributed electronic device using a transferrable redistribution layer
TWI517274B (zh) 2012-03-21 2016-01-11 矽品精密工業股份有限公司 晶圓級半導體封裝件之製法及其晶圓級封裝基板之製法
US9209142B1 (en) 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030077885A1 (en) * 2000-05-30 2003-04-24 Bernard Aspar Embrittled substrate and method for making same
US20100075461A1 (en) * 2008-09-24 2010-03-25 Commissariat A L'energie Atomique Method for transferring chips onto a substrate
CN104485316A (zh) * 2013-03-08 2015-04-01 英飞凌科技股份有限公司 半导体器件及其制造方法
US20140339706A1 (en) * 2013-05-17 2014-11-20 Nvidia Corporation Integrated circuit package with an interposer formed from a reusable carrier substrate

Also Published As

Publication number Publication date
TW201742189A (zh) 2017-12-01
SG10201913072VA (en) 2020-03-30
TWI712106B (zh) 2020-12-01
SG11201810104VA (en) 2018-12-28
FR3051971B1 (fr) 2019-12-13
KR20190015707A (ko) 2019-02-14
DE112017002718T5 (de) 2019-02-28
KR102397140B1 (ko) 2022-05-16
US20200328094A1 (en) 2020-10-15
FR3051971A1 (zh) 2017-12-01
WO2017207390A1 (en) 2017-12-07
US11114314B2 (en) 2021-09-07
CN109196627B (zh) 2023-08-08

Similar Documents

Publication Publication Date Title
CN109411443B (zh) 垂直堆叠晶圆及其形成方法
KR101120805B1 (ko) 수직의 웨이퍼 대 웨이퍼 상호접속을 제공하기 위한 금속 충진된 관통 비아 구조
CN105023917B (zh) 晶圆上芯片封装件及其形成方法
JP5670306B2 (ja) 浅いトレンチ分離および基板貫通ビアの集積回路設計への統合
US8816489B2 (en) Integrated circuit structures, semiconductor structures, and semiconductor die
US20050082526A1 (en) Techniques for layer transfer processing
WO2007021639A3 (en) 3d ic method and device
US7700410B2 (en) Chip-in-slot interconnect for 3D chip stacks
US8906803B2 (en) Method of forming through substrate vias (TSVs) and singulating and releasing die having the TSVs from a mechanical support substrate
KR20150022987A (ko) 3-차원 집적에서 tsv(through silicon vias) 스트레스를 감소시키기 위한 컨포멀한 코팅 탄성 쿠션의 이용
US8212346B2 (en) Method and apparatus for reducing semiconductor package tensile stress
US20140054791A1 (en) Through silicon via packaging structures and fabrication method
CN103137566A (zh) 用于形成集成电路的方法
CN107768370B (zh) 在衬底两侧上的集成电路结构及形成方法
CN104051411B (zh) 叠层封装结构
CN109196627A (zh) 包含无任何贯通孔的内插层的半导体结构的制造方法
JP2013537363A (ja) 犠牲材料を使用して半導体構造体中にウェーハ貫通相互接続部を形成する方法、及びかかる方法により形成される半導体構造体
KR20200083398A (ko) 전도성 비아들을 구비하는 인터포저들을 포함하는 반도체 구조물의 제조 방법, 및 이와 관련된 구조물들 및 소자들
JP2001144173A (ja) 半導体装置の製造方法
CN108122838A (zh) 半导体器件制备工艺

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant