TWI712106B - 用於製作包含中介層之半導體結構之方法 - Google Patents

用於製作包含中介層之半導體結構之方法 Download PDF

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TWI712106B
TWI712106B TW106117418A TW106117418A TWI712106B TW I712106 B TWI712106 B TW I712106B TW 106117418 A TW106117418 A TW 106117418A TW 106117418 A TW106117418 A TW 106117418A TW I712106 B TWI712106 B TW I712106B
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temporary support
layer
semiconductor
contact pads
item
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TW106117418A
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TW201742189A (zh
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璧顏 阮
魯多維克 伊卡諾
那地雅 班穆罕默德
克里斯多夫 馬勒維
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法商索泰克公司
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Abstract

本發明涉及一種用於製作一半導體結構之方法，其包括：在選定條件下將氫種及氦種引入一暫時支撐件(1)，以在該暫時支撐件(1)中一預定深度處形成一弱化平面(2)，並定義出一表面層(3)及該暫時支撐件(1)之一剩餘部分(4)；在該暫時支撐件(1)上形成一互連層(5)；將至少一半導體晶片(6)安置在該互連層(5)上；將一加強件(8)組裝在該至少一半導體晶片(6)之背面；及對該暫時支撐件(1)提供熱能以分離該剩餘部分(4)並提供所述半導體結構。

Description

用於製作包含中介層之半導體結構之方法
本發明與一種用於製作包含中介層之半導體結構之方法有關。
中介層(interposers)經常作為被動元件使用，讓半導體晶片或晶粒得以並排堆疊，使其互相連接並與外部環境連結。中介層讓具有不同功能(處理單元、記憶體、輸入/輸出)的晶片或晶粒得以混合，以形成具有高帶寬(high bandwidth)組構及小巧外形尺寸之封裝半導體元件。中介層避免在晶粒等級上集積所有功能元件，並加快了元件開發時間。
美國專利申請案公開第2013/0214423號揭示，一中介層通常以足夠厚的材料層為剛性材料(例如大約200微米或更厚)製成，其相對的兩面上有用於連結至半導體晶片及/或外部連接件的接觸墊。中介層也包含貫穿該中介層的通孔，以電性連接在其相對面上的接觸墊。
形成具有高深寬比(其定義為一通孔的長度除以其截面尺寸)，例如大於寬高比5，的通孔通常很困難。因此，通孔具有通常大於20微米的最小橫截面尺寸。該尺寸限制了可在中介層一給定表面中形成的通孔數目，從而限制了最終組裝半導體元件的集積密度(integration density)。不夠小巧的元件問題很多，因其無法被安置在小尺寸的裝置中(智慧型手機、連網手錶等等)。不夠小巧的元件也限制了效能，因為其所需的較長連接線路可能影響傳播信號的帶寬(bandwidth)及延遲(latency)。
不需貫通孔的中介層製作新方法，例如美國專利申請案公開第2014/0191419號所描述者，越來越受到重視。
舉例而言，美國專利申請案公開第20030219969號揭示一種半導體元件製作方法，該半導體元件是與結構精密的一中介層一起封裝，該中介層使用一矽底材製作。該方法包括以下步驟：在一矽底材上形成一可剝離樹脂層，在可剝離樹脂層上形成配線層，在配線底材上安裝多個半導體晶片，以一密封樹脂密封該些半導體晶片形成半導體元件，透過從密封樹脂側切割該些半導體元件但保留矽底材而獲得個別的半導體元件，以及將每一個別半導體元件從矽底材剝離。
但該製作方法非常難實現。該方法要求精密控制結構中連續界面處的黏著力，這樣當在元件上施加牽引力時，才能在樹脂層處精確地從底材將完整元件移除。同時，在該製作方法的初步階段中，樹脂層必須提供足夠的黏附以將不同層一起保持在矽底材上。
本發明的目標在於形成一半導體元件使其包含至少一半導體晶片或晶粒，以及一中介層，以按路線發送來自該至少一半導體晶片的導電部件的電信號，並將電信號按路線發送至該至少一半導體晶片的導電部件。
為達成前述目標，本發明與一種用於製作一半導體結構之方法有關，其包括： ●在選定植入條件下將氫離子及氦離子植入一暫時支撐件，以在該暫時支撐件的預定深度處形成一弱化平面，並定義出一表面層及該暫時支撐件之一剩餘部分； ●在該暫時支撐件上形成一互連層，該互連層包含多個接觸墊及介於該些接觸墊間之導電路徑； ●將至少一半導體晶片安置在該互連層上以電性耦合該晶片之導電部件與該互連層之接觸墊； ●將一加強件組裝在該至少一半導體晶片之背面；及對該暫時支撐件提供熱能及選擇性機械能，以分離該剩餘部分並獲得所述半導體結構。
對該暫時支撐件提供熱能的步驟，可進一步弱化該弱化平面，且可同時強化該加強件對所述半導體結構其餘部分的黏合力。該步驟有利於該支撐件剩餘部分的分離及透過施加中等力量移除該剩餘部分，而沒有使該加強件從所述半導體結構其餘部分分離的風險。
不論單獨或組合實施，本發明另外的非限制性特徵包括： ●導入氦種的選定條件包括以1至2 10^16 at/cm^3之間的劑量及以40 keV至200 keV之間的植入能量植入氦離子； ●導入氫種的選定條件包括以0.5至1.5 10^16 at/cm^3之間的劑量及以25 keV至200 keV之間的植入能量植入氫離子； ●該互連層在該半導體晶片側具有一第一表面，以及與該第一表面相對之一第二表面，且其中該些接觸墊係同時設置在該第一及第二表面上； ●該方法包括在分離該剩餘部分後去除該表面層，以曝露出該互連層第二表面之至少一些接觸墊； ●該方法包括在該第一表面的接觸墊上形成凸出部件，例如微凸塊(microbumps)或金屬凸點(metal studs)，以利於該半導體晶片之導電部件與該些接觸墊之電性耦合； ●該方法包括在該表面層的上面及/或當中形成多個基本元件； ●該表面層具有小於大約10微米之厚度，較佳者為小於1微米，更佳者為50至600奈米之間； ●分離兩個並置接觸墊的距離為0.2微米至2微米之間； ●所述組裝步驟係在將該至少一半導體晶片安置在該互連層上的步驟之後或之前進行； ●所述組裝步驟更包括底膠填充(underfilling)之步驟，以在該至少一半導體晶片周圍的自由空間中提供一填充材料； ●該方法包括切割該半導體結構之步驟，以提供至少一原料半導體元件，以及封裝該至少一原料半導體元件之步驟，以形成一最終半導體元件； ●該互連層具有200奈米至20微米間之厚度； ●與形成該互連層相關聯之熱預算為在低於250℃下達4小時，或在350℃下少於20分鐘； ●提供熱能之步驟包括施加200℃至450℃間之一溫度，持續10分鐘至2小時之間的一段時間。
為簡化以下說明，在不同實施例中實現相同功能的元件將使用相同元件編號。
圖1描繪可藉由本發明所述方法而製作之一半導體結構10。
該半導體結構10包含由一互連層5構成之一中介層。該互連層5包含接觸墊5a，其優選地被設置在該互連層5的兩個表面上；以及位於該些接觸墊5a間的導電路徑5b。該互連層5可具有200奈米至20微米間之厚度，通常為5至10微米間之厚度。一些接觸墊5a被電性耦合到至少一半導體晶片6的導電部件6a。其他接觸墊5a，尤其是設置在該互連層5之曝露表面上者，可提供該半導體結構10之外部輸入/輸出連結。
如圖1所示，該些接觸墊5a可以很高的密度設置在該互連層5的每一表面上。舉例而言，分離兩個並置接觸墊5a的距離可為0.2至2微米之間。
複數個半導體晶片6被優選地設置並電性耦合至該互連層5。該些晶片6可為不同尺寸，具有不同功能，且以不同技術製作。舉例而言，一晶片6可為14奈米製程製作的CPU，而另一晶片6可為0.25微米製程製作的輸入/輸出晶片。晶片6可為，舉例而言，一DRAM或SRAM記憶體晶片、一CPU、一GPU、一微控制器或一輸入/輸出晶片。
該半導體結構10可選擇性包含額外晶片6設置在互連層5的曝露表面上(圖1未繪出)。
互連層5允許將具有不同功能的不同晶片共同集積，以實現一功能性半導體元件。互連層5的導電路徑5b允許不同晶片6的導電部件6a在電性上連結在一起，以使其在功能上合作。為允許複雜的互連方案，互連層5可包含複數個，例如2到4個，堆疊的互連子層。
為增進晶片6的導電部件6a與互連層5的接觸墊5a之間的電性耦合，這些接觸墊5a及/或導電部件6a可被提供成具有凸出部件7a，7b，例如微凸塊。
圖1的半導體結構10亦包含設置在該些晶片6背面之一加強件8，以為該半導體結構提供剛性支撐。加強件8可以任何適當材料製成，例如矽或環氧樹脂材料。晶片6、加強件8及互連層5三者間的自由空間，可以絕緣填充材料，例如二氧化矽，加以填充，以保護半導體結構10並提高其剛性。
該半導體結構10可選擇性地在與該些晶片6相對的表面上包含一表面層3於整個或部分互連層5上方，如圖2所示。該表面層3可包括多個基本元件11，其被耦合至互連層5的一些接觸墊5a。基本元件11可為該些晶片6提供額外功能。基本元件11可對應於，舉例而言，薄膜電晶體、PN二極體或光子元件。
圖1或圖2的半導體結構10可加以切割而形成原料半導體元件，接著，原料半導體元件可加以封裝而形成最終半導體元件，如本發明所屬技術領域通常所做的那樣。封裝可包括在設置於互連層5曝露表面上的一些接觸墊5a上形成打線(wire bonds)以為這些元件提供外部連結。
本發明係針對一種用於製作如圖1或圖2所示之半導體結構10之方法。
參考圖3，本發明之方法包括將氫種及氦種，例如氫離子及氦離子，導入一暫時支撐件1之步驟，以在該支撐件的預定深度處形成一弱化平面2。所述氫種及氦種可透過植入方式導入。該弱化平面2定義出一表面層3及該暫時支撐件1之一剩餘部分4。
基於成本和可取得性考量，該支撐件可對應於一圓形標準尺寸矽晶圓。舉例而言，該矽晶圓可具有200或300公厘的直徑及300至900 微米間的厚度。但本發明方法的暫時支撐件不限於前述材料、形狀及尺寸。一般而言，該暫時支撐件係被選定成提供價廉、具剛性且可自行支撐的材料。該暫時支撐件1可包覆有一個或多個表面層材料，例如半導體材料、導體材料或絕緣材料。因此，表面層3亦可包含暫時支撐件1的一個或多個表面層。
視下文詳述的植入條件而定，表面層3的厚度可小於大約10微米，或小於1微米。該厚度以50至600奈米之間為佳。在某些情況下，表面層3會完全從最終結構移除，因此其厚度不是特別重要。但較薄的表面層3有利於移除。
表面層的厚度通常比剩餘部分4的厚度少一或二個10倍差距(decade)。因此，剩餘部分4的厚度與暫時支撐件1的厚度非常接近。
弱化平面2被提供成在本發明之半導體結構10製作方法的後續分離步驟中，允許且有利於暫時支撐件(詳言之為暫時支撐件1的剩餘部分4)的移除。
因此，弱化平面2應受到精確控制，以使其在剩餘部分4移除前的步驟中能保持足夠穩定。平面2的弱化特別會受到這些後續步驟的熱預算(thermal budgets)影響。「足夠穩定」係指平面2的弱化，或弱化平面2在分離前任何步驟中的演變，不應發展成表面層3的變形(例如植入表面起泡造成的變形)，也不應引起剩餘部分4的過早分離。
然而，弱化平面2必須足夠弱化，以使在分離步驟中提供合理的能量便可移除剩餘部分4。
依照本發明，平面2的弱化程度，係透過選定氫種及氦種的導入(即植入)條件而受到精確控制。該條件選定應考量暫時支撐件1的材料，因其可能影響平面2的弱化演變，並考量與分離步驟前暫時支撐件所進行處理步驟相關聯的熱預算(廣言之為能量預算)。
舉例而言，氫離子及氦離子的植入，可在下列植入條件下，於一矽暫時支撐件中進行： •   以0.5至1.5 10^16 at/cm^3之間的劑量，並以25 keV，或廣言之為10 keV至200 keV之間，或10 keV至80 keV之間的植入能量，植入氫離子； •   以1至2 10^16 at/cm^3之間的劑量，並以40 keV，或廣言之為10 keV至200 keV之間，或10 keV至80 keV之間的植入能量，植入氦離子。
氫離子及氦離子可依序植入暫時支撐件1，例如先植入氦離子。先植入氫離子亦可。一般而言，氦種及氫種的植入能量被選定在前述建議的範圍內，這樣在沿著暫時支撐件深度繪製的分配剖面圖中，尖峰值便會彼此靠近，亦即小於150奈米。
利用上述植入種源及植入條件，本發明顯示出暫時支撐件可接受相當於在250℃下處理大約4小時的熱預算，而不會有表面變形或引起剩餘部分4分離的情況。「相等熱預算」係指在較短時間內的較高溫度，或者，較長時間內的較低溫度亦可施加於暫時支撐件1。
還要注意的是，此一熱預算施加於暫時支撐件時，不需為植入表面提供加強件。因此，就相同的植入條件及所施加的熱預算而言，氣泡發展的變動過程(dynamics)不同於被提供成具有加強件的植入底材的斷裂變動過程。
本發明之發明人觀察到，本發明可接受的熱預算(即不會引起表面變形及/或過早分離的熱預算)比起可施加於設有單獨由氫種、單獨由氦種或由其他種源所形成的弱化平面的暫時支撐件的熱預算更廣。發明人特別注意到，可以250℃(或更低)進行4小時的處理或以350℃進行20分鐘(或更短)的處理，來應用熱預算，而不會引起表面變形或剩餘部分4過早分離。
在某些情況中，本發明之方法可包括在表面層3當中及/或上面形成基本元件11之步驟。此步驟可在弱化平面2形成之前或之後進行。基本元件11可對應於，舉例而言，薄膜電晶體、PN二極體或光子元件。這些基本元件最好是執行簡單的電性或光導(light guiding)功能，而不需高階效能，因為表面層3的材料品質可能因弱化平面2的形成而變質。
基本元件可透過半導體產業的任何已知技術製作，例如沉積、蝕刻、摻雜物植入或擴散等等。
基本元件11可在弱化平面2形成後製作，但最好在弱化平面2形成前製作，這樣基本元件的製作對於可由暫時支撐件1接收的可接受熱預算便沒有影響。
若基本元件11是在弱化平面2形成後製作，與基本元件11製作相關聯的熱預算應遠低於所述的可接受熱預算，也就是，舉例而言，遠低於大約250℃、4小時，或遠低於大約350℃、20分鐘。
如圖4所示，本發明之方法亦包括在暫時支撐件1上形成互連層5之步驟，該互連層包含多個接觸墊5a及該些接觸墊5a之間一導電路徑5b。
在此製程階段，該互連層5具有與暫時支撐件1接觸之第一表面，以及曝露之第二表面。該些接觸墊5a最      好設置同時在互連層5的兩個表面上。
互連層5可利用諸如金屬化或雙重鑲嵌(dual damascene)等常規技術製作。其可包括介電沉積、依照定義的光阻圖案進行蝕刻、屏障沉積、鋁或銅沉積(例如透過電鍍)及平坦化(例如透過化學機械研磨)的連續步驟。互連層5可由複數個堆疊的互連子層(例如2到4個子層)構成，以提供更複雜的互連方案。所述互連方案被設計成使半導體結構10的晶片在功能上互相耦合並連到外部連接件。
與互連層5製作相關聯的熱預算通常為低於250℃達數小時，視構成互連層5的子層數目而定。在結合分離步驟之前的所有其他熱預算後，熱預算不應超過可接受熱預算，例如以250℃溫度處理4小時。
由於接觸墊5a及導電路徑5b實質上是以沉積技術製作，因此互連層5不需要在一厚的剛性材料中形成通孔。接觸墊5a在第一或第二表面上的密度可以非常高。舉例而言，分離兩個並置接觸墊5a的距離可為0.2微米至2微米之間。每一接觸墊(其表面部分)的尺寸可為相同尺寸，在0.2微米至2微米之間。該尺寸是傳統中介層方法中必需的一般通孔尺寸的至少五倍小。
製作互連層5的步驟亦可包括在其曝露表面的至少一些接觸墊5a上形成凸出部件7a，以增進與晶片6的導電部件6a的耦合。接觸墊5a上面的凸出部件7a可由微凸塊構成。此種微凸塊可經由在接觸墊5a上進行選擇性金屬生長而製作。作為替代，亦可蝕刻接觸墊5a四周的絕緣材料使接觸墊5a凸出於曝露表面，然後融化凸起金屬部分而形成金屬凸點。
若製作凸出部件7a的製程涉及相當的熱預算，那麼在分離步驟前施加於弱化平面2的整體熱預算，不應超過可接受熱預算，例如以250℃溫度處理4小時或以350℃溫度處理20分鐘。
如圖5所示，本發明製作半導體結構10的方法更包括將至少一晶片6安置在互連層5上，並將晶片6的導電部件6a電性耦合至接觸墊5a之步驟。
晶片6可包含凸出部件7b，其類似於前文所述製作在接觸墊5a上的凸出部件7a，例如微凸塊或金屬凸點，以增進其與互連層5的電性連結。晶片6的凸出部件7b可與互連層5的凸出部件7a接觸(如圖5所示)或直接與接觸墊5a接觸。
作為替代，可在晶片的導電部件6a與接觸墊5a之間透過諸如直接「分子」鍵合或黏附鍵合，建立直接接觸。
安置至少一晶片6的步驟，最好包括安置複數個晶片6。這可以透過習知的「取放」技術達成。
此步驟最好在室溫下進行，這樣對分離步驟前的可接受熱預算才不會影響太大。
如前說明，晶片6可被提供成具有不同尺寸、技術及功能。一晶片6可為一DRAM或SRAM記憶體、一CPU、一GPU、一微控制器或一輸入/輸出元件。
被選定的一組晶片，例如一DRAM晶片、一GPU晶片及一I/O晶片，可安置於其在互連層5上的擬定位置處，並藉由互連層5以能夠發揮功能的方式電性耦合在一起。
半導體結構10可包含多個此類晶片群組，這樣在切割及封裝後，便可統一製作多個半導體元件。
待晶片6安置在互連層5上後，互連層5上方、晶片6四周的自由空間，便可以一絕緣填充材料9填滿，以保護及強固組裝件。填充材料可由二氧化矽構成，其以旋塗式玻璃技術塗佈在互連層5上及晶片6四周。若填充材料具有低密度，則有利於其塗佈及底膠填充。
如圖6所示，本發明之方法有利地包括將一加強件8組裝在晶片6背面之步驟。該加強件8係由具有足夠厚度及剛性的材料製成，這樣半導體結構10在暫時支撐件1移除後便可自行支撐。
該加強件8可由諸如一矽晶圓或一塊環氧樹脂材料製成。其尺寸應至少對應於暫時支撐件1的尺寸。
前述組裝可透過黏附鍵合、直接鍵合或其他技術進行。選定的技術最好不要涉及曝露在高於室溫的溫度下，以避免影響弱化平面2及引起暫時支撐件1的剩餘部分4過早分離。
在一替代方式中，可先將晶片6的背面定位並固定在加強件8的預定位置上，然後將晶片6與加強件8的組裝件安置在互連層5上方，並使晶片6的所有導電部件6a與接觸墊5a電性耦合在一起。
不論選擇以何種方式將晶片6安置在互連層5上及組裝加強件8，都能產生圖6所示的組構。
若組裝加強件的製程，或以絕緣材料6底膠填充晶片6四周空間的步驟涉及相當的熱預算，那麼在分離步驟前施加於弱化平面2的整體熱預算，不應超過可接受熱預算，例如以250℃溫度處理4小時。
本發明製作半導體結構10的方法更包括對暫時支撐件1(詳言之為弱化平面2)提供能量之步驟，以分離剩餘部分4並提供半導體結構10。此步驟如圖7所示。
所提供的能量可為熱能，例如大約400℃的回火，廣言之為200℃至450℃之間，持續10分鐘至大約2小時的一段時間。可使剩餘部分4從暫時支撐件1分離的任何其他熱處理亦可採用。除熱處理外(或某些情況下作為熱能的替代方案)，所提供的能量還可為機械能，例如在暫時支撐件1的弱化平面2處插入一切割刃。
不論其形式為何，所施加的能量，加上弱化平面在之前步驟中所接受的能量，會造成暫時支撐件1的剩餘部分4分離，從而獲得圖8所示的半導體結構10。
對暫時支撐件1提供能量之步驟是特別有利的，因為其進一步弱化了弱化平面，並同時強化了加強件對結構其他部分的黏附。因此，該步驟有利於分離暫時支撐件1的剩餘部分4，及透過施加中等力量移除該剩餘部分，而不用冒著使加強件8從半導體結構其餘部分分離的風險。
在一選擇性後續步驟中，表面層3可被完全去除(若前一步驟沒有製作基本元件11)或部分去除(以保留基本元件11)。去除可透過選擇性(selective)乾式或濕式蝕刻進行，例如在暫時支撐件為矽的情況下使用氫氧化鉀(KOH)。
以本發明之方法所獲得的半導體結構10如圖1及圖2所示。
毋庸贅言，本發明並不限於本說明書所述之特定實施例。本發明亦包括落入後附申請專利範圍內的所有替代實施方式或額外步驟。
舉例而言，基本元件11或額外基本元件11亦可在提供能量與分離暫時支撐件1的剩餘部分4的步驟後，製作在表面層3當中。
在可於分離步驟後進行之一選擇性步驟中，可將額外的晶片6安置在互連層5的曝露表面上，並使其電性耦合至接觸墊5a。
如前所述，半導體結構10可經過切割以形成原料半導體元件，接著原料半導體元件可經過封裝而形成最終半導體元件，如習知技術通常所做的那樣。封裝可包括將打線製作在設置於互連層5曝露表面的某些接觸墊5a上，以為這些元件提供外部連結。
1‧‧‧暫時支撐件2‧‧‧弱化平面3‧‧‧表面層4‧‧‧剩餘部分5‧‧‧互連層5a‧‧‧接觸墊5b‧‧‧導電路徑6‧‧‧半導體晶片6a‧‧‧導電部件7a、7b‧‧‧凸出部件8‧‧‧加強件9‧‧‧填充材料10‧‧‧半導體結構11‧‧‧基本元件
當結合所附圖式閱讀下文的詳細說明時，本發明的許多其他特徵及優點將更為彰顯，其中： -     圖1及圖2描繪依照本發明所述方法而製作之半導體結構； -     圖3描繪將氫種及氦種引入一暫時支撐件之步驟； -     圖4描繪形成一互連層之步驟； -     圖5描繪將至少一半導體晶片安置在該互連層上之步驟； -     圖6描繪組裝一加強件之步驟； -     圖7描繪對該暫時支撐件提供能量以分離一剩餘部分之步驟；及 -     圖8描繪該暫時支撐件之剩餘部分移除後之半導體結構。
2‧‧‧弱化平面
4‧‧‧剩餘部分
5‧‧‧互連層
5a‧‧‧接觸墊
6‧‧‧半導體晶片
7a、7b‧‧‧凸出部件
8‧‧‧加強件
9‧‧‧填充材料

Claims (15)

  1. 一種用於製作一半導體結構(10)之方法，該方法包括：‧在選定條件下將氫種及氦種引入一暫時支撐件(1)，以在該暫時支撐件(1)之一預定深度形成一弱化平面(2)，並定義出一表面層(3)及該暫時支撐件(1)之一剩餘部分(4)；‧在該暫時支撐件(1)上形成一互連層(5)，該互連層(5)包含多個接觸墊(5a)及介於該些接觸墊(5a)間之導電路徑(5b)；‧將至少一半導體晶片(6)安置在該互連層(5)上以電性耦合該晶片之導電部件(6a)與該互連層(5)之接觸墊(5a)；‧透過鍵合將至少具有該暫時支撐件之尺寸之一加強件(8)組裝在該至少一半導體晶片(6)之背面；及‧對該暫時支撐件(1)提供熱能及選擇性的機械能，以分離該剩餘部分(4)並獲得所述半導體結構(10)。
  2. 如申請專利範圍第1項之方法，其中所述導入氦種的選定條件包括以1至2 10^16 at/cm^3之間的劑量及以10keV至200keV之間的植入能量植入氦離子。
  3. 如申請專利範圍第1或2項之方法，其中所述導入氫種的選定條件包括以0.5至1.5 10^16 at/cm^3之間的劑量及以10keV至200keV之間的植入能量植入氫離子。
  4. 如申請專利範圍第1項之方法，其中該互連層(5)具有在該半導體晶片(6)側之一第一表面，以及與該第一表面相對之一第二表面，且其中該些接觸墊(5a)同時設置在該第一及第二表面上。
  5. 如申請專利範圍第4項之方法，其更包括在分離該剩餘部分(4)後至少部分地去除該表面層(3)，以曝露出該互連層(5)第二表面之至少一些接觸墊(5a)。
  6. 如申請專利範圍第4或5項之方法，其更包括在該第一表面的接觸墊(5a)上形成凸出部件(7a)，例如微凸塊或金屬凸點，以利於該半導體晶片(6)之導電部件(6a)與該些接觸墊(5a)之電性耦合。
  7. 如申請專利範圍第1項之方法，其更包括在該表面層(3)上面及/或當中形成多個基本元件(11)之步驟。
  8. 如申請專利範圍第1項之方法，其中該表面層(3)具有小於大約10微米之厚度，較佳者為小於1微米，更佳者為50至600奈米之間。
  9. 如申請專利範圍第1項之方法，其中分離兩個並置接觸墊(5a)的距離為0.2微米至2微米之間。
  10. 如申請專利範圍第1項之方法，其中所述組裝步驟係在將該至少一半導體晶片(6)安置在該互連層(5)上的步驟之後進行。
  11. 如申請專利範圍第10項之方法，其中所述組裝步驟更包括底膠填充(underfilling)之步驟，以在該至少一半導體晶片(6)周圍的自由空間中提供一填充材料(9)。
  12. 如申請專利範圍第1項之方法，其更包括切割該半導體結構(10)之步驟，以提供至少一原料半導體元件，以及封裝該至少一原料半導體元件之步驟，以形成一最終半導體元件。
  13. 如申請專利範圍第1項之方法，其中該互連層(5)具有200奈米至20微米間之厚度。
  14. 如申請專利範圍第1項之方法，其中與形成該互連層(5)相關聯之熱預算為低於250℃達4小時，或在350℃下少於20分鐘。
  15. 如申請專利範圍第1項之方法，其中提供熱能之步驟包括施加200℃至450℃間之一溫度，持續10分鐘至2小時之間的一段時間。
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