TWI653368B - 用於保持半導體晶圓的基座、用於在半導體晶圓的正面上沉積磊晶層的方法、以及具有磊晶層的半導體晶圓 - Google Patents
用於保持半導體晶圓的基座、用於在半導體晶圓的正面上沉積磊晶層的方法、以及具有磊晶層的半導體晶圓 Download PDFInfo
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Abstract
本發明關於一種用於在半導體晶圓的正面上沉積磊晶層期間保持半導體晶圓的基座、用於在半導體晶圓正面使用基座沉積磊晶層的方法、以及具有磊晶層的半導體晶圓。該基座包含基座環和基座底,其中在該基座環的下方,在基座底中以旋轉對稱地分佈的方式設置凹槽。
Description
本發明係關於一種在半導體晶圓的正面上沉積磊晶層的過程中用於保持半導體晶圓的基座。本發明還關於一種用於在半導體晶圓的正面上沉積磊晶層的方法以及具有磊晶層的半導體晶圓,在該方法中係使用該基座。
US 2008/0118712 A1描述了一種基座,其包含基座環和基座底。該基座環具有一用於以半導體晶圓背面的邊緣區域放置該半導體晶圓的凸緣,且係放置在基座底上,以在半導體晶圓的正面沉積一層。
US 2007/0227441 A1注意到在由矽組成的磊晶塗覆半導體晶圓的邊緣區域中之磊晶層厚度的週期性波動。原因是磊晶層不同的生長速率。不同的生長速率與半導體晶圓的正面的晶體取向有關。半導體晶圓的正面是指在其上沉積磊晶層的半導體晶圓該側表面。為了使磊晶層的厚度在邊緣區域更均勻,US 2007/0227441 A1建議改變基座的結構使其具有週期性的厚度波動。
出於同樣的目的,US 2013/0263776提出另外在基座中設置孔,此孔對稱地放置於基座上的半導體晶圓半徑之外的基座周圍。
本發明的一個目的是通過改變基座來改善具有沉積的磊晶層的半導體晶圓在邊緣區域的平整度,而不必影響磊晶層的厚度。尤其,本發明說明了一種因為磊晶層的沉積而沒有使得邊緣下降(ERO)更均勻的方式。
這個目的通過一種基座實現,該基座是用於在半導體晶圓的正面上沉積磊晶層期間保持半導體晶圓,該基座包含: 基座環,其具有用於以半導體晶圓背面的邊緣區域放置該半導體晶圓的凸緣;以及 基座底,其中該基座環位於基座底上的中心,其中, 在基座底中具有凹槽,凹槽存在於基座環的下方,並且在基座底上以旋轉對稱地分佈的方式設置,以及均具有大於基座環之徑向寬度的徑向寬度。
本發明還關於一種用於在半導體晶圓的正面上沉積磊晶層的方法,該方法包含: 提供半導體晶圓; 將該半導體晶圓放置在根據本發明之基座的基座環的凸緣上,其中基座底具有多個凹槽,所述多個凹槽對應於半導體晶圓正面的邊緣區域的二個交替部分區域的多個第一部分區域,以及由於正面的晶體取向,磊晶層的生長速度在第一部分區域中比在第二部分區域中低,由此使得第一部分區域位於基座底中之凹槽的上方;以及 在半導體晶圓的正面上沉積磊晶層。
最後,本發明關於一種具有磊晶層的半導體晶圓,其中具有磊晶層之半導體晶圓的邊緣區域的第一部分區域中的磊晶層的厚度比在邊緣區域的第二部分區域中的薄,且在半導體晶圓的背面存在材料沉積,藉此使得具有磊晶層的半導體晶圓在第一部分區域中的總厚度與具有磊晶層的半導體晶圓在第二部分區域的總厚度相匹配。
對於2毫米的邊緣排除,半導體晶圓較佳在邊緣區域中具有最大ESFQR值為不大於12奈米,較佳不大於10奈米的局部平整度。
半導體晶圓或半導體晶圓包含半導體晶圓表面的至少一部分是單晶的,並且較佳由矽、鍺或這些元素的混合物構成。半導體晶圓可以完全由所述材料的一種構成。然而,這也可以是已經塗覆有一層或多層磊晶層的SOI晶圓(絕緣體上矽)、鍵合半導體(bonded semiconductor wafer)晶圓或基材晶圓(substrate wafer)。所述磊晶層較佳由矽、鍺或這些元素的混合物構成,並且如果適合可含有摻雜物。
半導體晶圓可以從根據FZ法(浮區)或根據CZ法結晶的單晶中切片而得。CZ法包括將種晶浸入坩堝中的熔體,並提升該籽晶並在其上從熔體中結晶單晶。
半導體晶圓的直徑為至少200毫米,較佳為至少300毫米。半導體晶圓的正面較佳為<100>取向或<110>取向。
在正面<100>取向的情況下,半導體晶圓的正面的邊緣區域可以分為四個交替的第一及第二部分區域。在四個第一部分區域中,磊晶層的生長速率比在邊緣區域的四個第二部分區域中的生長速率低。第一部分區域的中心均具有相對於半導體晶圓圓周的角度位置θ。如果取向凹口確定為垂直於半導體晶圓的正面<100>取向的<110>方向,並且如果將270°的角度位置θ分配給該方向,則對應于垂直於半導體晶圓正面<100>取向的<100>方向的角度位置,四個第一部分區域的中心的角度位置θ分別為45°、135°、225°和315°。
在正面<110>取向的情況下,半導體晶圓的正面的邊緣區域可以分為二個交替的部分區域。在二個第一部分區域中半導體晶圓正面上的磊晶層的生長速率比在邊緣區域的二個第二部分區域中的生長速率低。如果取向凹口確定為垂直於半導體晶圓的正面<110>取向的<110>方向,並且如果將270°的角度位置θ分配給該方向,則對應于垂直於半導體晶圓前側<110>取向的<100>方向的角度位置,二個第一部分區域的中心的角度位置θ分別為0°和180°。
在半導體晶圓的正面上沉積磊晶層期間,半導體晶圓位於基座環的凸緣上,而基座環位於基座底的上部放置區域。設置半導體晶圓使得半導體晶圓的正面的邊緣區域的第一部分區域位於基座底的凹槽上方,由於正面的晶體取向,在該第一部分區域中的生長速率較低。
本發明的一個特徵包含將基座環放置在基座底的上部放置區域上,隨後將半導體晶圓放置在基座環的凸緣上,使得半導體晶圓以所需的方式設置。本發明的另一個特徵包含將半導體晶圓放置於基座環的凸緣上,隨後將其凸緣上有半導體晶圓的基座環置於基座底的上部放置區域,使得半導體晶圓以所需的方式設置。
該基座底較佳由石墨氈或塗覆有碳化矽的石墨氈或塗覆有碳化矽的石墨、或碳化矽組成,並且基座環較佳由碳化矽或其他一些塗覆碳化矽的材料組成。該其它材料較佳為石墨或矽。基座環具有內徑和外徑。該內徑小於在其正面上要沉積磊晶層的半導體晶圓的直徑,該外徑大於該半導體晶圓的直徑。基座環的徑向寬度對應於基座環的外徑和內徑之差的一半。基座環凸緣從基座環的內邊緣一直延伸到一增加了基座環高度的臺階。凸緣較佳以從該臺階向內落的方式成形。
基座底中的凹槽以旋轉對稱的方式設置。它們各自具有徑向寬度,並且較佳地被銑削(mill)入基座底中。
在每種情況下,凹槽的徑向寬度比基座環的徑向寬度大較佳不小於10 毫米且不大於100 毫米。因此,基座環不完全覆蓋凹槽。由於凹槽,在半導體晶圓正面上沉積磊晶層期間,在半導體晶圓的背面也額外沉積材料。根據本發明,注意確保額外沉積的位置實質上位於半導體晶圓正面的邊緣區域的第一部分區域之下方。雖然磊晶層沉積在半導體晶圓的正面上,該磊晶層被邊緣區域的第一部分區域中磊晶層的厚度比第二部分區域薄的缺陷所困擾,但是,具有沉積的磊晶層的半導體晶圓在邊緣區域中具有特別均勻的總厚度,因為在半導體晶圓背面上有目標地沉積了額外的材料使得所述缺陷不再重要。
在半導體晶圓背面的邊緣區域中額外材料沉積的徑向位置可以目標方式受到影響。這取決於半導體晶圓所覆蓋之凸緣的長度的選擇。該長度越長,材料沉積位置的越向內深入。覆蓋的長度較佳為不小於0.5毫米且不大於3毫米。
基座底中的凹槽各有沿圓周方向的寬度,其大小可以由中心角說明。從基座底中心到凹槽二端的二個半徑形成凹槽的中心角。凹槽的中心位於中心角的角平分線上。
如果目的是要在具有<100>取向的半導體晶圓的正面上沉積磊晶層,則基座底中的四個凹槽的中心角在每種情況下較佳為60°至70°,特別較佳為65°。半導體晶圓較佳置於基座環的凸緣上,以這種方式使得半導體晶圓正面的邊緣區域的四個第一部分區域的中心位於四個凹槽的中心之上。
如果目的是要在具有<110>取向的半導體晶圓的正面上沉積磊晶層,則基座底的二個凹槽的中心角在每種情況下較佳為90°至110°,特別較佳為100°。半導體晶圓較佳置於基座環的凸緣上,以這種方式使得半導體晶圓正面的邊緣區域的二個第一部分區域的中心位於二個凹槽的中心之上。
基座底中的凹槽的深度較佳不小於0.3毫米且不大於1.0毫米。凹槽的深度可以是均勻的。然而,較佳的是,在圓周方向上該深度增加且再減小,並且在該方向上的凹槽的截面具有U形或V形的輪廓。
關於上述根據本發明的方法的實施方案所指定的特徵可以相應地應用於根據本發明的裝置。相反地,根據本發明的裝置的上述實施態樣所指定的特徵可以相應地應用於根據本發明的方法。在圖式說明和申請專利範圍中描述說明了根據本發明的實施態樣的這些和其它特徵。個別的特徵可以單獨地或組合地作為本發明的實施態樣實現。此外,它們可以描述可獨立地保護的有利的實施態樣。
下面參考附圖更詳細地解釋本發明。
根據第1圖的設置包含基座底1和基座環2,基座環2具有內邊緣9,其中凸緣3與內邊緣9相鄰朝向外部。半導體晶圓4可以半導體晶圓的背面的邊緣區域放置於凸緣3上。
根據第4圖,在基座底1中,存在4個凹槽5,其以在基座底1的上部放置區域10上旋轉對稱的方式排列,並且還有用於升高和降低半導體晶圓的升降銷孔7。每個凹槽5都具有內緣8和沿圓周方向對應於中心角α大小的寬度。凹槽的中心位於中心角的角平分線(虛線)上。凹槽的數量對應於半導體晶圓的正面的邊緣區域的四個部分區域的數量,其中由於正面的晶體取向,磊晶層在該等部分區域中的生長速率比在四個部分區域之間的部分區域中的生長速率低。
第2圖示出了具有正面<100>取向的半導體晶圓4的取向特徵。取向缺口6標記270°的角度位置θ。因此,具有較低的磊晶層生長速率的邊緣區域的四個部分區域的中心位於45°、135°、225°和315°的角度位置,其中虛線箭頭的尖端指向這四個角度位置。
第3圖示出了具有正面<110>取向的半導體晶圓4的取向特徵。取向缺口6標記270°的角度位置θ。因此,具有較低的磊晶層生長速率的邊緣區域的二個部分區域的中心位於0°和180°的角度位置,其中虛線箭頭的尖端指向這二個角度位置。
為了在半導體晶圓的正面上沉積磊晶層11,具有正面<100>取向的半導體晶圓4置於基座環2的凸緣3上,以這種方式使得四個第一部分區域位於基座底1中的四個凹槽5上方,較佳使得四個第一部分區域的中心位於四個凹槽的中心之上。
為了在半導體晶圓的正面上沉積磊晶層,具有正面<110>取向的半導體晶圓置於基座環的凸緣上,以這種方式使得二個第一部分區域位於基座底中的二個凹槽上方,較佳使得二個第一部分區域的中心位於兩個凹槽的中心之上。
第6圖示出了通過基座底中的一個凹槽的中心的徑向截面,以及第5圖示出了二個凹槽之間的相應截面。沉積氣體通過較短的箭頭所示的路徑到達半導體晶圓4的正面,在其上沉積磊晶層11。由於凹槽5,對於沉積氣體存在另一路徑,該另一路徑由第6圖中較長的箭頭所示並且穿過基座環2的下方到達半導體晶圓4的背面,使得材料12沉積在半導體晶圓4的背面的邊緣區域中。雙頭箭頭表示凸緣3被半導體晶圓4覆蓋的長度。材料沉積12的徑向位置可以通過選擇覆蓋的長度來進行影響,並隨著覆蓋的長度增加而向內移動。使用具有相對較小徑向寬度的凸緣3的基座環2可產生較短的覆蓋,而使用具有更寬的凸緣3的基座環2可產生較大的覆蓋。
當因為不存在凹槽(第5圖),基座環2直接位於基座底上時,在半導體晶圓4背面不存在材料沉積12。
第7圖示出了根據第4圖的通過凹槽的沿圓周方向的截面。因為沿著較佳65°的中心角α凹槽的深度T上升到0.3毫米至1毫米的最大值,並且再次降低,且較佳係線性上升和降低,所以截面的輪廓為V形。
第8圖示出了通過根據第4圖凹槽的沿圓周方向的截面,其輪廓與第7圖所示的不同。因為沿著較佳65°的中心角α凹槽的深度T上升到0.3毫米至1毫米的最大值,且較佳係線性地上升,保持在最大值一部分並再次降低,較佳係線性降低,所以截面的輪廓是梯形的。對於本發明目的的實現,這種形式的輪廓是特別較佳的。
第9圖示出了通過根據第4圖凹槽的沿圓周方向的截面,其輪廓與第7圖及第8圖所示的不同。因為沿著較佳65°的中心角α凹槽的深度T快速上升到0.3毫米至1毫米的最大值,保持在最大值並再次迅速降低,較佳係突然上升和降低,所以截面的輪廓是U形的。
實施例
由直徑為300毫米且正面<100>取向的單晶矽構成的半導體晶圓在單晶圓反應器中塗覆由矽組成的磊晶層。一部分半導體晶圓(對比晶圓)以位於第1圖所示的基座上的方式被塗覆。該基座底缺少根據本發明之凹槽。另一部分半導體晶圓係根據本發明塗覆,也就是說以位於本發明的基座上的方式。具有較低的磊晶層生長速率的四個部分區域的中心位於基座底中的四個凹槽的中心之上。
之後,確定所塗覆的半導體晶圓在邊緣區域中的局部平整度。第10圖分別示出了該一部分及該另一部分的經塗覆的半導體晶圓的ESFQR值(邊緣排除2毫米,θ = 265o
的鐳射標記,扇面長度30毫米)。在根據本發明塗覆的半導體晶圓的情況下,ESFQR值(實線)沒有表現出特徵性的週期性波動,而在對比晶圓(虛線)的情況下可以看到。
應當將上述示例性實施態樣的描述理解為示例性的。因此,本說明書的內容首先使本領域技藝人士能夠理解本發明及其相關優點,其次在本領域技藝人士的理解中還包括對所述結構和方法的明顯變化及改良。因此,所有這些變化及改良以及等同物均應涵蓋在申請專利範圍的保護範圍內。
1‧‧‧基座底
2‧‧‧基座環
3‧‧‧凸緣
4‧‧‧半導體晶圓
5‧‧‧凹槽
6‧‧‧取向缺口
7‧‧‧升降銷孔
8‧‧‧凹槽的內邊緣
9‧‧‧基座環的內邊緣
10‧‧‧上部放置區域
11‧‧‧磊晶層
12‧‧‧材料沉積
α‧‧‧中心角
T‧‧‧深度
第1圖是先前技術的描述,其顯示了基座底、基座環和半導體晶圓的相對排列。 第2圖及第3圖示出了具有正面(100)晶面取向(第2圖)和具有正面(110)晶面取向(第3圖)的半導體晶圓的取向特徵。 第4圖以平面圖示出了根據本發明的基座底。 第5圖及第6圖顯示了在不同位置處基座底的徑向垂直截面,第5圖是基座底中二個凹槽之間區域的垂直截面,第6圖是基座底中一個凹槽區域的垂直截面。 第7圖、第8圖及第9圖示出了根據第4圖的通過凹槽的沿圓周方向的截面輪廓的較佳形式。 第10圖是表示經磊晶塗覆的測試晶圓在邊緣區域中的平整度的圖。在圖中,ESFQR值相對於角度位置θ作圖。
:無。
Claims (2)
- 一種具有磊晶層之半導體晶圓,其中該具有磊晶層之半導體晶圓的邊緣區域的第一部分區域中的磊晶層厚度比在該邊緣區域的第二部分區域中的薄,以及在該半導體晶圓的背面存在材料沉積,藉此使得該具有磊晶層之半導體晶圓在第一部分區域中的總厚度係與該具有磊晶層之半導體晶圓在第二部分區域中的總厚度相匹配。
- 如請求項1所述的半導體晶圓,其中對於2毫米的邊緣排除,其在邊緣區域中的局部平整度具有不大於12奈米的最大ESFQR值。
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2016
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- 2017-05-31 CN CN201780035494.9A patent/CN109314041B/zh active Active
- 2017-05-31 WO PCT/EP2017/063089 patent/WO2017211630A1/de unknown
- 2017-05-31 JP JP2018564312A patent/JP6880078B2/ja active Active
- 2017-05-31 EP EP17728487.4A patent/EP3469624B1/de active Active
- 2017-05-31 SG SG11201810554QA patent/SG11201810554QA/en unknown
- 2017-06-08 TW TW106119130A patent/TWI653368B/zh active
- 2017-06-08 TW TW107129199A patent/TWI671439B/zh active
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TWI671439B (zh) | 2019-09-11 |
JP2019523991A (ja) | 2019-08-29 |
KR20190008361A (ko) | 2019-01-23 |
KR102200146B1 (ko) | 2021-01-11 |
TW201812122A (zh) | 2018-04-01 |
EP3469624A1 (de) | 2019-04-17 |
CN109314041B (zh) | 2023-07-28 |
DE102016210203B3 (de) | 2017-08-31 |
SG11201810554QA (en) | 2018-12-28 |
JP6880078B2 (ja) | 2021-06-02 |
US10865499B2 (en) | 2020-12-15 |
TW201842244A (zh) | 2018-12-01 |
WO2017211630A1 (de) | 2017-12-14 |
CN109314041A (zh) | 2019-02-05 |
EP3469624B1 (de) | 2022-04-20 |
US20190106809A1 (en) | 2019-04-11 |
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