TWI650840B - 引線支架、半導體裝置及引線支架之製造方法 - Google Patents

引線支架、半導體裝置及引線支架之製造方法 Download PDF

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Publication number
TWI650840B
TWI650840B TW104121787A TW104121787A TWI650840B TW I650840 B TWI650840 B TW I650840B TW 104121787 A TW104121787 A TW 104121787A TW 104121787 A TW104121787 A TW 104121787A TW I650840 B TWI650840 B TW I650840B
Authority
TW
Taiwan
Prior art keywords
inner lead
external connection
lead
connection terminal
die bond
Prior art date
Application number
TW104121787A
Other languages
English (en)
Chinese (zh)
Other versions
TW201603221A (zh
Inventor
林真太郎
Original Assignee
日商新光電氣工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商新光電氣工業股份有限公司 filed Critical 日商新光電氣工業股份有限公司
Publication of TW201603221A publication Critical patent/TW201603221A/zh
Application granted granted Critical
Publication of TWI650840B publication Critical patent/TWI650840B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
TW104121787A 2014-07-09 2015-07-06 引線支架、半導體裝置及引線支架之製造方法 TWI650840B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014141584A JP6357371B2 (ja) 2014-07-09 2014-07-09 リードフレーム、半導体装置及びリードフレームの製造方法
JP??2014-141584 2014-07-09

Publications (2)

Publication Number Publication Date
TW201603221A TW201603221A (zh) 2016-01-16
TWI650840B true TWI650840B (zh) 2019-02-11

Family

ID=55068140

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104121787A TWI650840B (zh) 2014-07-09 2015-07-06 引線支架、半導體裝置及引線支架之製造方法

Country Status (5)

Country Link
US (1) US9633933B2 (enExample)
JP (1) JP6357371B2 (enExample)
KR (1) KR102402841B1 (enExample)
CN (1) CN105261605B (enExample)
TW (1) TWI650840B (enExample)

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JP6840466B2 (ja) * 2016-03-08 2021-03-10 株式会社アムコー・テクノロジー・ジャパン 半導体パッケージ及び半導体パッケージの製造方法
JP6500822B2 (ja) * 2016-03-25 2019-04-17 トヨタ自動車株式会社 セレクタブルワンウェイクラッチ
JP6603169B2 (ja) * 2016-04-22 2019-11-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US9892999B2 (en) 2016-06-07 2018-02-13 Globalfoundries Inc. Producing wafer level packaging using leadframe strip and related device
US10109563B2 (en) * 2017-01-05 2018-10-23 Stmicroelectronics, Inc. Modified leadframe design with adhesive overflow recesses
JP7182374B2 (ja) * 2017-05-15 2022-12-02 新光電気工業株式会社 リードフレーム及びその製造方法
JP2020136324A (ja) * 2019-02-13 2020-08-31 セイコーエプソン株式会社 電子デバイスの製造方法
JP7338204B2 (ja) * 2019-04-01 2023-09-05 富士電機株式会社 半導体装置
WO2022021294A1 (en) 2020-07-31 2022-02-03 The Procter & Gamble Company Wearable article comprising an elastic laminate
WO2022021266A1 (en) 2020-07-31 2022-02-03 The Procter & Gamble Company Wearable article comprising an elastic laminate
WO2022021295A1 (en) 2020-07-31 2022-02-03 The Procter & Gamble Company Wearable article comprising an elastic laminate having good wicking properties
JP7479771B2 (ja) * 2020-10-01 2024-05-09 三菱電機株式会社 半導体装置、半導体装置の製造方法及び電力変換装置

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US6614100B1 (en) * 1996-06-24 2003-09-02 Infineon Technologies Ag Lead frame for the installation of an integrated circuit in an injection-molded package
TW200419765A (en) * 2002-09-17 2004-10-01 Chippac Inc Semiconductor multi-package module having wire bond interconnection between stacked packages
US20090072363A1 (en) * 2007-09-13 2009-03-19 Zigmund Ramirez Camacho Integrated circuit package-in-package system with leads

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DE3911711A1 (de) * 1989-04-10 1990-10-11 Ibm Modul-aufbau mit integriertem halbleiterchip und chiptraeger
JP2568915B2 (ja) * 1989-07-19 1997-01-08 イビデン株式会社 Ｉｃカード
JPH05144992A (ja) * 1991-11-18 1993-06-11 Mitsubishi Electric Corp 半導体装置およびその製造方法ならびにその製造に使用されるリードフレームおよびその製造方法
JPH09260568A (ja) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
KR980006174A (ko) * 1996-06-18 1998-03-30 문정환 버틈 리드 패키지
KR100214544B1 (ko) * 1996-12-28 1999-08-02 구본준 볼 그리드 어레이 반도체 패키지
US6329705B1 (en) * 1998-05-20 2001-12-11 Micron Technology, Inc. Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes
KR100319616B1 (ko) * 1999-04-17 2002-01-05 김영환 리드프레임 및 이를 이용한 버텀리드 반도체패키지
KR100355749B1 (ko) * 1999-11-04 2002-10-19 앰코 테크놀로지 코리아 주식회사 리드 프레임의 구조와 그 제조방법 그리고 이 리드프레임을 적용한 반도체 패키지
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US8395251B2 (en) * 2005-05-12 2013-03-12 Stats Chippac Ltd. Integrated circuit package to package stacking system
JP6092645B2 (ja) * 2013-02-07 2017-03-08 エスアイアイ・セミコンダクタ株式会社 半導体装置
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US6614100B1 (en) * 1996-06-24 2003-09-02 Infineon Technologies Ag Lead frame for the installation of an integrated circuit in an injection-molded package
TW449843B (en) * 1999-07-22 2001-08-11 Seiko Epson Corp Semiconductor apparatus and its manufacturing method, electric circuit board and electronic machine
TW200419765A (en) * 2002-09-17 2004-10-01 Chippac Inc Semiconductor multi-package module having wire bond interconnection between stacked packages
US20090072363A1 (en) * 2007-09-13 2009-03-19 Zigmund Ramirez Camacho Integrated circuit package-in-package system with leads

Also Published As

Publication number Publication date
KR20160006608A (ko) 2016-01-19
JP2016018931A (ja) 2016-02-01
US20160013120A1 (en) 2016-01-14
JP6357371B2 (ja) 2018-07-11
TW201603221A (zh) 2016-01-16
US9633933B2 (en) 2017-04-25
KR102402841B1 (ko) 2022-05-27
CN105261605A (zh) 2016-01-20
CN105261605B (zh) 2019-08-02

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