TWI638454B - 用於射頻整合式被動元件之具有減低射頻損失之高阻値矽基板 - Google Patents
用於射頻整合式被動元件之具有減低射頻損失之高阻値矽基板 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 65
- 230000002829 reductive effect Effects 0.000 title claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 title description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title description 4
- 239000010703 silicon Substances 0.000 title description 4
- 210000000746 body region Anatomy 0.000 claims abstract description 17
- 230000003071 parasitic effect Effects 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 57
- 238000005498 polishing Methods 0.000 claims description 29
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 26
- 238000000227 grinding Methods 0.000 claims description 26
- 239000013078 crystal Substances 0.000 claims description 20
- 229910052732 germanium Inorganic materials 0.000 claims description 20
- 238000012545 processing Methods 0.000 claims description 17
- 238000005422 blasting Methods 0.000 claims description 6
- 230000001680 brushing effect Effects 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 238000004321 preservation Methods 0.000 claims 1
- 230000009467 reduction Effects 0.000 abstract description 5
- 230000002401 inhibitory effect Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 85
- 230000008569 process Effects 0.000 description 24
- 208000024875 Infantile dystonia-parkinsonism Diseases 0.000 description 10
- 208000001543 infantile parkinsonism-dystonia Diseases 0.000 description 10
- 238000002161 passivation Methods 0.000 description 10
- 238000007517 polishing process Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 238000004458 analytical method Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 239000002800 charge carrier Substances 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- 230000007935 neutral effect Effects 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical group O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000011859 microparticle Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000004886 process control Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229940119177 germanium dioxide Drugs 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000013532 laser treatment Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000010421 standard material Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02024—Mirror polishing
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
本申請案有關一種用於射頻整合式被動元件之具有減低射頻損失的高阻值矽基板。該基板包含一主體區含有高阻值主體矽,及一保存的下表面晶格損害區含有破裂的矽在該主體區上方。該晶格損害區係被處理於該基板中,且該保存的晶格損害區係構製成能藉抑制一寄生表面傳導來達到該基板的射頻損失減低。
Description
本申請案概有關於一種用於射頻整合式被動元件(RF-IPD)之具有減低射頻(RF)損失的高阻值矽(HRS)基板。
高阻值矽基板的可用性已為發展和行銷射頻組件,尤其是整合式被動元件(IPDs)提供一甚大的新機會。由於能與已建立的積體電路(IC)製造技術共存之可相容性,及可用性和成本,高阻值矽(HRS)已變成一種幾近理想之用於射頻整合式被動元件(RF-IPDs)的基材。
但是,表面效應持續地呈現問題,會部份地掩蔽以先進的HRS基板可獲得之潛在的低射頻損失標度。即,被囿陷在矽與介電質介面或該介電層本身中的電荷會造成累積或反相層等,其能使寄生表面傳導通道被產生。此等寄生通道會在一射頻場中產生雜散電流。該等雜散電流則會增加傳輸線衰減,減少感應器中可得的Q係數,及減少製造在該等基板上的濾波器之選擇性。
某些方法曾被想出來克服該等表面效應所展現的性能限制。最普遍使用的方法係為一種以中性物質譬如氬、矽、中子或光子的較重植入法(M.Spirito,F.Maria de Paola,L.Nanver,E.Valletta,B.Rong,B.Rejaei,L.C.N.de Vreede,J.J.N.Burghartz,等人之“Surface-Passivated High-Resistivity Silicon as True Microwave Substrate”IEEE Transaction on Microwave Theory and Techniques,Vol.53,No.7,July 2005;及Chan,K.T.,Chin,A.,Chen,Y.B.,Lin,Y.-D,等人之“Integrated antennas on Si,proton-implanted Si and Si-on-quartz”IEDM '01 Technical Digest,IEEE International,2001)及一種沈積非結晶的多晶矽層於該等HRS基板上(B.Rong,J.N.Burghartz,L.K.Nanver,B.Rejaei,及M.van der Zwan,等人之“Surface-Passivated High-Resistivity Silicon Substrates for RFICs”IEEE Electron deviceletters,Vol.25,No.4,April 2004)。一種非結晶/多晶矽沈積亦曾被應用來處理用於SOI製造的晶圓(D.Lederer and J.-P.Raskin,等人之“RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate,”IEEE Transaction on Electron Devices,July 2008)。在所有該等方法中的抑制效果係基於將電荷載體加強地囿陷在該HRS基板之一頂面上的植入或多晶矽層中。
但是,全部的該等方法皆會導致添加成本的結果,且它們在以HRS為基礎的元件製程中會有限制。此等
問題已限制該等方法的可用性。
本發明之一目的係為消除上述的缺點,及要提供一種具有減低射頻訊號損失的高阻值矽基板,並因而使構建在該基板上的射頻整合式被動元件具有較高性能。
本發明之一目的係可藉提供一如請求項1的高阻值矽基板,一如請求項9的方法,及一如請求項10的射頻整合式被動元件來達成。
一用於一射頻整合式被動元件之具有減低射頻損失的高阻值矽基板之一實施例包含一主體區含有高阻值主體矽。該基板更包含一保存的下表面晶格損害區,其係被處理於該基板之一正面中,其會形成前表面並包含破裂的矽在該主體區上方。該晶格損害區係被處理於該基板中,且該保存的晶格損害區係構製成能藉抑制一寄生表面傳導來達成該基板的射頻損失減低。
所謂”表面鈍化”係指例如一被施加於一矽晶圓之一表面的處理,用以在一射頻激發時抑制寄生表面傳導促成的雜散電流產生。
所謂”高阻值矽”係指半導體級的矽晶體,其具有一異常高的電阻率,例如,典型高於100Ω-cm或更多。標準的矽電阻率範圍為由1以下至10至20Ω-cm。
所謂”射頻整合式被動元件”係指被動組件,例如傳導器、感應器、凹槽濾波器、大量聲波(BAW)濾波器、
薄膜大量聲波共振器(FBAR),及其它類型的濾波器等,其已被整合在一適當的平台上,例如在一高阻值矽上。
一種製造用於一射頻整合式被動元件之具有減低射頻損失之高阻值矽基板的方法之一實施例,包含生長一高阻值矽,及處理所生長的矽來由該所生長的矽切片一矽晶圓,並薄化所切片的矽晶圓。該處理會達成一晶格損害區含有破裂的矽於一被處理的矽晶圓中。該方法更包含拋光被處理的矽晶圓來獲得該基板,其包含一主體區含有高阻值的主體矽,並藉該拋光保存該主體區上之晶格損害區的至少一部份,該至少一部份的晶格損害區係構製成能抑制一寄生表面傳導而來達到該基板的射頻損失減低。
一射頻整合式被動元件之一實施例包含該具有減低射頻損失的高阻值矽基板。該矽基板包含一主體區含有高阻值主體矽,及一保存的下表面晶格損壞區,其係被處理於該基板之一正面中,其會形成前表面並包含破裂的矽在該主體區上方。該晶格損害區係被處理於該基板中,且該保存的晶格損害區係構製成能抑制一寄生表面情況來達到該基板的射頻損失減少。
本發明的更多實施例係界定於附屬請求項中。
該動詞”包含”在本文件中係被用作一開放性限制,其既不排除亦不必定要有未示出的特徵存在。該等動詞”包括”及”具有”係被定義為如同包含。
該等詞語”一”、”一個”及”至少一個”若被用於此,乃定義如同一個或一個以上,該”多數”乙詞係定義為
二個或二個以上。
該”另一”乙詞,若被用於此,係定義為至少有一第二個或更多個。
該”或”乙詞一般係以其意義來被使用,包含”及/或”除非該內容有清楚地另作指示。
針對上述界定的動詞和名詞,該等定義應可適用,除非在申請專利範圍或在本說明書中的別處有被給予一不同的定義。
最後,在各附屬請求項中所述的特徵係可互相自由地組合,除非另有明白地表示。
100‧‧‧HRS基板(晶圓)
110‧‧‧主體區
120a‧‧‧最上層
120b‧‧‧晶格損害區
121‧‧‧破裂區
122‧‧‧晶圓正面
123‧‧‧晶圓背面
124‧‧‧過度區
126‧‧‧彈性應變區
130‧‧‧多晶矽層
131‧‧‧前表面
200,300‧‧‧製造方法
202-288,302-388‧‧‧各步驟
490‧‧‧晶圓
本發明的實施例將參照所附圖式來被說明,其中:圖0示出一下表面損害模式;圖1a~1b示出一正面損害的HRS晶圓在一拋光製程之前和之後的狀況;圖1c示出一正面損害的HRS晶圓,其已被以一可擇性的多晶矽層來完成;圖2示出一用以製造一HRS晶圓的方法之一舉例流程圖;圖3示出一用以製造一矽在絕緣體上(SOI)晶圓的方法之一舉例流程圖;及圖4a~4c示出一正面損害晶圓,一中性物質植入晶圓,及一具有一多晶矽層正面損害晶圓等之電荷載體擴散長度
描圖影像。
圖0示出一下表面損害模式(H.F.Hadamovsky,Werkstoffe del Halbleitertechnik;Leipzig:Deutcher verlag für Grundstofftechnik,1990)。
該用以製造一HRS基板(晶圓)100的方法200係用來為圖0中所示的破裂區產生足夠的深度和範圍,俾使一晶圓表面的頂面被以一無損害的化學機械平坦化(CMP)拋光技術來最終化。一最上層會被移除,且一電荷載體囿陷及寄生傳導抑制將會在保留於該最後晶圓100中的破裂區內發生。先前使用的普通方法,該高劑量的植入,典型係被限制於一混亂/破裂的晶體損害程度,以避免該非結晶化劑量及在後續處理中相關的問題。
圖1a~1b和圖2示出該用於RF-IPDs之具有減低RF訊號損失的基板100,及用以製造它的方法200。
在步驟202當開始時,一生長腔室會被啟動,且必需的維修操作,例如有關該腔室情況及所用的反應氣體與一矽饋料的適足性等之檢查操作會被進行。
在步驟204時,一HRS錠塊會在該腔室中生長,且所生長的錠塊會被切割及研磨來處理。
在步驟210時,HRS晶圓會被由該處理的錠塊切片,例如藉多線切片依目前的工業標準為之。該切片製程會機械地將一些下表面晶格損害併入該等切片的晶圓中,
此時該等切片的晶圓包含一晶格損害區含有破裂的矽。嗣,該等切片的晶圓會被清潔,且該等切片晶圓的邊緣會被研磨。
在步驟220時,該等切片晶圓會藉打光來薄化以至少部份地除去該切片所致的結晶體損害。該等經打光的晶圓嗣會被清潔。
因該打光製程亦會機械地將一些下表面晶格損害併入該等切片的晶圓中,故經打光的晶圓包含一晶格損害區,該處是破裂的矽。或者,若該切片所致的晶體損害係要被至少部份地保留在該打光的晶圓中,其乃可以調變該打光製程,而使至少一部份該切片所致的晶格損害區保留,且該等打光的晶圓含有該切片及打光所致的晶體損害。另一種相同最後結果的可能性係全部一起繞過該打光階段。
在步驟230時,該等打光晶圓會被酸蝕刻以至少部份地除去該等晶體損害,然後,經蝕刻的晶圓會被目視檢查,清潔,並以熱施體退火來處理。
在步驟240時,該等經蝕刻的晶圓會被以受控的研磨來薄化,其亦會機械地將一些下表面晶格損害併入該等蝕刻的晶圓中。故,圖1a的經研磨晶圓100只包含該研磨所致的晶體損害,假使該蝕刻製程已除去該等切片及/或打光所致的晶體損害;或者,當該研磨製程係被調變成可保留先前處理的晶體損害時,則會包含該研磨和先前處理的晶體損害。
該研磨製程可被例如以一旋轉磨料研磨來提供。此外,該研磨製程可被以一受控的多步驟研磨來執行,其包含粗磨步驟和細磨步驟等。
在該二步驟的研磨製程中,該粗磨步驟係被用來作一標準的原料移除及一較深的晶格損害產生。此乃後接一細磨階段,其中該晶圓表面122會被平坦化準備拋光。該細磨步驟可在兩天內來被實施。一種方法係只增加最上層120a中的晶格損害,其正常嗣會在拋光步驟260、270時被移除。或者,該細磨損害深度可被增加,而使甚至在拋光步驟270之後會有一比被該粗磨階段所造成的混亂更增加的晶格混亂(損害)之量。該最後拋光260、270係用來進一步改良晶圓表面122的性質以供元件處理(微影術)。針對某些元件製程,該表面準備需求係較不嚴苛,但省略一或更多個表面準備步驟不會改變該實施例。
該研磨會提供所產生的晶格損害之量和強度的可調適性。此得能調整該基板100所要進行的實際元件處理製程之特定需要的鈍化層性質。
在步驟260時,該單面拋光製程會被控制,而使該晶格損害區的一部份120a被移除,且在該主體區110上方之晶格損害區的至少一部份120b會被保存,如圖1b所示。
此保存的晶格損害區120b係在該基板100的正面122。該正面122結構上可為單晶矽,而會形成前表面122。該保存的晶格損壞區120b包含破裂的矽,會藉抑制一寄生表面傳導來達成該正面損害的基板100之RF損失減低。該晶
格損害區120b可包含一破裂區121,一過度區124,及一彈性應變區126等在該主體矽區110上方。
依據本發明之一實施例,一RF-IPD包含該正面損害的基板100具有減低的RF訊號損失。在該RF-IPD中的基板100包含一主體區110含有高阻值主體矽,及一保存的下表面晶格損害區120b含有破裂的矽在該主體區100上方。該晶格損害區120b已被機械地處理於該基板100中,且其係構製成能藉抑制一寄生表面情況來達到該基板100的RF損失減低。
依據本發明之一實施例,該RF-IPD基板100中的保存晶格損害區120b係被處理於該基板100之一正面122中,且其會形成該前表面122。
當該晶格損害區120a、120b被使用濕噴砂、雷射處理或刷損法來拋光而完全地除去時,其亦可能將該晶體損害實施於一正常無損害的前表面122。但是,全部的此等方法皆具有增加成本及導入某些步驟其中污染物會被容易引入該晶圓100的缺點。
在步驟268時,若有需要藉由某種另一製程,例如以刷損法、雷射處理、濕噴砂、或乾噴砂,來將一晶格損害機械地提供於該薄化的晶圓100中,則在步驟270時,該薄化的晶圓100會被刷損,雷射處理,或濕噴砂,以提供該晶體損害。
在步驟272時,該有損害的晶圓100,其包含該主體區110含有主體矽,會被例如以CMP拋光法來拋光。該拋
光製程係特別地導至該損害晶圓100之一正面122,其結構可為單晶矽。
依據本發明之一實施例,該RF-IPD基板100中的拋光正面122結構上係為CMP拋光的單晶矽。
在步驟274時,該拋光製程會被控制,而使一被提供於該主體區110上方之晶格損害區的至少一部份被保存。
在步驟276時,其乃可以提供一多晶矽層130,將其沈積在該拋光的晶圓表面122上-特別是在該正面122上-而來該沈積層130覆蓋該晶格損害區120a、120b頂上。該沈積層130嗣會被拋光。
該添加層130更會加強藉由該晶格損害區120a、120b所達成的鈍化(減低感應損失)。其會增加該鈍化HRS晶圓100的處理成本,但所造成的前表面131將可適合於一般使用於半導體工業的表面檢查方法。
用於此目的之該層130的厚度可為0.2~8.0μm,且最佳的厚度為0.4~6.0μm。同時,該沈積層130將會強化。
在步驟280時,該具有晶格損害區120b的拋光晶圓100等會被以分類、清楚、檢查、及包裝該等拋光晶圓來最後處理。
嗣,在步驟288時,該方法200會結束。
在一典型的HRS生長製程中,各種不同的機械操作步驟210、220、240、250之指導原則係要除去所有在先前的機械步驟210、220、240、250中累積的全部晶體損害,
但它們全可被調變成能將一些晶體損害併入於所完成的晶圓100。
由多線切片所造成的機械損害以及打光損害,具有二主要缺點,其一,由切片步驟210中之塗層鋼線或由打光步驟220中之鐵板等所引致的金屬污染係高度有害於半導體製程,且所有的預防措施皆應被採用以確保此污染不會被附帶於最終的晶圓100上。雖使用鑽石線來切片可提供一些改良,但要達到如此的最佳方法係在該蝕刻步驟230時完全地除去該損害。
此外,該兩種損害皆會被引生於晶圓的二表面122、123上。該晶圓背面123的完整性亦為一元件處理線中的安全傳輸之一重要因素,且並無可僅由該背面123除去該損害的方便方法。又,當來自切片或打光的深損害未被利用時,該較為昂貴的拋光製程能被縮短。
其中該損害會被以旋轉的固定磨料研磨來處理的機械處理通常係使用於許多先進的晶圓製程中,被用在基板晶圓100處理及在經處理的元件晶圓100之背面研磨中。該等基礎晶圓100只需要很少的處理來使其能完全符合該半導體處理的需求。
該損害產生的實施係藉由該研磨步驟240的最佳化來進行,以使足夠的破裂區120b深度和損害強度能被確保,且該拋光步驟260係被限制於一較短步驟,其不會折損所達到的寄生表面電流之抑制。
若所用的表面檢查標準要求包含該多晶矽層
130,則該等晶格損害區120a、120b的包含會加強該鈍化效果,並能在高溫製程中提供改良鈍化耐久性的附加利益。
相對於植入的晶圓,被以該方法200鈍化的晶圓100不包含植入的物質譬如氬,或植入的矽本身間質。不像多晶/非晶矽沈積,該損害的前表面122結構上仍是單晶矽。
該單面拋光的晶圓100係被以單面一步驟或多步驟研磨來製成,且單面拋光係以一CMP拋光機或以一批次或多晶圓拋光機來僅部份地除去研磨損害以保持殘留損害。
該殘留損害的指標為晶格缺陷,其可藉由氧化致生的堆疊損傷,或使用濕式氧化測試法在晶圓100中所見的凹坑及/或脫位,或使用少數載體壽命時間或SPV測試法所得之該晶圓100相較於沒有殘留損害保留的類似晶圓較縮減的少數載體壽命時間等而成為可見的。
或者,該等晶圓100能藉以一雙面拋光機取代該單面拋光而被製成雙面拋光的,因此,當該等晶圓100在一面或兩面上研磨時,該殘留損害能被保留在一面或兩面上。
圖3示出一用以製造一SOI晶圓的方法300,其中該殘留損害係被製成於該SOI晶圓上,其包含一矽基板晶圓及一矽元件層被以一介電層隔離。此介電層可為二氧化矽,氮化矽,或不同介電層之組合的其它介電質。該殘留損害可被留在該元件層上。
在步驟302中當開始時,必要的操作會被進行,
且在步驟304、305時該等基板和元件晶圓會被提供。
在步驟306、307時,其係可能在至少一個該等晶圓上提供氧化層或其它介電層。
在步驟308時,該等晶圓會被互相接合,且在該接合的結構物頂上之元件晶圓會在步驟309時被薄化。
在步驟368時,若該薄化的結構物已包含一充分的晶格損害且其係要被利用,則該損害的結構物會在步驟272時,被例如以受控的CMP拋光來拋光。
或者,在步驟368時,若其需要藉由例如研磨、刷損、雷射處理、或濕噴砂來機械地提供一晶格損害於該薄化的元件晶圓中,則在步驟370時該薄化結構物會被處理而來提供該晶體損害,且嗣在步驟372時被拋光。
在步驟374時,該拋光製程會被控制而使所提供的晶格損害之至少一部份被保存,然後,其係可能沈積一多晶矽層在該晶格損害區頂上,並拋光所沈積的多晶矽層。
在步驟380時,具有該殘留晶格損害的拋光結構物-及可能的該多晶矽層-會被以分類、清潔、檢查、及包裝來最後處理。
嗣,在步驟388時,該方法300會結束。
或者,當該SOI晶圓係被以一可保存該殘留損害的低溫接合製法來製成時,該殘留損害可被製成於該基板晶圓上。且,該等晶圓的其它製造步驟係低得足以保持該殘留損害。用來保持該損害的典型最高溫度係小於1000℃,或較好小於800℃,且最好低於600℃。因在此等溫度
的該SOI製程,限制係極為有限,且在該晶格損害區頂上含有該多晶矽層會改良高溫製程中之鈍化的耐久性。
該殘留損害能被以脈衝雷射掃描通過該表面122來損害該表面,而類似該拋光的晶圓100地製成於該SOI晶圓上。雷射功率會被調整,而使該矽中的損害臨界點被超過,但不會由該表面122削除過多的矽。
該殘留損害能被以磨料微粒濕式或乾式噴砂該晶圓表面122,而類似該拋光的晶圓100地製成於該SOI晶圓上。微粒可為由次微米尺寸至30μm大小的任何硬微粒,較有利的是以尺寸為1~10μm的二氧化矽微粒來損害該表面122,但其他的磨料,如氧化鋁、氧化鋯、或碳化矽亦可被使用。
藉著調修該矽晶圓製程中之材料移除的最終階段,其乃可能結合足以供鈍化的晶格損害,且在用以製造RF IPDs所需之較有限的線寬處,表面品質仍可與IC處理相容,該矽帶隙內的囿陷位置之產生,能藉由許多的機械處理步驟來被達成,例如一晶圓切片,打光、研磨、刷損及濕式噴砂。
於此所示的原理適用於全部該等技術,因在該等變化例之間基本的方法並無不同。所示的方法200係依據旋轉研磨,且研磨參數被選成能有足夠深度均勻的晶格損害。此步驟係後接一高度地受控制的材料移除,目的在保存足夠的晶格損害程度,但包含CMP拋光以確保基板能在供元件處理的微影製程中被圖案化。由於使用植入和多晶
矽沈積技術,故此方法200不能與長熱氧化相容,但因廣泛漸增的大量工業IPD製程係以低溫介電質沈積技術為基礎,故其不應被視為一大缺點。
依據該方法200製成的晶圓100曾被用於RF被動元件的處理。經測試的被動元件包括傳輸線(共平面波導),平面感應器,及濾波結構物等。其成功的結果驗證該最終表面係與使用於製造RF被動元件的製程完全相容,且在基板100中產生的層120b會甚劇地改良該傳輸線衰減和各種感應結構物中的Q係數。此證明該寄生表面情況已如設計地被抑制。
製程控制對確保該等併有內建表面鈍化之已製成的晶圓100等皆為性質相同一致乃是不可或缺的。此係可藉由表面復合速度分析來促成,其係依據復合壽命時間分析。因該測量可針對所達到的RF性能來被校正,故其是高度可重複的並能提供全晶圓描圖,此係甚為適用於該目的。
圖4a示出一正面損害的HRS晶圓100之電荷載體擴散長度描圖影像(平均擴散長度576μm),圖4b為一中性物質植入的晶圓490之描圖影像(平均擴散長度558μm),其依據一復合速度分析具有類似的囿陷效率,及圖4c為一具有一多晶矽層的正面損害HRS晶圓100之描圖影像。
此分析係用來驗證以被製成的鈍化層120b所達到的囿陷效率係類似於以既有的方法所達成者。此製程控制亦可被擴伸至所述之各種用於製造RF被動元件之不同元件製程的鈍化方法之可相容性的驗證。
在所製成的被動元件之RF性能分析中,此一晶圓100已在由20KHz至50或甚至高達80GHz顯示改良的性能,乃取決於所測試的被動組件。
本發明現已參照前述實施例等說明如上,且本發明的一些優點已被驗證。顯然本發明並非僅限於該等實施例,而係包含所有在本發明概念之精神和範疇及以下申請專利範圍內的全部可能實施例。
Claims (9)
- 一種用於射頻整合式被動元件之具有減低射頻損失的高阻值矽基板,其包含:一主體區,其包含高阻值主體矽,及一保存的下表面晶格損害區,其經加工至該基板之一正面側,其中該基板係一矽晶圓,及其中該晶格損害區包含位在該主體區上方之破裂的矽,該基板特徵在於:該晶格損害區形成該晶圓的一前表面,其中該正面係一化學機械平坦化拋光之前表面,其中該晶格損害區係一薄化之晶格損害區,及其中該晶格損害區抑制一寄生表面傳導,俾以達成該基板的射頻損失減低。
- 如請求項1的基板,其中該正面係結構單晶矽。
- 如請求項1或2的基板,其中該保存的晶格損害區係被以切片、打光、研磨、刷損、雷射處理或濕噴砂來機械性地加工。
- 如請求項3的基板,其中該研磨係為一旋轉的固定磨料研磨,及/或該研磨係以一包含一粗磨與一細磨的二步驟研磨來執行。
- 如請求項1或2的基板,係包含位在該保存的晶格損害區 之頂面上的一多晶矽層。
- 如請求項5的基板,其中該多晶矽層之厚度係為0.2~8.0μm。
- 如請求項5的基板,其中該多晶矽層之厚度係為0.4~6.0μm。
- 一種用以製造用於射頻整合式被動元件之如請求項1~7中之任一項的具有減低射頻損失的高阻值矽基板之方法,該方法包含至少下列步驟:生長一高阻值矽;藉由從所生長的矽切片一矽晶圓以及藉由薄化被切片的矽晶圓,來加工該生長的矽,俾以達成於該經加工的矽晶圓中的一含有破裂的矽之晶格損害區;化學機械平坦化拋光該經加工的矽晶圓俾以獲得該基板,該基板包含一含有高阻值主體矽的主體區;及藉由該化學機械平坦化拋光之步驟來保存該主體區上方之該晶格損害區的至少一部份,使得該晶格損害區形成該晶圓的一化學機械平坦化拋光之前表面並且包含位在該主體區上方之破裂的矽。
- 一種射頻整合式被動元件,係包含如請求項1~7中之任一項的具有減低射頻損失的高阻值矽基板。
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KR102606738B1 (ko) * | 2017-02-10 | 2023-11-24 | 글로벌웨이퍼스 씨오., 엘티디. | 반도체 구조들을 평가하기 위한 방법들 |
FR3066858B1 (fr) * | 2017-05-23 | 2019-06-21 | Soitec | Procede pour minimiser une distorsion d'un signal dans un circuit radiofrequence |
CN109103582A (zh) * | 2018-08-29 | 2018-12-28 | 河海大学常州校区 | 薄膜体声波谐振器结构的纳米机械声学天线及制造方法 |
FI129826B (en) * | 2020-10-08 | 2022-09-15 | Okmetic Oy | Manufacturing method of high-resistive silicon wafer intended for hybrid substrate structure |
US20220115226A1 (en) * | 2020-10-08 | 2022-04-14 | Okmetic Oy | Manufacture method of a high-resistivity silicon handle wafer for a hybrid substrate structure |
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FR3126169A1 (fr) * | 2021-08-12 | 2023-02-17 | Stmicroelectronics (Tours) Sas | Procédé de fabrication de composants radiofréquence |
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