TWI613770B - 晶片封裝體 - Google Patents

晶片封裝體 Download PDF

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Publication number
TWI613770B
TWI613770B TW105103010A TW105103010A TWI613770B TW I613770 B TWI613770 B TW I613770B TW 105103010 A TW105103010 A TW 105103010A TW 105103010 A TW105103010 A TW 105103010A TW I613770 B TWI613770 B TW I613770B
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Taiwan
Prior art keywords
semiconductor
dielectric layer
present disclosure
semiconductor wafer
conductive
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TW105103010A
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English (en)
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TW201715660A (zh
Inventor
余振華
陳明發
葉松峯
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台灣積體電路製造股份有限公司
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Publication of TW201715660A publication Critical patent/TW201715660A/zh
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Abstract

本揭露提供一種晶片封裝體，包括：半導體晶片及設於半導體晶片上之半導體晶粒。此晶片封裝體亦包括介電層，此介電層設於半導體晶片上，且包覆半導體晶粒，其中此介電層大抵上由半導體氧化物材料製得。此晶片封裝體更包括導電元件，此導電元件貫穿半導體晶粒之半導體基板，且物理連接半導體晶片之導電墊。

Description

晶片封裝體
本揭露係有關於半導體技術，且特別係有關於晶片封裝體。
半導體裝置應用於各種電子裝置，例如個人電腦、手機、數位相機等各式電子儀器。半導體裝置的形成通常包括在半導體基板上依序沉積絕緣層或介電層、導電層及半導體層材料，並利用微影與蝕刻步驟圖案化各種材料層，以在基板上形成電路及元件。
半導體工業藉由持續縮小元件之最小尺寸來增加各個電子元件(例如電晶體、二極體、電阻、電容等)之整合密度，使一既定的面積內可整合更多的元件。輸入和輸出的連接數量大幅增加。使用較少的面積或較小的高度的較小的封裝結構被發展以封裝半導體裝置。例如，為了更進一步增加電路密度，三維積體電路已被研發。
新的封裝技術被研發以增進半導體裝置之密度及功能。這些相當新穎之半導體裝置之封裝技術面臨挑戰。
本揭露提供一種晶片封裝體，包括：半導體晶片(semiconductor chip)；半導體晶粒(semiconductor die)，設於半導體晶片上；介電層，設於半導體晶片上，且包覆 (encapsulate)半導體晶粒，其中介電層大抵上由半導體氧化物材料製得；及導電元件，貫穿半導體晶粒之半導體基板，且物理連接半導體晶片之導電墊。
本揭露更提供一種晶片封裝體，包括：半導體晶片(semiconductor chip)；半導體晶粒(semiconductor die)，設於半導體晶片上；介電層，包覆(encapsulate)半導體晶粒，其中介電層大抵不包括聚合物材料；導電元件，貫穿半導體晶片之半導體基板；及連接結構，設於半導體基板上，且電性連接導電元件，其中半導體晶片係設於半導體晶粒與連接結構之間。
本揭露又提供一種晶片封裝體，包括：半導體晶片(semiconductor chip)；半導體晶粒(semiconductor die)，接合至半導體晶片，其中半導體晶粒直接接觸半導體晶片；及導電元件，貫穿半導體晶粒之半導體基板，且物理連接半導體晶片之導電墊。
為讓本揭露之特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下。
10‧‧‧基板
20‧‧‧半導體晶粒
20’‧‧‧半導體晶粒
30‧‧‧半導體晶粒
30’‧‧‧半導體晶粒
40‧‧‧半導體晶粒
70‧‧‧基板
70’‧‧‧基板
80‧‧‧基板
80’‧‧‧基板
100‧‧‧半導體基板
100a‧‧‧表面
100b‧‧‧表面
102‧‧‧層間介電層
104‧‧‧導電墊
104’‧‧‧測試墊
126‧‧‧導電元件
200‧‧‧半導體基板
200a‧‧‧表面
200b‧‧‧表面
202‧‧‧層間介電層
204‧‧‧導電墊
204’‧‧‧測試墊
206‧‧‧介電層
208‧‧‧蝕刻停止層
210‧‧‧介電層
212‧‧‧圖案化罩幕層
214‧‧‧開口
216‧‧‧圖案化罩幕層
218‧‧‧開口
220‧‧‧絕緣層
222d‧‧‧絕緣元件
222s‧‧‧絕緣元件
224‧‧‧絕緣元件
226d‧‧‧導電元件
226s‧‧‧導電元件
228‧‧‧接合層
300‧‧‧半導體基板
300a‧‧‧表面
300b‧‧‧表面
302‧‧‧層間介電層
304‧‧‧導電墊
306‧‧‧介電層
308‧‧‧蝕刻停止層
310‧‧‧介電層
322d‧‧‧絕緣元件
322s‧‧‧絕緣元件
326d‧‧‧導電元件
326s‧‧‧導電元件
326’‧‧‧導電元件
328‧‧‧介電層
330‧‧‧重佈層
332‧‧‧鈍化層
397‧‧‧連接結構
399‧‧‧連接結構
400‧‧‧半導體基板
402‧‧‧介電層
404‧‧‧導電墊
406‧‧‧介電層
426s‧‧‧導電元件
600‧‧‧承載基板
600’‧‧‧承載基板
602‧‧‧黏著層
602’‧‧‧黏著層
606‧‧‧介電層
606’‧‧‧介電層
608‧‧‧隔離層
608’‧‧‧隔離層
610‧‧‧介電層
610’‧‧‧介電層
612‧‧‧重佈層
612’‧‧‧重佈層
626s‧‧‧導電元件
626d‧‧‧導電元件
692‧‧‧鈍化層
694‧‧‧導電墊
696‧‧‧鈍化層
698‧‧‧連接結構
700‧‧‧半導體基板
702a‧‧‧介電層
702b‧‧‧鈍化層
702c‧‧‧介電層
702d‧‧‧蝕刻停止層
702e‧‧‧介電層
702e’‧‧‧介電層
703a‧‧‧阻障層
703b‧‧‧阻障層
703c‧‧‧阻障層
704a‧‧‧導電墊
704b‧‧‧導電元件
704c‧‧‧導電元件
704’‧‧‧測試墊
705‧‧‧虛置元件
800‧‧‧半導體基板
802a‧‧‧介電層
802b‧‧‧鈍化層
802c‧‧‧介電層
802d‧‧‧蝕刻停止層
802e‧‧‧介電層
802e’‧‧‧介電層
803a‧‧‧阻障層
803b‧‧‧阻障層
803c‧‧‧阻障層
804a‧‧‧導電墊
804b‧‧‧導電元件
804c‧‧‧導電元件
804’‧‧‧測試墊
805‧‧‧虛置元件
903‧‧‧晶種層
903’‧‧‧晶種層
904‧‧‧罩幕層
1002‧‧‧元件
1004‧‧‧封膠化合物
1006‧‧‧封裝體穿孔
1008‧‧‧半導體晶粒
1010‧‧‧連接結構
1012‧‧‧重佈層
第1A-1O圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
第2A-2B圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
第3圖係本揭露一些實施例之晶片封裝體之剖面圖。
第4A-4I圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
第5A-5F圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
第6A-6E圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
第7圖係本揭露一些實施例之晶片封裝體之剖面圖。
以下的揭露內容提供許多不同的實施例或範例，以實施本案的不同特徵。而本揭露書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化說明。當然，這些特定的範例並非用以限定。例如，若是本揭露書以下的內容敘述了將一第一特徵形成於一第二特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本揭露書中不同範例可能使用重複的參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“較下部”、“上方”、“較上部”及類似的用語等。除了圖式所繪示的方位之外，空間相關用語用以涵蓋使用或操作中的裝置的不同方位。所述裝置也可 被另外定位(例如，旋轉90度或者位於其它方位)，並對應地解讀所使用的空間相關用語的描述。
以下敘述了本揭露書的一些實施例。第1A-1O圖顯示根據一些實施例之於半導體元件之形成製程的多個階段中的剖面圖。額外的步驟可於第1A-1O圖所述之階段之前、之間、及/或之後提供。以下敘述之一些製程階段可於不同的實施例中被置換或排除。額外的元件可加入半導體裝置結構中。以下敘述之一些構件可於不同的實施例中被置換或排除。雖然以下敘述之實施例係以特定順序進行各個步驟，然而這些步驟可依照其它合乎邏輯之順序進行。
如第1A圖所示，提供基板10與預定接合至此基板10之半導體晶粒20。在本揭露一些實施例中，基板10可包括半導體晶圓、半導體晶圓之一部分、介電晶圓之一部分、其它適合之基板、或上述之組合。此半導體晶圓(例如矽晶圓)可包含裝置元件，例如主動元件及/或被動元件。在本揭露其它一些實施例中，此半導體晶圓不包含裝置元件。例如，此半導體晶圓可為空白矽晶圓(blank silicon wafer)。上述介電晶圓可包括玻璃晶圓。在本揭露其它一些實施例中，基板10上接合有一或多個其它半導體晶粒(未繪示)。
在本揭露一些實施例中，基板10包括半導體基板100及形成於半導體基板100上之內連線結構，如第1A圖所示。此內連線結構包括層間介電層102與導電墊104。此層間介電層102包括多個次介電層。而多個導電接觸、導電孔、及導線形成於層間介電層102中。此導線之一些部分形成上述導電墊 104。
在本揭露一些實施例中，層間介電層102包括覆蓋導電墊104之次膜層。此次膜層可作為一接合層以進行後續與半導體晶粒20之接合步驟(例如藉由熔融接合步驟(fusion bonding process))。在這些實施例中，設於導電墊104上之次膜層具有一大抵平坦之上表面。可藉由平坦化步驟來提供具有大抵平坦之上表面之次膜層，此平坦化步驟例如可為化學機械研磨。在本揭露其它一些實施例中，一些或全部之導電墊104並未完全埋設於層間介電層102中，且這些或全部之導電墊104被暴露出來。此導電墊104之上表面可與層間介電層102之上表面大抵共平面。
如第1A圖所示，半導體晶粒20包括半導體基板200及形成於半導體基板200上之內連線結構。此內連線結構包括層間介電層202以及導電墊204。半導體晶粒20之內連線結構可與基板10之內連線結構類似。在本揭露一些實施例中，導電墊204係埋設於層間介電層202中。在本揭露其它一些實施例中，此導電墊204之上表面可與層間介電層202之上表面大抵共平面。
可形成於半導體基板200內的各種裝置元件的範例包括電晶體(例如，金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor，MOSFET)、互補型金屬氧化物半導體(complementary metal-oxide-semiconductor，CMOS)電晶體、雙極性接面電晶體(bipolar junction transistor，BJT)、高壓電晶體、高頻電 晶體、P型通道場效電晶體及/或N型通道場效電晶體(PFETs/NFETs)等)、二極體、其它適合的元件或其組合。可進行各種製程(例如，沉積製程、蝕刻製程、離子佈值製程、光微影製程、退火製程、及/或其它可應用的製程或其組合)，以形成各種裝置元件。此多個裝置元件之間係透過半導體晶粒20之內連線結構互連，以形成積體電路裝置。此積體電路裝置例如可為邏輯裝置、記憶體裝置(例如靜態隨機存取記憶體，SRAM)、射頻裝置、輸入/輸出裝置、系統晶片裝置、上述之組合、或其它任何適合之裝置。
如第1B圖所示，在本揭露一些實施例中，半導體晶粒20接合至基板10上。可藉由多種接合步驟將半導體晶粒20接合至基板10上。在本揭露一些實施例中，半導體晶粒20係藉由熔融接合步驟接合至基板10。此熔融接合步驟可為氧化物對氧化物(oxide-to-oxide)之接合。在本揭露一些實施例中，半導體晶粒20係設於基板10上，使層間介電層102與層間介電層202彼此互相直接接觸。接著，可進行一熱處理步驟以完成層間介電層102與層間介電層202之間的熔融接合。於進行熔融接合步驟時，第1B圖所示之結構可被加熱至約150℃至約300℃。
在本揭露其它一些實施例中，半導體晶粒20可藉由混合接合(hybrid bonding)步驟接合至基板10。此混合接合步驟可為氧化物對氧化物(oxide-to-oxide)之接合及金屬對金屬(metal-to-metal)之接合。在本揭露一些實施例中，半導體晶粒20係設於基板10上，使層間介電層102與層間介電層202彼此互相直接接觸，且一些導電墊104與一些導電墊204彼此互 相直接接觸。接著，可進行一熱處理步驟以完成層間介電層102與層間介電層202之間的混合接合以及導電墊104與導電墊204之間的混合接合。於進行混合接合步驟時，第1B圖所示之結構可被加熱至約300℃至約450℃。
雖然半導體晶粒20之前側(內連線結構形成處)係面對基板10，然而本揭露實施例並不限於此。在本揭露其它一些實施例中，此半導體晶粒20可上下顛倒設置，使此半導體晶粒20之背側面對基板10。易言之，半導體晶粒20之背側係位於前側與基板10之間。在本揭露一些實施例中，基板200接合至層間介電層102。在本揭露一些實施例中，半導體基板200上可形成有介電薄膜(例如氧化膜)以進行與層間介電層102之接合。在本揭露一些實施例中，此介電薄膜可為成長於半導體基板200上之原生氧化膜(native oxide film)。
如第1C圖所示，在本揭露一些實施例中，半導體晶粒20被薄化。在本揭露一些實施例中，一部分之半導體基板200被移除以薄化半導體晶粒20。在本揭露一些實施例中，可藉由平坦化步驟來達成半導體晶粒20之薄化。此平坦化步驟可包括化學機械研磨步驟、研磨步驟(grinding process)、蝕刻步驟、任何其它適合之步驟、或上述之組合。
如第1D圖所示，在本揭露一些實施例中，於基板10上沈積介電層206，以包覆(encapsulate)半導體晶粒20。此介電層206圍繞且覆蓋半導體晶粒20。此介電層206可用以保護半導體晶粒20。在本揭露一些實施例中，介電層206直接接觸半導體晶粒20。在本揭露一些實施例中，介電層206直接接 觸半導體基板200之側邊及背側。第1D圖所示之結構可作為晶片封裝體。或者，第1D圖所示之結構可更進一步整合入其它封裝結構中。
在本揭露一些實施例中，介電層206大抵上由半導體氧化物材料製得。例如，介電層206可大抵上由氧化矽製得。在本揭露一些實施例中，介電層206之主要部分(major portion)大抵上由半導體氧化物材料(例如氧化矽)製得。在本揭露一些實施例中，介電層206可包括氧化矽、氮氧化矽、硼矽玻璃、磷矽玻璃、硼磷矽玻璃、氟矽玻璃、低介電常數材料、任何其它適合之材料、或上述之組合。在本揭露一些實施例中，介電層206為單層。在本揭露其它一些實施例中，介電層206包括多個次膜層。在本揭露一些實施例中，大多數的次膜層係由半導體氧化物材料製得。而一個或一些次膜層係由半導體氮化物材料、半導體氮氧化物材料、或半導體碳化物材料製得，且可作為蝕刻停止層。
在本揭露一些實施例中，介電層206大抵不包括聚合物材料。在本揭露一些實施例中，於介電層206與半導體晶粒20之間不具有封膠化合物(molding compound)或底部填充材料(underfill material)。由於介電層206大抵不包括聚合物材料或封膠化合物材料，介電層206的熱膨脹係數(coefficient of thermal expansion(CTE))、半導體晶粒20的熱膨脹係數及基板10之熱膨脹係數皆類似。因此，可減少或防止因熱膨脹係數不匹配(CTE mismatch)所造成之翹曲(warpage)。因此，晶片封裝體之品質及可靠性可提昇。
在本揭露一些實施例中，介電層206可藉由氣相沉積法沈積。此氣相沉積法可包括化學氣相沉積、原子層沉積、物理氣相沉積、任何其它適合之方法、或上述之組合。在本揭露一些實施例中，可藉由平坦化步驟來提供具有大抵平坦之上表面之介電層206，此平坦化步驟例如可包括化學機械研磨製程、研磨製程、其它可應用製程、或上述之組合。
然而，本揭露實施例並不限於上述實施例。在本揭露其它一些實施例中，介電層206可由封膠化合物製得。
可對本揭露實施例做許多變化及/或調整。在本揭露一些實施例中，一或多個導電元件可形成於晶片封裝體中以提供垂直方向之電連接。
如第1E圖所示，在本揭露一些實施例中，蝕刻停止層208及介電層210沈積於介電層206上。蝕刻停止層208可由氮化矽、氮氧化矽、碳化矽、任何其它適合之材料、或上述之組合製得。介電層210之材料可與介電層206之材料類似或相同。在本揭露一些實施例中，蝕刻停止層208及介電層210可各自獨立地由化學氣相沉積、原子層沉積、物理氣相沉積、任何其它適合之方法、或上述之組合沈積。在本揭露其它一些實施例中，可不形成蝕刻停止層208及/或介電層210。
如第1F圖所示，在本揭露一些實施例中，形成圖案化罩幕層212於介電層210上。此圖案化罩幕層212可為一光阻層，且可藉由光微影蝕刻步驟圖案化。如第1F圖所示，圖案化罩幕層212可包括開口，此開口對應預定要形成導電元件之位置。
如第1G圖所示，在本揭露一些實施例中，移除一部分介電層210以形成開口214露出蝕刻停止層208。介電層210可藉由蝕刻步驟並透過圖案化罩幕層212之開口被部分移除。接著，圖案化罩幕層212被移除。
如第1H圖所示，在本揭露一些實施例中，於介電層210及蝕刻停止層208上形成另一圖案化罩幕層216，且蝕刻停止層208係被開口214露出。此圖案化罩幕層216之材料與形成方法可與圖案化罩幕層212之材料與形成方法類似。此圖案化罩幕層216具有較小的開口，此開口部分露出蝕刻停止層208。接著，移除蝕刻停止層208被露出的部分，如第1H圖所示。
如第1I圖所示，在本揭露一些實施例中，移除一部分之介電層206以及一部分之半導體基板200以形成開口218。其中一些開口218露出半導體晶粒20之內連線結構，例如層間介電層202。此開口218可藉由蝕刻步驟並透過圖案化罩幕層216的開口形成。在本揭露一些實施例中，每一個開口214連接對應之一個開口218。在本揭露一些實施例中，每一個開口214比對應之開口218寬。接著，移除圖案化罩幕層216。
如第1J圖所示，在本揭露一些實施例中，絕緣層220沈積於介電層210上以及開口214及218之側壁及底部上。絕緣層220可由氮氧化矽、氧化矽、氮化矽、碳化矽、任何其它適合之材料、或上述之組合製得。此絕緣層220可藉由化學氣相沉積、物理氣相沉積、旋轉塗佈法、任何其它適合之方法、或上述之組合沈積。
如第1K圖所示，在本揭露一些實施例中，部分移 除絕緣層220以形成絕緣元件222s、222d及224。絕緣元件222s可用以提供半導體基板200與後續形成於開口218中的導電元件之間的電性絕緣。在本揭露一些實施例中，每一個絕緣元件222s具有不均勻的厚度。在本揭露一些實施例中，如第1K圖所示，每一個絕緣元件222s自絕緣元件222s之頂部向基板10逐漸變寬。在本揭露其它一些實施例中，絕緣元件222s的厚度大抵相同。
在本揭露一些實施例中，可藉由蝕刻步驟(例如非等向性蝕刻步驟)部分移除絕緣層220。而絕緣層220於開口218中殘留於半導體基板200之側壁上的部分形成絕緣元件222s。位於未貫穿半導體基板200之開口218之側壁上的絕緣層220之剩餘部分形成絕緣元件222d。位於開口214之側壁上的絕緣層220之剩餘部分形成絕緣元件224。在本揭露一些實施例中，絕緣層220位於開口214之側壁上的一些部分亦於蝕刻步驟中被移除。在本揭露一些實施例中，開口214之側壁上並未形成有絕緣元件。
如第1L圖所示，在本揭露一些實施例中，可藉由一蝕刻步驟更進一步將開口218延伸至基板10。於此蝕刻步驟中，一部分之層間介電層202及一部分之層間介電層102被移除。因此，半導體晶粒20之一些導電墊204與基板10之一些導電墊104被露出。在本揭露一些實施例中，絕緣元件222s之材料與層間介電層202及102之材料不同。因此，於蝕刻步驟後，仍保有絕緣元件222s以覆蓋並保護半導體基板200。
如第1M圖所示，在本揭露一些實施例中，導電元 件226s與226d形成於開口214與218中。如第1M圖所示，其中一個導電元件226s貫穿半導體基板200且電性接觸其中一個導電墊204。在本揭露一些實施例中，其中一個導電元件226s貫穿半導體基板200及半導體晶粒20之內連線結構，且電性接觸其中一個導電墊104。如上所述，絕緣元件222s可用以提供半導體基板200與導電元件226s之間的電性絕緣。在本揭露一些實施例中，其中一個導電元件226s係作為穿孔(through-via)且物理連接基板10(例如為半導體晶片)之其中一個導電墊104。在本揭露一些實施例中，其中一個導電元件226s完全貫穿半導體晶粒20。在本揭露一些實施例中，導電元件226d貫穿介電層210與206且電性接觸其中一個導電墊104，如第1M圖所示。
在本揭露一些實施例中，每一個導電元件226s及226d包括一阻障層及一導電層。此阻障層可由鉭、氮化鉭、鈦、氮化鈦、任何其它適合之材料、或上述之組合製得。此阻障層可為多個子膜層之層疊，例如氮化鉭/鉭或氮化鈦/鈦之層疊。此導電層可由銅、鋁、鎢、金、鉑、任何其它適合之材料、或上述之組合製得。在本揭露一些實施例中，於形成導電層之前，可於阻障層上形成一晶種層。此晶種層可包括銅層。
在本揭露一些實施例中，阻障層係沈積於介電層210、導電墊204及104、及開口214及218之側壁上。此阻障層可藉由化學氣相沉積、物理氣相沉積、任何其它適合之方法、或上述之組合沈積。接著，可藉由例如為物理氣相沉積(例如濺鍍法)、化學氣相沉積、任何其它適合之方法、或上述之組合於阻障層上沈積晶種層。接著，可藉由例如為電鍍法之步驟 於晶種層上沈積導電層。接著，進行一平坦化步驟以移除阻障層、晶種層及導電層位於開口214及218外之部分。此平坦化步驟例如可包括化學機械研磨製程、研磨製程、蝕刻步驟、其它可應用製程、或上述之組合。藉此，阻障層、晶種層及導電層留下之部分形成導電元件226s及226d，如第1M圖所示。
接著，如第1M圖所示，在本揭露一些實施例中，於介電層210及導電元件226s及226d上沈積接合層228。此接合層228係用以進行後續與一或多個其它半導體晶粒接合之步驟。接合層228之材料與形成方法與層間介電層102或202之材料與形成方法類似。在本揭露其它一些實施例中，可不形成接合層228。
接著，在本揭露一些實施例中，藉由與第1A-1C圖所示之步驟類似之方法，將半導體晶粒30透過接合層228接合至半導體晶粒20上，如第1N圖所示。在本揭露一些實施例中，接合層228直接接觸半導體晶粒30之層間介電層302。接合層228與層間介電層302藉由其中一種型式之熔融接合步驟(例如氧化層對氧化層接合)彼此接合。在本揭露其它一些實施例中，並未形成接合層228，而其中一個導電元件226s之頂部與半導體晶粒30之導電墊304直接接觸。在這些實施例中，半導體晶粒30可藉由其中一種型式之混合接合(hybrid bonding)步驟接合至基板20上。此混合接合步驟可包括氧化物對氧化物(oxide-to-oxide)之接合及金屬對金屬(metal-to-metal)之接合。
雖然半導體晶粒30之前側(內連線結構形成處) 係面對基板10及/或半導體晶粒20，然而本揭露實施例並不限於此。在本揭露其它一些實施例中，此半導體晶粒30之背側面對基板10及/或半導體晶粒20。易言之，半導體晶粒30之背側係位於半導體晶粒30之前側與基板10之間。在本揭露一些實施例中，半導體晶粒30之半導體基板300接合至接合層228。在本揭露一些實施例中，半導體基板300上可形成有介電薄膜(例如氧化膜)以進行與接合層228之接合。在本揭露一些實施例中，此介電薄膜可為成長於半導體基板300上之原生氧化膜(native oxide film)。
接著，在本揭露一些實施例中，藉由與第1D圖所示之步驟類似之方法，形成介電層306以包覆半導體晶粒30，如第1N圖所示。介電層306之材料與形成方法與介電層206之材料與形成方法類似。接著，在本揭露一些實施例中，藉由與第1E-1L圖所示之步驟類似之方法，形成蝕刻停止層308及介電層310，且形成貫穿半導體基板300及介電層306之開口。一些開口露出導電墊304，一些開口露出導電元件226s，而一些開口露出導電元件226d。亦可形成絕緣元件322s及322d。
接著，在本揭露一些實施例中，藉由與第1M圖所示之步驟類似之方法，形成導電元件326s及326d，如第1N圖所示。在本揭露一些實施例中，其中一個導電元件326s及其中一個導電元件226s共同形成一個貫穿半導體晶粒30及20之導電元件。在本揭露一些實施例中，此導電元件(包括導電元件226s及326s)電性接觸基板10之其中一個導電墊104。在本揭露一些實施例中，其中一個導電元件326d及其中一個導電元件226d 共同形成一個貫穿介電層306及206之導電元件。在本揭露一些實施例中，此導電元件(包括導電元件226d及326d)電性接觸基板10之其中一個導電墊104。
接著，如第1N圖所示，在本揭露一些實施例中，於介電層310及導電元件326s及326d上沈積介電層328。此介電層328可作為一保護層保護導電元件326s及326d。若有其它半導體晶粒被設計要接合至半導體晶粒30上，此介電層328亦可作為一接合層。此介電層328之材料與形成方法與接合層228之材料與形成方法類似。可藉由重複進行類似之步驟於第1N圖所示之結構上堆疊更多半導體晶粒。
如第1O圖所示，在本揭露一些實施例中，於介電層328上形成重佈層(redistribution layer)330與鈍化層332。此重佈層330可被部分露出以提供連接結構(connector)之著陸區(landing area)。此連接結構例如可為焊材凸塊(solder bump)。在本揭露一些實施例中，此重佈層330可由銅、鋁、鎢、金、鈦、鉑、鈷、任何其它適合之材料、或上述之組合製得。在本揭露一些實施例中，鈍化層332可由氮化矽、聚亞醯胺、任何其它適合之材料、或上述之組合製得。
在本揭露一些實施例中，介電層328被圖案化以露出導電元件，例如導電元件326s及326d。接著，一導電層被沈積並圖案化以形成重佈層330。此導電層可藉由電鍍步驟、物理氣相沉積、化學氣相沉積、化學電鍍(electroless plating process)、任何其它適合之方法、或上述之組合沈積。接著，可於介電層328及重佈層330上沈積並圖案化鈍化層332。可藉 由適合之沈積步驟，例如化學氣相沉積或旋轉塗佈步驟來沈積鈍化層332。
可對本揭露實施例做許多變化及/或調整。例如，在本揭露一些實施例中，可於進行用以堆疊半導體晶粒之接合步驟前，形成貫穿半導體晶粒之導電元件。第2A-2B圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
如第2A圖所示，在本揭露一些實施例中，提供預定接合至基板10之半導體晶粒40。半導體晶粒40包括半導體基板400及內連線結構。此內連線結構包括層間介電層402以及導電墊404。半導體晶粒40亦包括形成於半導體基板400中的一或多個導電元件426s。此導電元件426s可貫穿半導體基板400且電性連接對應之導電墊404。於導電元件426s與半導體基板400之間可形成有絕緣元件或絕緣層(未繪示)。
如第2B圖所示，在本揭露一些實施例中，半導體晶粒40接合至基板10上。雖然半導體晶粒40之背側係面對基板10，然而本揭露實施例並不限於此。在本揭露其它一些實施例中，與第1B圖所示之結構類似，半導體晶粒40之前側係面對基板10。此半導體晶粒40可藉由前述之熔融接合步驟或混合接合步驟接合至基板10上。
接著，如第2B圖所示，在本揭露一些實施例中，形成介電層406以包覆半導體晶粒40。介電層406之材料與形成方法與介電層206之材料與形成方法類似。第2B圖所示之結構可作為晶片封裝體。或者，第2B圖所示之結構可更進一步整合入其它封裝結構中。在本揭露其它一些實施例中，半導體晶粒 40上可堆疊有一或多層半導體晶粒。本揭露之實施例可具有許多變化，在本揭露其它一些實施例中，介電層406係由封膠化合物製得。
可對本揭露實施例做許多變化及/或調整。第3圖係本揭露一些實施例之晶片封裝體之剖面圖。第3圖繪示類似於第1O圖之晶片封裝體。在本揭露一些實施例中，基板10包括貫穿半導體基板100之導電元件126。導電元件126可作為穿孔(through-via)並提供設於半導體基板100之相反側上之元件之間的電性通路(electrical path)。在本揭露一些實施例中，每一個導電元件126電性連接對應之連接結構397，此連接結構397形成於半導體基板100之背側上。在本揭露一些實施例中，絕緣元件(未繪示)形成於半導體基板100與導電元件126之間。如第3圖所示，在本揭露一些實施例中，連接結構399形成於半導體晶粒30上。
在本揭露一些實施例中，如第3圖所示，半導體晶粒20'亦堆疊於基板10上。此半導體晶粒20'係設置於與半導體晶粒20大抵相同之高度層級(height level)。如第3圖所示，在本揭露一些實施例中，可形成貫穿介電層306與206之導電元件326’。在本揭露一些實施例中，於接合半導體晶粒30與形成介電層306後，形成包含導電元件326’之開口。
在本揭露一些實施例中，基板10及/或半導體晶粒20、20’或30包括測試墊，例如測試墊104’及/或204’。測試墊104’及/或204’係用於電性測試。可於接合基板10及/或半導體晶粒20、20’或30前，進行多個測試步驟以確保基板10及/或半 導體晶粒20、20’或30具有良好的品質。因此，晶片封裝體之可靠度及性能皆可提昇。在本揭露一些實施例中，此測試墊104’及/或204’可由鋁、鎢、銅、金、鈦、任何其它適合之材料、或上述之組合製得。然而，應瞭解的是，本揭露實施例並不限於此。在本揭露其它一些實施例中，可不形成測試墊104’及/或204’。
在本揭露一些實施例中，導電元件226s係作為穿孔(through-via)並形成連接至基板10(例如為半導體晶片)之電性連接。在本揭露一些實施例中，一或一些導電元件226s物理連接形成於基板10之層間介電層102中的導電墊104。基板10可為半導體晶片或半導體晶圓。在本揭露一些實施例中，於導電元件226s與半導體晶粒20之半導體基板200之間形成有絕緣元件(未繪示)。在本揭露一些實施例中，此絕緣元件與第1O圖所示之絕緣元件222s類似。
可對本揭露實施例做許多變化及/或調整。例如，一些或全部貫穿半導體晶粒之半導體基板的導電元件，可於半導體晶粒接合至基板或其它半導體晶粒上後才形成。或者，一些或全部貫穿半導體晶粒之半導體基板的導電元件，可於半導體晶粒接合至基板或其它半導體晶粒上前形成。此基板與半導體晶粒之間的接合、或不同半導體晶粒之間的接合可根據需求藉由熔融接合或混合接合達成。
可對本揭露實施例做許多變化及/或調整。第4A-4I圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
如第4A圖所示，在本揭露一些實施例中，一或多個半導體晶粒(例如半導體晶粒20及20’)係設於承載基板600上。半導體晶粒20及20’可透過黏著層602接合至承載基板600上。在本揭露一些實施例中，每一個半導體晶粒20及20’包括測試墊204'。測試墊204'係用於電性測試。可於將半導體晶粒20及20’接合至承載基板600上之前，進行多個測試步驟以確保半導體晶粒20及20’具有良好的品質。在本揭露一些實施例中，承載基板600可包括半導體基板(例如矽晶圓)、介電基板(例如玻璃晶圓)、其它適合之基板、或上述之組合。
如第4B圖所示，在本揭露一些實施例中，於承載基板600上沈積介電層606以包覆半導體晶粒20及20’。此介電層606圍繞且覆蓋半導體晶粒20及20'。此介電層606可用以保護半導體晶粒20及20'。在本揭露一些實施例中，介電層606直接接觸半導體晶粒20及20'。在本揭露一些實施例中，介電層606之材料與形成方法與介電層206之材料與形成方法類似。在本揭露一些實施例中，可藉由平坦化步驟來提供具有大抵平坦之表面之介電層606。
如第4C圖所示，在本揭露一些實施例中，第4B圖所示之結構接合至基板10上。第4B圖所示之結構可藉由晶圓對晶圓接合(wafer-to-wafer bonding)來接合至基板10上。在本揭露一些實施例中，介電層606可藉由熔融接合步驟與基板10之層間介電層102接合。在本揭露一些實施例中，一部分之介電層606係夾設於半導體晶粒20或20’與基板10之間。此基板10可為半導體晶圓或半導體晶片。
在本揭露其它一些實施例中，半導體晶粒20或20’之部分導電墊204或測試墊204'並未被介電層606覆蓋。基板10之部分導電墊104或測試墊104'可與半導體晶粒20或20’之部分導電墊204或測試墊204'直接接觸。在這些實施例中，第4B圖所示之結構可藉由混合接合(hybrid bonding)來接合至基板10上。此混合接合步驟可包括氧化物對氧化物(oxide-to-oxide)之接合及金屬對金屬(metal-to-metal)之接合。
在本揭露一些實施例中，基板10為晶圓且包括測試墊104'。此測試墊104’係用於電性測試。可於接合步驟前，進行多個測試步驟以確保基板10具有良好的品質。
如第4D圖所示，在本揭露一些實施例中，移除承載基板600及黏著層602。在本揭露一些實施例中，承載基板600及黏著層602係同時被移除。在本揭露其它一些實施例中，承載基板600自黏著層602被移除，接著，黏著層602自半導體晶粒20或20’被移除。
如第4E圖所示，在本揭露一些實施例中，進行平坦化步驟以薄化介電層606。於此平坦化步驟後，介電層606之表面與半導體晶粒20或20’之表面大抵共平面。在本揭露一些實施例中，半導體晶粒20或20’亦於平坦化步驟中被薄化。此平坦化步驟可包括化學機械研磨步驟、研磨步驟(grinding process)、蝕刻步驟、任何其它適合之步驟、或上述之組合。
接著，如第4E圖所示，在本揭露一些實施例中，於介電層606與半導體晶粒20或20’上沈積隔離層(isolation layer)608。此隔離層608可用以將後續形成之多個導電元件彼 此電性隔離。在本揭露一些實施例中，隔離層608可由氧化矽、氮氧化矽、氮化矽、碳化矽、任何其它適合之材料、或上述之組合製得。在本揭露一些實施例中，隔離層608可藉由化學氣相沉積、旋轉塗佈法、物理氣相沉積、任何其它適合之方法、或上述之組合沈積。
如第4F圖所示，在本揭露一些實施例中，類似於第1M圖或第2圖所示之實施例，形成導電元件226s與226d。類似於第1M圖所示之實施例，隔離元件(未繪示)可形成於導電元件226s與半導體晶粒20或20’之半導體基板200之間。此隔離元件可用以提供導電元件226s與半導體晶粒20或20’之半導體基板200之間的電性絕緣。
如第4G圖所示，在本揭露一些實施例中，於隔離層608與導電元件226s與226d上形成重佈層612與介電層610。形成重佈層612與介電層610之步驟可包括多個沈積及圖案化步驟。
如第4H圖所示，在本揭露一些實施例中，與第4A圖所示之實施例類似，一或多個半導體晶粒，例如半導體晶粒30及30’，可使用一黏著層602’接合至承載基板600’上。接著，在本揭露一些實施例中，與第4B圖所示之實施例類似，形成介電層606’以包覆半導體晶粒30及30’。接著，如第4H圖所示，在本揭露一些實施例中，與第4C圖所示之實施例類似，介電層606’與第4G圖所示之結構藉由混合接合彼此接合。
如第4I圖所示，在本揭露一些實施例中，與第4F-4G圖所示之實施例類似，形成導電元件626s與626d、隔離 層608’、重佈層612’與介電層610’。接著，如第4I圖所示，在本揭露一些實施例中，形成鈍化層692與696、導電墊694與連接結構698。
在本揭露一些實施例中，介電層606與606’大抵不包括聚合物材料。在本揭露一些實施例中，於介電層606與半導體晶粒20與20’之間、或介電層606’與半導體晶粒30與30’之間於不具有封膠化合物(molding compound)或底部填充材料(underfill material)。由於介電層606與606’大抵不包括聚合物材料或封膠化合物材料，介電層606與606’的熱膨脹係數(coefficient of thermal expansion(CTE))、半導體晶粒20、20’、30及30’的熱膨脹係數及基板10之熱膨脹係數皆類似。因此，可減少或防止因熱膨脹係數不匹配(CTE mismatch)所造成之翹曲(warpage)。因此，晶片封裝體之品質及可靠性可提昇。
可對本揭露實施例做許多變化及/或調整。在本揭露一些實施例中，可形成虛置導電墊以提升半導體晶粒或基板之平坦度。藉由平坦度的提升，可改善堆疊多個半導體晶粒之接合步驟。第5A-5F圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
如第5A圖所示，提供半導體基板700。在本揭露一些實施例中，此半導體基板700為半導體晶圓。此半導體晶圓包括形成於其中之裝置元件。內連線結構係形成於半導體基板700上。此內連線結構包括介電層702a與導電墊704a。在本揭露一些實施例中，導電墊704a為內連線結構之頂金屬線(top metal line)之一部分，且被稱為頂部金屬(top metal)。在本揭露一些實施例中，此內連線結構包括多個介電層、多個導線與多個導孔(conductive via)。
在本揭露一些實施例中，此導電墊704a與介電層702a之材料與形成方法可分別與導電墊104與層間介電層102之材料與形成方法類似。在本揭露一些實施例中，可於導電墊704a與介電層702a之間形成阻障層703a。
在本揭露一些實施例中，如第5A圖所示，於介電層702a與導電墊704a上形成鈍化層702b。此鈍化層702b具有一開口露出其中一個導電墊704a。在本揭露一些實施例中，鈍化層702b可由氮化矽、氧化矽、氮氧化矽、任何其它適合之材料、或上述之組合製得。在本揭露一些實施例中，於暴露出之導電墊704a上形成導電元件，例如測試墊704’。測試墊704’係用於電性測試。在本揭露一些實施例中，測試墊704’為鋁測試墊。可進行多個測試步驟以確保形成於半導體晶粒700中的裝置元件具有良好的品質。
接著，如第5B圖所示，在本揭露一些實施例中，於鈍化層702b與測試墊704’上沈積介電層702c。在本揭露一些實施例中，介電層702c之材料與形成方法與層間介電層102之材料與形成方法類似。在本揭露一些實施例中，可藉由平坦化步驟來提供具有大抵平坦之表面之介電層702c。此平坦化步驟可包括化學機械研磨步驟、研磨步驟、蝕刻步驟、任何其它適合之步驟、或上述之組合。
如第5C圖所示，在本揭露一些實施例中，於介電 層702c中形成導電元件704b。導電元件704b可作為一導孔並電性連接至其中一個導電墊704a。在本揭露一些實施例中，可於導電元件704b與介電層702c之間形成阻障層703b。可藉由一或多個光微影及蝕刻步驟形成開口，此開口貫穿介電層702c與鈍化層702b，且露出其中一個導電墊704a。接著，可藉由多個沈積步驟於此開口之底部與側壁上沈積多個膜層。此多個膜層可包括阻障層、晶種層及導電層。接著，可進行平坦化步驟以移除此多個膜層位於此開口外之部分。因此，此多個膜層剩餘之部分形成阻障層703b與導電元件704b。
如第5D圖所示，在本揭露一些實施例中，於介電層702c與導電元件704b上沈積蝕刻停止層702d與介電層702e。在本揭露一些實施例中，此蝕刻停止層702d與介電層702e之材料與形成方法可分別與蝕刻停止層208與介電層210之材料與形成方法類似。
如第5E圖所示，在本揭露一些實施例中，於介電層702e中形成導電元件704c與虛置元件(例如虛置導電墊)705。在本揭露一些實施例中，阻障層703c係形成於導電元件704c與介電層702e之間及/或虛置元件705與介電層702e之間。在本揭露一些實施例中，可藉由光微影步驟及蝕刻步驟於介電層702e與蝕刻停止層702d中形成多個開口，且其中一個開口露出導電元件704b。
接著，可藉由多個沈積步驟於此開口之底部與側壁上沈積多個膜層。此多個膜層可包括阻障層、晶種層及導電層。接著，可進行平坦化步驟以移除此多個膜層位於此開口外 之部分。因此，此多個膜層之剩餘部分形成阻障層703c、導電元件704c與虛置元件705。在本揭露一些實施例中，此平坦化步驟可包括化學機械研磨步驟、研磨步驟、任何其它適合之步驟、或上述之組合。因此，如第5E圖所示，形成類似於基板10之基板70。此基板70可為半導體晶圓或半導體晶片。
此導電元件704c及阻障層703c可作為用以與另一基板接合之接合墊，此另一基板例如可為另一半導體晶粒。類似地，虛置元件705及阻障層703c可作為另一接合墊。然而，本揭露實施例並不限於此。在其它一些實施例中，並未形成阻障層703c。在這些實施例中，導電元件704c及虛置元件705係作為接合墊。
在本揭露一些實施例中，如第5F圖所示，導電元件704b係設於由導電元件704c與阻障層703c組成之接合墊之下。在本揭露一些實施例中，導電元件704b物理連接此接合墊。在本揭露一些實施例中，另一導電元件(例如測試墊704’)係設於由虛置元件705與阻障層703c組成之接合墊之下，如第5F圖所示。在本揭露一些實施例中，導電元件(例如測試墊704’)係與接合墊隔離。例如，導電元件(例如測試墊704’)係藉由介電層702c與虛置元件705隔離。
由於虛置元件705之存在，於平坦化步驟後，虛置元件705之表面、介電層702e之表面及導電元件704c之表面大抵共平面，此有利於後續之接合步驟。在本揭露一些實施例中，可於介電層702e內形成多個虛置元件。在本揭露一些實施例中，這些虛置元件包括虛置元件705及其它導電元件。上述 其它導電元件包括均勻分佈於半導體基板700上之導電元件704c，以有利於平坦化步驟之進行。
在本揭露一些實施例中，並未形成虛置元件705。在這些實施例中，由於並未有用以平衡研磨力道之虛置元件，介電層702e的一些部分會於用以形成導電元件704c之平坦化步驟之後凹陷。因此，此會對後續之接合步驟產生不好的影響。
接著，如第5F圖所示，在本揭露一些實施例中，基板80接合至基板70上。在本揭露一些實施例中，基板80為半導體晶圓。在本揭露其它一些實施例中，基板80為半導體晶粒。基板80包括半導體基板800及內連線結構。
與基板70之內連線結構類似，基板80之內連線結構可包括介電層802a、802c及802e、鈍化層802b、蝕刻停止層802d、導電墊804a、導電元件804b及804c、阻障層803a、803b及803c、與虛置元件805。導電元件804c與阻障層803c可作為接合墊。虛置元件805與阻障層803c可作為另一接合墊。在本揭露一些實施例中，可藉由分別形成於基板80與基板70上之接合墊將基板80接合至基板70上。類似地，由於虛置元件805之存在，於平坦化步驟後，虛置元件805之表面、介電層802e之表面及導電元件804c之表面大抵共平面。因此，可改善用以接合基板70與80之接合步驟。
如第5F圖所示，在本揭露一些實施例中，類似於第1D圖所示之實施例，沈積介電層206以包覆基板80並形成晶片封裝體。在本揭露一些實施例中，可進行類似於第1E-1O圖所示之步驟以形成包括更多半導體晶粒之晶片封裝體。在本揭 露一些實施例中，虛置元件705並未電性連接置任何貫穿介電層206之導電元件。
在第5A-5F圖所示之實施例中，接合墊係用以接合基板70及80。在本揭露一些實施例中，接合墊係用於第1A-1O圖或第3圖所示之實施例中，且係用以幫助接合步驟進行。在本揭露一些實施例中，類似於導電元件226s及226d之穿孔(through-via)形成於基板80中以形成與基板70之電性連接。其中一個穿孔可貫穿介電層206且物理連接基板70(例如半導體晶片)之其中一個導電墊704a。其中一個穿孔可貫穿基板80(例如半導體晶粒)之半導體基板800且物理連接基板70(例如半導體晶片)之其中一個導電墊704a。
可對本揭露實施例做許多變化及/或調整。例如，在本揭露一些其它實施例中，介電層206可由封膠化合物製得。
可對本揭露實施例做許多變化及/或調整。例如，虛置元件之形成方法並不限於第5A-5F圖所示之實施例。第6A-6E圖係本揭露一些實施例之晶片封裝體在其製造方法中各階段的剖面圖。
如第6A圖所示，在本揭露一些實施例中，於第5C圖所示之結構上沈積晶種層903。在本揭露一些實施例中，於沈積晶種層903之前，可於第5C圖所示之結構上沈積阻障層(未繪示)。
如第6B圖所示，在本揭露一些實施例中，於晶種層903上形成罩幕層904。此罩幕層904具有一開口露出晶種層903。此開口定義導電元件704c與虛置元件705形成之位置。在 本揭露一些實施例中，罩幕層904係由光阻材料製得。可藉由光微影步驟形成上述開口。接著，可藉由電鍍步驟或其它可實施之步驟於晶種層903被露出之部分沈積導電材料。藉此，可形成導電元件704c與虛置元件705。在本揭露一些實施例中，導電材料並未完全填滿上述開口。
如第6C圖所示，在本揭露一些實施例中，移除罩幕層904，且部分移除晶種層903。在本揭露一些實施例中，導電元件704c與虛置元件705可作為一罩幕，可進行一蝕刻步驟以部分移除晶種層903。在本揭露一些實施例中，位於導電元件704c與虛置元件705下之部分晶種層903被移除，如第6C圖所示。
如第6D圖所示，在本揭露一些實施例中，於介電層702c上沈積介電層702e’以圍繞導電元件704c與虛置元件705。在本揭露一些實施例中，進行一平坦化步驟以使介電層702e’之表面、導電元件704c之表面、虛置元件705之表面大抵共平面。由於虛置元件705之存在，於平坦化步驟後，虛置元件705之表面、介電層702e’之表面及導電元件704c之表面大抵共平面，此有利於後續之接合步驟。在本揭露一些實施例中，可於介電層702e’內形成多個虛置元件。在本揭露一些實施例中，這些虛置元件包括虛置元件705及其它導電元件。上述其它導電元件包括均勻分佈於半導體基板700上之導電元件704c，以有利於平坦化步驟之進行。
如第6E圖所示，在本揭露一些實施例中，類似於第5F圖所示之實施例，基板80’接合置基板70’上，如第6E圖所 示。在本揭露一些實施例中，基板80’為半導體晶圓。在本揭露其它一些實施例中，基板80’為半導體晶粒。在本揭露一些實施例中，類似基板80，基板80’包括半導體基板800及內連線結構。類似於基板70’或基板80之內連線結構，基板80’之內連線結構可包括介電層802a、802c及802e’、鈍化層802b、蝕刻停止層802d、導電墊804a、導電元件804b及804c、阻障層803a、803b及803c、晶種層903’、與虛置元件805。類似地，由於虛置元件805之存在，虛置元件805之表面、介電層802e’之表面及導電元件804c之表面大抵共平面。因此，可改善用以接合基板70’與80’之接合步驟。
如第6E圖所示，在本揭露一些實施例中，類似於第1D圖所示之實施例，沈積介電層206以包覆基板80’並形成晶片封裝體。在本揭露一些實施例中，可進行類似於第1E-1O圖所示之步驟以形成包括更多半導體晶粒之晶片封裝體。
上述虛置元件(或虛置導電墊)可用於本揭露多個實施例中。在本揭露一些實施例中，此虛置元件係形成於第1D、1M、1N、1O、2B、3、4F或4I圖所示之實施例。
可對本揭露實施例做許多變化及/或調整。如前文所述，本揭露實施例之晶片封裝體可更進一步整合入其它封裝結構中。在本揭露一些實施例中，第1D、1M、1N、1O、2B、3、4F、4I、5F或6E圖之實施例所示之晶片封裝體可更進一步封裝於整合型扇出型封裝結構中(integrated fan-out(InFO)package structure)。
第7圖係本揭露一些實施例之晶片封裝體之剖面 圖。在本揭露一些實施例中，封裝結構包括封膠化合物層1004，此封膠化合物層1004部分或完全包覆元件1002。在本揭露一些實施例中，元件1002包括半導體晶粒。在本揭露一些實施例中，元件1002為晶片封裝體。此晶片封裝體包括第1D、1M、1N、1O、2B、3、4F、4I、5F或6E圖所示之實施例。
在本揭露一些實施例中，此封裝結構包括一或多個封裝體穿孔(through package via)1006，此封裝體穿孔1006貫穿封膠化合物1004。在本揭露一些實施例中，一或多個半導體晶粒1008係設於重佈層1012上，此重佈層1012係形成於封膠化合物1004與元件1002上，如第7圖所示。在本揭露一些實施例中，連接結構1010係形成於封膠化合物1004與元件1002之另一側上。在本揭露一些實施例中，此封裝體穿孔1006形成半導體晶粒1008與連接結構1010之間的電性連接。在本揭露一些實施例中，一些重佈層1012形成半導體晶粒1008與元件1002中的半導體晶粒之間的電性連接。
可對本揭露實施例做許多變化及/或調整。在本揭露一些實施例中，上述扇出型封裝結構或第1D、1M、1N、1O、2B、3、4F、4I、5F或6E圖所示之晶片封裝體可更進一步封裝入晶片上層疊晶圓上層疊基材(chip-on-wafer-on-substrate，CoWoS)封裝結構中。
本揭露實施例於基板上堆疊一或多個半導體晶粒。此外，亦形成貫穿半導體晶粒或介電層之導電元件以提供垂直方向上之電性連接。晶片封裝體之尺寸可更進一步縮小。此半導體晶粒係藉被大抵上由半導體氧化物材料製得之介電 層包覆。因此，介電層的熱膨脹係數、半導體晶粒的熱膨脹係數及基板之熱膨脹係數皆類似。因此，可減少或防止因熱膨脹係數不匹配所造成之翹曲。因此，晶片封裝體之品質及可靠性可提昇。
根據本揭露一些實施例，提供一晶片封裝體，此晶片封裝體包括一半導體晶片及設於半導體晶片上之半導體晶粒。此晶片封裝體亦包括設於半導體晶片上且包覆半導體晶粒之介電層。此介電層大抵上由半導體氧化物材料製得。此晶片封裝體更包括貫穿半導體晶粒之半導體基板且物理連接半導體晶片之導電墊的導電元件。
根據本揭露一些實施例，提供一晶片封裝體，此晶片封裝體包括一半導體晶片及設於此半導體晶片上之半導體晶粒。此晶片封裝體亦包括包覆半導體晶粒之介電層，且此介電層大抵不包括聚合物材料。此晶片封裝體更包括貫穿半導體晶片之半導體基板之導電元件以及設於半導體基板上且電性連接導電元件之連接結構。上述半導體晶片係設於半導體晶粒與連接結構之間。
根據本揭露一些實施例，提供一晶片封裝體，此晶片封裝體包括一半導體晶片及接合至半導體晶片之半導體晶粒。此半導體晶粒直接接觸半導體晶片。此晶片封裝體亦包括貫穿半導體晶粒之半導體基板且物理連接半導體晶片之導電墊之導電元件。
雖然本揭露的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離 本揭露之精神和範圍內，當可作更動、替代與潤飾。此外，本揭露之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本揭露揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本揭露使用。因此，本揭露之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本揭露之保護範圍也包括各個申請專利範圍及實施例的組合。
10‧‧‧基板
20‧‧‧半導體晶粒
30‧‧‧半導體晶粒
100‧‧‧半導體基板
100a‧‧‧表面
100b‧‧‧表面
102‧‧‧層間介電層
104‧‧‧導電墊
200‧‧‧半導體基板
200a‧‧‧表面
200b‧‧‧表面
202‧‧‧層間介電層
204‧‧‧導電墊
206‧‧‧介電層
208‧‧‧蝕刻停止層
210‧‧‧介電層
222d‧‧‧絕緣元件
222s‧‧‧絕緣元件
224‧‧‧絕緣元件
226d‧‧‧導電元件
226s‧‧‧導電元件
228‧‧‧接合層
300‧‧‧半導體基板
300a‧‧‧表面
300b‧‧‧表面
302‧‧‧層間介電層
304‧‧‧導電墊
306‧‧‧介電層
308‧‧‧蝕刻停止層
310‧‧‧介電層
322d‧‧‧絕緣元件
322s‧‧‧絕緣元件
326d‧‧‧導電元件
326s‧‧‧導電元件
328‧‧‧介電層
330‧‧‧重佈層
332‧‧‧鈍化層

Claims (15)

  1. 一種晶片封裝體，包括：一半導體晶片；一半導體晶粒，設於該半導體晶片上；一介電層，設於該半導體晶片上，且包覆該半導體晶粒，其中該介電層由一半導體氧化物材料組成；及一導電元件，貫穿該半導體晶粒之一半導體基板，且物理連接該半導體晶片之一導電墊。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該介電層直接接觸該半導體晶粒。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該導電元件貫穿該半導體晶粒之一內連線結構，以電性接觸該半導體晶片之該導電墊。
  4. 如申請專利範圍第1項所述之晶片封裝體，更包括：一第二導電元件，貫穿該介電層，且電性接觸該半導體晶片之一第二導電墊。
  5. 如申請專利範圍第1項所述之晶片封裝體，更包括：一接合墊，設於該半導體晶片和該半導體晶粒之間；及一第二導電元件，設於該接合墊下，且物理連接該接合墊，其中該第二導電元件係設於該接合墊與該半導體晶片之間，且電性連接該半導體晶片之一第二導電墊。
  6. 如申請專利範圍第5項所述之晶片封裝體，更包括：一第二接合墊，設於該半導體晶片和該半導體晶粒之間；及一第三導電元件，設於該第二接合墊下，且與該第二接合墊 隔離，其中該第三導電元件係設於該接合墊與該半導體晶片之間，且電性連接該半導體晶片之一第三導電墊。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該接合墊之上表面與該第二接合墊之上表面大抵共平面。
  8. 如申請專利範圍第1項所述之晶片封裝體，其中一部分之該介電層係夾設於該半導體晶粒與該半導體晶片之間。
  9. 一種晶片封裝體，包括：一半導體晶片；一半導體晶粒，設於該半導體晶片上；一介電層，包覆該半導體晶粒，其中該介電層大抵不包括聚合物材料；一導電元件，貫穿該半導體晶片之一半導體基板；及一連接結構，設於該半導體基板上，且電性連接該導電元件，其中該半導體晶片係設於該半導體晶粒與該連接結構之間。
  10. 如申請專利範圍第9項所述之晶片封裝體，其中於該介電層與該半導體晶粒之間不具有封膠化合物。
  11. 如申請專利範圍第9項所述之晶片封裝體，更包括：一接合墊，設於該半導體晶片和該半導體晶粒之間；一第二導電元件，設於該接合墊下，且物理連接該接合墊，其中該第二導電元件係設於該接合墊與該半導體晶片之間，且電性連接該半導體晶片之一第二導電墊；一第二接合墊，設於該半導體晶片和該半導體晶粒之間；及一第三導電元件，設於該第二接合墊下，且與該第二接合墊 隔離，其中該第三導電元件係設於該接合墊與該半導體晶片之間，且電性連接該半導體晶片之一第三導電墊。
  12. 一種晶片封裝體，包括：一半導體晶片；一半導體晶粒，接合至該半導體晶片，其中該半導體晶粒直接接觸該半導體晶片；一介電層，設於該半導體晶片上，且包覆該半導體晶粒，其中該介電層大抵不包括聚合物材料；及一導電元件，貫穿該半導體晶粒之一半導體基板，且物理連接該半導體晶片之一導電墊。
  13. 如申請專利範圍第12項所述之晶片封裝體，其中該介電層係由一半導體氧化物材料製得。
  14. 如申請專利範圍第12項所述之晶片封裝體，其中該半導體晶片之一第一內連線結構直接接觸該半導體晶粒之一第二內連線結構。
  15. 如申請專利範圍第12項所述之晶片封裝體，更包括：一第二導電元件，貫穿該半導體晶片之一半導體基板；及一連接結構，設於該半導體基板上，且電性連接該第二導電元件，其中該半導體晶片係設於該半導體晶粒與該連接結構之間。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI809506B (zh) * 2021-04-12 2023-07-21 南亞科技股份有限公司 具有測試墊的半導體元件及其製備方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9754918B2 (en) 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US9666520B2 (en) * 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US10163859B2 (en) 2015-10-21 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method for chip package
US10074611B1 (en) * 2017-03-08 2018-09-11 Semiconductor Components Industries, Llc Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die
US10672729B2 (en) 2017-03-30 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of forming package structure
US20190006305A1 (en) * 2017-06-29 2019-01-03 Powertech Technology Inc. Semiconductor package structure and manufacturing method thereof
US10951347B2 (en) * 2017-07-12 2021-03-16 Qualcomm Incorporated User equipment capability discovery in distributed wireless networks
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
KR102428328B1 (ko) * 2017-07-26 2022-08-03 삼성전자주식회사 반도체 장치
US10290611B2 (en) * 2017-07-27 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
US10535636B2 (en) * 2017-11-15 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrating passive devices in package structures
US10937743B2 (en) * 2018-04-30 2021-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Mixing organic materials into hybrid packages
US11031344B2 (en) * 2018-08-28 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Package having redistribution layer structure with protective layer and method of fabricating the same
CN109148415B (zh) * 2018-08-28 2020-08-25 武汉新芯集成电路制造有限公司 多晶圆堆叠结构及其形成方法
US10867879B2 (en) 2018-09-28 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
DE102018130035B4 (de) 2018-09-28 2020-09-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package und verfahren
KR20200047930A (ko) * 2018-10-26 2020-05-08 삼성전자주식회사 테스트 패드를 포함하는 반도체 패키지
KR102583127B1 (ko) 2018-10-30 2023-09-26 삼성전자주식회사 다이스택 구조물과 이를 구비하는 반도체 패키지
WO2020098623A1 (en) * 2018-11-12 2020-05-22 Changxin Memory Technologies, Inc. Semiconductor device, pad structure and fabrication method thereof
US10861808B2 (en) 2018-11-21 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure of dies with dangling bonds
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US10923421B2 (en) * 2019-04-23 2021-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
KR102622412B1 (ko) * 2019-07-05 2024-01-09 삼성전자주식회사 관통 홀을 포함하는 반도체 패키지 및 이의 제조 방법
KR20210041363A (ko) 2019-10-07 2021-04-15 삼성전자주식회사 다이 대 웨이퍼 접합 구조 및 이를 이용한 반도체 패키지
US11605620B2 (en) * 2020-06-19 2023-03-14 Qualcomm Incorporated Three-dimensional (3D) integrated circuit with passive elements formed by hybrid bonding
KR102393225B1 (ko) * 2020-11-16 2022-05-02 성균관대학교산학협력단 제어 회로 웨이퍼와 결합된 일체형 수발광 소자 및 제조 방법

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201327740A (zh) * 2011-11-14 2013-07-01 Micron Technology Inc 具有增強型熱能管理之半導體晶粒總成，包含該半導體晶粒總成之半導體裝置及其相關方法
TW201338126A (zh) * 2012-03-09 2013-09-16 Ind Tech Res Inst 晶片堆疊結構及其製作方法
TW201539696A (zh) * 2014-02-13 2015-10-16 Taiwan Semiconductor Mfg Co Ltd 半導體裝置及半導體裝置製造方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100394808B1 (ko) 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
TWI233188B (en) * 2003-10-07 2005-05-21 United Microelectronics Corp Quad flat no-lead package structure and manufacturing method thereof
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US9293418B2 (en) * 2007-07-03 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Backside through vias in a bonded structure
US7973310B2 (en) * 2008-07-11 2011-07-05 Chipmos Technologies Inc. Semiconductor package structure and method for manufacturing the same
US8900921B2 (en) 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV
CN101950745A (zh) 2009-07-10 2011-01-19 南茂科技股份有限公司 半导体封装结构及其制造方法
US8803332B2 (en) * 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
US9219023B2 (en) 2010-01-19 2015-12-22 Globalfoundries Inc. 3D chip stack having encapsulated chip-in-chip
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8786066B2 (en) 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
KR101697573B1 (ko) 2010-11-29 2017-01-19 삼성전자 주식회사 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지
KR101719636B1 (ko) 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US20120217610A1 (en) * 2011-02-28 2012-08-30 Hopper Peter J Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections
KR101539635B1 (ko) * 2012-02-15 2015-07-27 어플라이드 머티어리얼스, 인코포레이티드 캡슐화 필름을 증착하기 위한 방법
US8877603B2 (en) * 2012-03-30 2014-11-04 International Business Machines Corporation Semiconductor-on-oxide structure and method of forming
KR20150003814A (ko) * 2012-04-17 2015-01-09 키사, 아이엔씨. 인터칩 통신을 위한 유전체 렌즈 구조들
US9190346B2 (en) * 2012-08-31 2015-11-17 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US20150187701A1 (en) 2013-03-12 2015-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Devices and Methods of Manufacture Thereof
US9250403B2 (en) * 2013-04-26 2016-02-02 Oracle International Corporation Hybrid-integrated photonic chip package with an interposer
US9299640B2 (en) 2013-07-16 2016-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Front-to-back bonding with through-substrate via (TSV)
KR20150058778A (ko) * 2013-11-21 2015-05-29 삼성전자주식회사 반도체 장치 및 그 제조 방법, 상기 반도체 장치를 포함하는 반도체 패키지 및 그 제조 방법
US9331021B2 (en) * 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9666520B2 (en) * 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US9754918B2 (en) * 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US10163859B2 (en) 2015-10-21 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method for chip package
KR102428328B1 (ko) 2017-07-26 2022-08-03 삼성전자주식회사 반도체 장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201327740A (zh) * 2011-11-14 2013-07-01 Micron Technology Inc 具有增強型熱能管理之半導體晶粒總成，包含該半導體晶粒總成之半導體裝置及其相關方法
TW201338126A (zh) * 2012-03-09 2013-09-16 Ind Tech Res Inst 晶片堆疊結構及其製作方法
TW201539696A (zh) * 2014-02-13 2015-10-16 Taiwan Semiconductor Mfg Co Ltd 半導體裝置及半導體裝置製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI809506B (zh) * 2021-04-12 2023-07-21 南亞科技股份有限公司 具有測試墊的半導體元件及其製備方法

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