TWI590332B - 異質退火方法及裝置 - Google Patents

異質退火方法及裝置 Download PDF

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TWI590332B
TWI590332B TW102131402A TW102131402A TWI590332B TW I590332 B TWI590332 B TW I590332B TW 102131402 A TW102131402 A TW 102131402A TW 102131402 A TW102131402 A TW 102131402A TW I590332 B TWI590332 B TW I590332B
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保羅Ｍ 恩奎斯特
蓋厄斯 吉歐曼 二世 方坦
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增普拓尼克斯公司
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Description

異質退火方法及裝置 相關申請案的交叉參考
本申請案係關於美國專利第6,902,987號；第6,932,835號；第7,041,178號；第7,335,996號；第7,387,944號；第7,485,968號；第7,602,070號；第7,807,548號；第7,842,540號；第7,871,898號及第8,053,329號及申請案第12/270,585號；第12/913,385號；第12/954,740號及第13/341,273號，該等專利案之全部內容以引用方式併入本文中。
本發明係關於三維積體電路之領域且更特定而言係關於使用直接晶圓接合之三維積體電路之裝置及其製造。
半導體積體電路(IC)通常製造在一矽晶圓之表面內或製造在一矽晶圓之表面上，從而導致一IC面積必定隨IC之尺寸增加而增加。對於減小IC中之電晶體尺寸方面之持續改良(通常稱為莫爾(Moore)定律)已使得一給定IC面積中之電晶體數目能夠大幅增加。然而，儘管電晶體密度增加，但歸因於所需電晶體數量之較大增加或介於電晶體之間之所需橫向互連之數目增加，許多應用需要增加總IC面積以達成一特定功能。在一單一、大面積IC晶粒中實現此等應用通常導致晶片良率減小且相應地導致IC成本增加。
IC製造之另一趨勢為增加一單一IC(更通常地稱為一系統單晶片 (SoC))內之不同類型電路之數目。此製造通常需要增加遮罩層級之數目以製造不同類型之電路。遮罩層級之增加通常亦導致晶片良率減小且相應地導致IC成本增加。避免此等非所要之良率降低及成本增加之一解決方案為垂直堆疊且垂直互連IC。此等IC可具有不同尺寸，來自不同尺寸之晶圓，包括不同功能(即，類比、數位、光學)，由不同材料(即，矽、GaAs、InP等等)製成。可在堆疊之前對IC進行測試以容許組合已知優良晶粒(Known Good Die；KGD)而改良良率。此垂直堆疊及垂直互連(或三維3D SoC)方式在經濟上的成功取決於堆疊及互連之良率及成本相比於與增加的IC或SoC面積相關聯之良率及成本係有利的。用於實現此方式之一可製造方法係使用直接接合而垂直堆疊個別製造之IC，其中直接接合表面製備使用習知晶圓製造技術，例如，金屬沈積、介電質沈積、化學機械拋光、晶圓減薄、微影遮罩及通孔蝕刻。將直接接合用於3D SoC製造之一進一步優點係由於直接接合程序而能夠達成堆疊之不同層或層級之間之垂直互連之一可調整密度。
直接接合需要一無法由通常IC晶圓製造產生之實質上平坦表面。因此，達成一充分晶圓平坦化可為一直接接合程序中之一重大成本要素。因此，期望具有包括一結構之一裝置及需要一最小成本來達成此所需之表面平坦性之製造該結構之一方法。
金屬直接接合包含用於形成3D結構之方法及裝置，其中可跨一接合介面製造電隔離電互連，可藉由將兩個元件之兩個表面對準且使其等直接接觸來形成該接合介面。各表面可具有絕緣部分及導電部分，且對準之導電部分可導致跨接合介面之一3D電互連，且對準之絕緣部分可使3D電互連與其他3D電互連隔離。
跨接合介面製造3D電互連之細節取決於絕緣部分與導電部分之相對平坦性。例如，若導電部分高於絕緣部分，則可藉由簡單地使兩 個表面接觸來製造一3D互連，例如，若導電部分上沒有防止一3D互連之原生氧化物且導電部分在絕緣部分上方之延伸足夠小使得絕緣部分亦可利用表面順應性而以直接接觸形式接合。亦可不藉由簡單地使兩個表面接觸來製造3D互連，例如若導電部分低於絕緣部分，使得當表面被放置在一起時導電部分不接觸。在此實例中，可使用歸因於導電部分與絕緣部分之間之熱膨脹係數(CTE)差異之溫度之一微小升高及絕緣組件之間之一充分接合能量來製造3D互連，該充分接合能量在元件具有標準厚度之情況下在加熱期間壓縮導電組件。若元件之CTE係相當的，則用於造成一連接之溫度之微小增加可與處於接觸中之絕緣部分之接合能量及元件之剛性相適應。若元件之CTE係不相當的，例如對於一些異質材料組合而言，則在用於製造3D互連之加熱期間，處於接觸中之絕緣部分之高接合能量可導致元件之一者或兩者斷裂。可藉由在加熱之前充分減薄元件之一者來避免此斷裂。此減薄藉由減小元件之剛性而增加元件之順應性使得其可適應元件之CTE差異。減薄以適應此CTE差異可導致元件之剛性減小使得壓縮不足以製造一3D互連。
本發明係關於一壓縮裝置及方法，該壓縮裝置及方法將在加熱兩個元件時促進在該等兩個元件之間形成直接接合3D互連，其中充分減薄一或兩個元件以折中跨越兩個元件之間之一接合介面而製造一3D互連所需之經減薄元件或多個經減薄元件之剛性。
在該方法及裝置之一實例中，含有具有不同CTE之半導體材料之兩個異質晶圓具有經適當製備以用於金屬直接接合之表面，其中表面之導電金屬部分或多個導電金屬部分低於絕緣部分或多個絕緣部分。對準該等晶圓且使該等晶圓接觸且絕緣部分以高接合能量形成一直接接合。接著，減薄一第一晶圓，但該減薄將經減薄晶圓之剛性減小至 低於可靠地形成3D互連所需之剛性。接著，將具有與第二晶圓相當之一CTE之一第三晶圓直接接合至第一晶圓之經減薄側從而增加經減薄晶圓之剛性，且加熱經接合結構從而容許形成3D互連。
在該方法及裝置之第二實例中，含有具有不同CTE之半導體材料之兩個異質晶圓具有經適當製備以用於金屬直接接合之表面，其中表面之導電金屬部分或多個導電金屬部分低於絕緣部分或多個絕緣部分。對準該等晶圓且使該等晶圓接觸且絕緣部分以高接合能量形成一直接接合。接著，減薄一第一晶圓，但該減薄將經減薄晶圓之剛性減小至低於可靠地形成3D互連所需之剛性。接著，將具有與第二晶圓相當之一CTE之一第三晶圓夾持至第一晶圓之經減薄側從而增加經減薄晶圓之剛性，且加熱經接合結構，從而容許以加熱形成3D互連。
1‧‧‧晶圓
2‧‧‧晶圓
3‧‧‧主要部分/晶圓
4‧‧‧直接金屬接合部分
5‧‧‧直接金屬接合部分/部分
6‧‧‧主要部分
7‧‧‧介面
8‧‧‧經減薄層/較厚層/較薄層/層/經減薄之主要部分/經減薄部分
9‧‧‧第三晶圓/晶圓
10‧‧‧部分
11‧‧‧晶圓
12‧‧‧晶圓
13‧‧‧通孔
14‧‧‧通孔
15‧‧‧夾具/晶圓
16‧‧‧卡盤/密封包封體
17‧‧‧高壓腔室
18‧‧‧金屬墊
19‧‧‧氧化物或氮化物材料
當藉由參考結合附圖考慮之以下詳細描述更好地理解本發明時，將容易獲得本發明之一更完整瞭解及其許多伴隨優點，其中：圖1係具有一主要部分及一直接金屬接合部分之兩個晶圓之一圖式。
圖2係具有一主要部分及經對準且放置在一起從而形成一接合介面之一直接金屬接合部分之兩個晶圓之一圖式。
圖3係具有一主要部分及經對準且放置在一起從而形成一接合介面之一直接金屬接合部分之兩個晶圓之一圖式，其中該兩個晶圓之一者之主要部分之一實質部分被移除從而導致一直接金屬接合對之一經減薄部分。
圖4係附接至一直接金屬接合對之經減薄部分之一加固晶圓之一圖式。
圖5係移除一加固晶圓之後一直接金屬接合對之一經減薄部分之一圖式。
圖6係包含經填充通孔之一第二實施例之一圖式。
圖7係各自具有經填充通孔之兩個經接合晶圓之一圖式。
圖8係展示通孔被曝露之圖7中之結構之一圖式。
圖9展示將一額外基板附接至圖8之結構。
圖10A至圖10C係金屬接合區域之詳細視圖。
圖11係以一夾具接合之一晶圓之一圖式。
圖12係以一夾具接合之一晶圓之另一圖式。
圖13係使用一撓性容器進行接合之一圖式。
圖14係將壓力施加至圖13中之撓性容器之一圖式。
圖15係使用一撓性容器進行接合之一圖式。
圖16係將壓力施加至圖15中之撓性容器之一圖式。
現參考圖式(特定而言圖1)，將描述根據本發明之方法之一第一實施例。此處應注意，圖式未按比例繪製而是經繪製以繪示本發明之概念。
兩個晶圓1及2經製備以用於接合。該等晶圓由不同材料製成且具有不同CTE。晶圓2包含一主要部分6及一直接金屬接合部分5。直接金屬接合部分5具有具絕緣部分及金屬部分之一表面。絕緣部分較佳係氧化物或氮化物，且更佳係氧化矽或氮化矽。在圖10A至圖10C中更詳細展示部分5。取決於程序條件及所要組態，金屬墊20可低於氧化物或氮化物材料21、與氧化物或氮化物材料21齊平或可高於氧化物或氮化物材料21。在於表面上使用化學機械拋光之情形中，金屬墊可為碟型且具有低於氧化物或氮化物材料之表面的一表面，或該氧化物或氮化物材料可為碟型且具有低於金屬墊之表面的一表面。
主要部分6可包含基板、裝置及互連部分，例如在工業標準製造之半導體晶圓(諸如，通常用銅或鋁後段程序製造之CMOS晶圓)中見 到的。晶圓1包含一主要部分3及一直接金屬接合部分4。主要部分3可包含基板、裝置及接觸部分，例如在生長於具有形成至異質磊晶材料之接觸件的藍寶石(GaN/藍寶石)上之工業標準氮化鎵系之異質磊晶裝置結構中見到的。
如申請案第09/505,283號、第10/359,608號及第11/201,321號中所描述將晶圓1及晶圓2直接金屬接合，如圖2中所展示。若金屬部分之表面低於絕緣部分之表面，則在第一次使晶圓接觸之後僅絕緣部分可在介面7處直接接觸。接著，可將經接合晶圓加熱以增加經接合絕緣部分之間之接合能量，但並非在使CTE誘發之應變使絕緣部分之間之接合破裂或使經接合晶圓破裂之一過高溫度下加熱。用於增加接合能量之最佳溫度將取決於經接合之晶圓之CET差異及厚度。例如，當將具有約500微米至1000微米藍寶石厚度範圍之一GaN/藍寶石結構接合至具有約500微米至750微米之厚度範圍之矽CMOS時，在75℃至150℃之範圍內之一溫度可為較佳的以達成大於1J/m2且較佳地大於2J/m2之一接合能量。在使用一更薄材料或使用具有一較低CTE差異之材料的情況下，更高的溫度係可行的，以促進達成大於2.5J/m2之甚至更高接合能量。雖然此溫度範圍可足以達成一非常高之接合能量，但取決於金屬部分與絕緣部分之相對高度及所使用之金屬類型，其可能不足以形成3D互連。例如，若使用銅，則在銅比氧化矽絕緣部分低0nm至10nm之情況下可能需要150℃至250℃之一溫度範圍。或者，若使用鎳，則在鎳比氧化矽絕緣部分低0nm至10nm之情況下，可能需要250℃至350℃之一溫度範圍以製造3D互連。銅相比於鎳之較低溫度範圍需求係金屬之類型可影響溫度範圍之一實例，其中銅相比於鎳之膨脹係數(約13ppm/℃)之較高膨脹係數(約17ppm/℃)導致一給定溫度下之更大膨脹，從而導致對於接合表面之金屬部分及絕緣部分之間之一給定高度差異而言之更低溫度範圍。因此可能需要更高溫度以促進 電互連，然而歸因於可使絕緣部分之間之接合破裂或使經接合晶圓破裂之CTE誘發之應變，在經接合晶圓之此組態之情況下更高溫度係不可行的。
接著，如圖3中所展示將主要部分3減薄以形成具有通常在1微米至10微米範圍內之一厚度之經減薄層8。取決於應用及材料，層8之厚度可在此範圍之外。例如，具有小於2ppm/℃之一低CTE失配之經接合材料組合可容許在10微米至100微米範圍內之一較厚層8且需要小於一微米之層轉移之應用可使用0.10微米至1.0微米之一較薄層8。減薄可包含背部研磨、拋光、蝕刻或雷射剝離之一者或一組合。例如，若晶圓2係一GaN/藍寶石結構，則可使用雷射剝離以移除藍寶石，從而促成具有金屬接觸部分之一極薄GaN裝置層。歸因於增加的順應性或彈性，經減薄層8容許加熱至一更高溫度而不使絕緣部分之間之接合破裂或使經接合晶圓破裂。所容許之增加溫度取決於材料及層8之減小的厚度。例如，對於具有2ppm/℃至5ppm/℃之一高CTE失配之經接合材料及2微米至20微米之一層8厚度可藉由此減薄實現超過350℃之溫度(例如350℃至400℃)。由減小之層8厚度實現之此增加之溫度範圍可適於實現3D互連或用於其他處理(例如，氧化物沈積或退火)。沒有必要將此增加溫度範圍之全部範圍用於其他處理。例如，比增加溫度範圍之前所容許之溫度範圍更高且低於最大經增加溫度範圍之其他處理係可行的。
在一些情形中，在加熱晶圓以促進電互連的情況下，層8可能太薄而不能提供充分剛性以在晶圓1及晶圓2之表面處之金屬部分之間產生充分壓縮以形成可靠3D互連。例如，若層8之厚度係在1微米至10微米之範圍內(其中此層之一上部分(例如0.2微米至2.0微米)包括絕緣接合材料及導電接合材料之一異質組合)，則歸因於絕緣接合材料與導電接合材料之間之CTE差異，在低溫(例如低於300℃)下可在絕緣接 合材料與導電接合材料之間之介面鄰近處產生垂直於接合介面之相當大的應力。此垂直應力可使薄層扭曲，從而導致金屬部分之間之更小壓縮力且防止跨接合介面之電互連。此扭曲係由經減薄表面處之導電接合材料相對於絕緣接合材料之一CTE失配誘發之擠壓所引起，該擠壓歸因於經減薄層相比於未部分移除或完全移除基板之層之經減小剛性而不受經減薄層約束。
可藉由將一第三晶圓9接合至經減薄之主要部分8來補償此經減小剛性，以減小或防止層8之扭曲且在晶圓1及晶圓2之表面處之金屬部分之間實現充分壓縮以在接合第三晶圓9之後用加熱形成3D互連，如圖4中所展示。所需之第三晶圓9之最小厚度可以實驗方式決定，然而，此厚度通常小於一標準晶圓厚度，例如對於直徑為100mm至300mm晶圓而言，此厚度係50微米至100微米，而標準厚度約為0.5mm至0.8mm，因為剛性隨著取決於第三晶圓9之厚度之立方之相對小之厚度而實質上增加。可藉由在附接之前或在附接之後減薄第三晶圓9來獲得第三晶圓9之一減小厚度。亦可使用大於最小厚度之一晶圓9厚度，例如一標準晶圓厚度。
第三晶圓9之附接可使用各種方法，例如使用如申請案第09/505,283號中所描述之一直接接合，或如圖11中所展示之一夾具15。在使用一直接接合的情況下，附接可包含在晶圓9及/或經減薄部分8上添加接合層。在使用一夾具的情況下，在圖11中展示夾具15，其中施加至晶圓堆疊之兩側之外部壓力由箭頭表示。此可藉由如圖11中所展示自兩側施加外部壓力或藉由如圖12中所展示自一側施加外部壓力而相對側由一卡盤16遏制而進行。第三晶圓9較佳地具有與晶圓2相當之一CTE，以在形成3D互連之後續加熱期間防止過度應力。例如，若晶圓1係GaN/藍寶石，且晶圓2係矽CMOS，則第三晶圓9可為矽。CTE差異之可行範圍取決於材料、其面積及其厚度。例如，當接 合200mm直徑矽晶圓且將氧化矽及銅分別用作絕緣接合材料及導電接合材料時，較佳地具有小於0.5ppm/℃之一CTE差異。當使用較大晶圓(例如300mm晶圓)進行作業時，較佳地具有小於0.3ppm/℃之一較小CTE差異，且當使用較小晶圓(例如200mm晶圓)進行作業時，可具有小於1.0ppm/℃之一較大CTE差異。當使用具有一較小CTE差異之接合材料(例如氧化矽及鎳)進行作業時，較佳地具有具一較小CTE差異之晶圓以容許相對多之加熱。
如圖13至圖16中所展示之一撓性夾持配置可用於輔助在加熱期間將經接合晶圓固持在一起同時另外適應歸因於晶圓之CTE差異而在加熱期間將自然發生之晶圓之彎曲。此方法可適用於圖2之具有不同CTE之兩個晶圓之第一次接合(在圖13及圖14中以撓性夾具方法展示)，且亦適用於圖4之3層堆疊(其中兩個厚CTE匹配材料接合至夾在兩個較厚層之間之由不同CTE材料組成之較薄層)(在圖15及圖16中以撓性夾具方法展示)。撓性夾持配置由2層撓性材料(例如聚矽氧橡膠薄片)組成，該撓性材料圍封接合材料且在邊緣處密封從而形成密封包封體16。所使用之材料必須能夠耐受待施加至經接合層之溫度。藉由抽空撓性材料包封體內之空間從而圍繞結構之外側均勻地施加大氣壓力而施加壓力(圖13、圖15)，及/或藉由將撓性包封體及其內容物放入一高壓腔室17且圍繞該包封體及其內容物均勻地施加所要壓力以將諸層壓縮在一起而施加壓力(圖14、圖16)。在兩種情形中，接著將熱施加至包封體及其內容物以加強接合同時容許經接合堆疊之彎曲以適應CTE失配且防止層破裂。
在歸因於缺乏溫度而尚未製造互連之情況下，接著可將圖4中所展示之晶圓1、2及3之經接合堆疊加熱至比先前更高之溫度以形成3D互連。例如，在晶圓1係GaN/藍寶石，晶圓2係矽CMOS，晶圓3係矽且金屬係鎳的情況下，可能需要300℃至350℃。已藉由使用與晶圓1 CTE匹配之晶圓9替換與晶圓1 CTE失配之晶圓2之一主要部分來實現加熱至一更高溫度之此能力。歸因於CTE失配之此減小，現在此等更高溫度可用於以更高溫度促進電互連。歸因於將使絕緣部分之間之接合破裂或使經接合晶圓破裂之CTE誘發之應變，此等更高溫度先前係不可行的。
在加熱之後，如圖5中所展示可移除晶圓3以留下部分10。部分10可實質上為經減薄部分8或可更厚(例如在晶圓9之一接合層部分未被移除的情況下)或可更薄(例如在經減薄部分8之一接合層部分被移除的情況下)。移除可使用各種方法，例如，背部研磨、化學機械拋光或蝕刻之一者或一組合。當晶圓3係矽時可使用此等技術。例如在晶圓3具有一有用功能(例如作為一封裝功能之部分)的情況下，亦可不移除晶圓3。
現將描述根據本發明之方法之一第二實施例。晶圓11及晶圓12之任一者或兩者可含有延伸穿過晶圓11及晶圓12之任一者或兩者之全部、大部分或一部分之以金屬填充之一通孔13或若干通孔13，分別如圖6及圖7中對於經填充通孔13及14所展示，該等經填充通孔13及14分別延伸穿過晶圓11及晶圓12之約一半且相隔比接合介面處之導電材料更大之一間距。通孔可電連接至接合介面處之導電材料。若晶圓11及晶圓12二者具有經填充通孔，則該等經填充通孔在將晶圓1及晶圓2對準且放置在一起期間可為相對的，如分別對於經填充通孔13及14所展示。通孔13及通孔14亦可為不相對的。
在減薄晶圓12之後，通孔可如圖8中所展示般曝露或可具有防止曝露之晶圓1之一極薄殘留部分。例如，殘留晶圓12之厚度可為小於100微米。歸因於經填充通孔周圍材料之間之膨脹係數差異，對圖8中之結構或經填充通孔上具有一殘留部分之一類似結構進行加熱將導致除先前對於金屬接合所描述外之額外垂直及水平應力。缺乏用於抑制 此應力之鬆弛之一晶圓3可使直接金屬接合介面扭曲且防止適當接合。如圖9中所展示附接或接合一晶圓15可抑制此應力之鬆弛且減緩金屬接合介面之扭曲且促進跨金屬接合介面之3D電互連。如在實施例1中，此晶圓15較佳地由具有與晶圓11之CTE匹配之一CTE之材料製成。
在上述教示之背景下本發明之許多修改及變動係可能的。因此應理解，在隨附申請專利範圍之範疇內，可以不同於本文中特定描述之其他方式實踐本發明。
2‧‧‧晶圓
8‧‧‧經減薄層/較厚層/較薄層/層/經減薄之主要部分/經減薄部分
9‧‧‧第三晶圓/晶圓

Claims (57)

  1. 一種整合具有一第一接觸結構之一第一元件與具有一第二接觸結構之一第二元件之方法，該方法包括：將具有一第一金屬接合結構之一第一元件直接接合至具有一第二金屬接合結構之一第二元件；其中該第一金屬接合結構具有的一表面帶有一絕緣部分和一金屬部分，且該第二金屬接合結構具有的一表面帶有一絕緣部分和一金屬部分；將該第一元件減薄至在經加熱至一溫度以促進該第一直接金屬接合結構與該第二直接金屬接合結構之間之直接連接的情況下將導致該第一元件扭曲之一厚度；將具有厚度以減小該扭曲之一第三元件附接至該經減薄第一元件；加熱經接合第一元件、第二元件及第三元件；以及在該第一金屬接合結構與該第二金屬接合結構之間形成電連接；並且其中該第一金屬接合結構和該第二金屬接合結構業已製備成促進該第一元件中的絕緣部分和金屬部分與該第二元件中相應的絕緣部分和金屬部分進行直接接合。
  2. 如請求項1之方法，其進一步包括移除該第三元件。
  3. 如請求項1之方法，其中該接合包括使用一夾具施加壓力。
  4. 如請求項3之方法，其包括將該第一元件及該第二元件放置於一撓性容器中。
  5. 如請求項4之方法，其包括抽空該撓性容器。
  6. 如請求項4之方法，其包括將壓力施加至該容器。
  7. 一種經接合裝置，其包括：一第一元件，其具有直接金屬接合至具有一第二直接金屬接合結構之一第二元件之一第一直接金屬接合結構；其中該第一金屬接合結構具有的一表面帶有一絕緣部分和一金屬部分，且該第二金屬接合結構具有的一表面帶有一絕緣部分和一金屬部分；該第一元件具有在加熱至製造直接金屬連接所需之一溫度之情況下將引起該第一元件扭曲之一厚度；一第三元件，該第三元件經接合至該第一元件且具有足夠厚度以減小該扭曲以容許該第一直接金屬接合結構與該第二直接金屬接合結構之間之一直接連接；以及該第一金屬接合結構及該第二金屬接合結構之至少一者包括一熱膨脹金屬接觸件；並且其中該第一金屬接合結構和該第二金屬接合結構業已製備成促進該第一元件中的絕緣部分和金屬部分與該第二元件中相應的絕緣部分和金屬部分進行直接接合。
  8. 一種整合具有具一第一絕緣材料及一第一接觸結構之一第一表面之一第一元件與具有具一第二絕緣材料及一第二接觸結構之一第二表面之一第二元件之方法，該方法包括：將該第一絕緣材料直接接合至該第二絕緣材料；移除該第二元件之一部分以留下具有一第一厚度之一剩餘部分；將具有與該第一元件之一熱膨脹係數(CTE)實質上相同之一CTE之一第三元件直接接合至該剩餘部分；及加熱該第一元件及該第三元件及該剩餘部分以使該第一接觸結構及該第二接觸結構直接接觸。
  9. 如請求項8之方法，其進一步包括移除該第三元件。
  10. 如請求項8之方法，其中該第一接觸結構及該第二接觸結構包括鎳，該第一元件包括一GaN/藍寶石基板，該第二元件包括一矽CMOS基板，且該第三元件包括一矽基板，該方法包括：加熱至300℃至350℃之一範圍內之一溫度。
  11. 如請求項8之方法，其中該第一元件包括具有在約500微米至1000微米之厚度範圍內之藍寶石基板之一GaN/藍寶石結構，該第二元件包括500微米至750微米厚度之一矽CMOS基板，該方法包括：加熱至75℃至150℃之一範圍內之一溫度。
  12. 如請求項8之方法，其中該第一接觸結構及該第二接觸結構包括銅，該第一元件包括氧化矽，該第二元件包括氧化矽，該方法包括：加熱至約100℃之一溫度。
  13. 如請求項8之方法，其中該第一元件及該第二元件具有小於0.5ppm/℃之一熱膨脹係數差異。
  14. 如請求項8之方法，其中該第一元件及該第三元件具有實質上相同之熱膨脹係數。
  15. 如請求項14之方法，其中該第二元件具有不同於該第一元件及該第三元件之一熱膨脹係數。
  16. 如請求項8之方法，其中該第一厚度在1微米至10微米之一範圍內。
  17. 如請求項8之方法，其包括：直接接合具有與該第一元件之該CTE之差異在0.3ppm/℃至1.0ppm/℃之一範圍內之一熱膨脹係數的該第三元件。
  18. 如請求項8之方法，其包括： 直接接合具有與該第一元件之該CTE之差異小於約0.3ppm/℃之一熱膨脹係數的該第三元件。
  19. 如請求項8之方法，其包括：直接接合具有與該第一元件之該CTE之差異小於約0.5ppm/℃之一熱膨脹係數的該第三元件。
  20. 如請求項8之方法，其包括：直接接合具有與該第一元件之該CTE之差異小於約1.0ppm/℃之一熱膨脹係數的該第三元件。
  21. 如請求項8之方法，其中該第一接觸結構及該第二接觸結構之至少一者係銅，該方法包括：加熱至150℃至250℃之一範圍內之一溫度。
  22. 如請求項21之方法，其包括：形成該第一接觸結構及該第二接觸結構之至少一者以具有比該等各自第一及第二絕緣材料之一表面低0nm至10nm之一表面。
  23. 如請求項8之方法，其中該第一接觸結構及該第二接觸結構之至少一者係鎳，該方法包括：加熱至250℃至350℃之一範圍內之一溫度。
  24. 如請求項23之方法，其包括：形成該第一接觸結構及該第二接觸結構之至少一者以具有比該等各自第一及第二絕緣材料之一表面低0nm至10nm之一表面。
  25. 如請求項8之方法，其包括：將該第三材料減薄至約0.1nm至1nm之一範圍內之一厚度。
  26. 如請求項8之方法，其包括：將該第三材料減薄至約1nm至10nm之一範圍內之一厚度。
  27. 如請求項8之方法，其包括：將該第三材料減薄至約10nm至100nm之一範圍內之一厚度。
  28. 如請求項8之方法，其包括：將該第三材料減薄至約2nm至20nm之一範圍內之一厚度；及加熱至至少350℃之一溫度。
  29. 如請求項8之方法，其包括：形成連接至該第一接觸結構及該第二接觸結構之至少一者之以導電材料填充之一通孔。
  30. 如請求項8之方法，其中該第一接觸結構及該第二接觸結構之至少一者包括一直接金屬接合結構。
  31. 如請求項8之方法，其中該接合包括使用一夾具施加壓力。
  32. 如請求項31之方法，其包括將該第一元件及該第二元件放置於一撓性容器中。
  33. 如請求項32之方法，其包括抽空該撓性容器。
  34. 如請求項32之方法，其包括將壓力施加至該容器。
  35. 一種經接合結構，其包括：一第一元件，其具有具一第一絕緣材料及一第一接觸結構之一第一表面，該第一元件之一部分被移除；一第二元件，其具有具一第二絕緣材料及一第二接觸結構之一第二表面，該第一絕緣材料直接接合至該第二絕緣材料；一第三元件，其具有與該第一元件之一熱膨脹係數(CTE)實質上相同之一CTE且經直接接合至該第一元件；該第一接觸結構與該第二接觸結構彼此直接連接；及該第一接觸結構及該第二接觸結構之至少一者包括一熱膨脹金屬接觸件。
  36. 一種經接合結構，其包括： 一第一元件，其具有具一第一絕緣材料及一第一接觸結構之一第一表面，該第一元件之一部分被移除；一第二元件，其具有具一第二絕緣材料及一第二接觸結構之一第二表面，該第一絕緣材料直接接合至該第二絕緣材料；一第三元件，其具有與該第一元件之一熱膨脹係數(CTE)實質上相同之一CTE且經直接接合至該第一元件；該第一接觸結構與該第二接觸結構彼此直接連接；及該第一接觸結構及該第二接觸結構之至少一者包括一熱膨脹金屬接觸件。
  37. 如請求項36之經接合結構，其中該第一接觸結構及該第二接觸結構包括鎳，該第一元件包括一GaN/藍寶石基板，該第二元件包括一矽CMOS基板，且該第三元件包括一矽基板。
  38. 如請求項36之經接合結構，其中該第一元件包括具有範圍在約500微米至1000微米厚度之藍寶石基板之一GaN/藍寶石結構，且該第二元件包括500微米至750微米厚度之一矽CMOS基板。
  39. 如請求項36之經接合結構，其中該第一接觸結構及該第二接觸結構包括銅，該第一元件包括氧化矽，且該第二元件包括氧化矽。
  40. 如請求項36之經接合結構，其中該第一元件及該第二元件具有小於0.5ppm/℃之熱膨脹係數之一差異。
  41. 如請求項36之經接合結構，其中該第一元件及該第三元件具有實質上相同之熱膨脹係數。
  42. 如請求項41之經接合結構，其中該第二元件具有不同於該第一元件及該第三元件之一熱膨脹係數。
  43. 如請求項36之經接合結構，其包括：該第三元件具有與該第一元件之該CTE之差異在0.3ppm/℃至 1.0ppm/℃之一範圍內之一熱膨脹係數。
  44. 如請求項36之經接合結構，其包括：該第三元件具有與該第一元件之該CTE之差異小於約0.3ppm/℃之一熱膨脹係數。
  45. 如請求項36之經接合結構，其包括：該第三元件具有與該第一元件之該CTE之差異小於約0.5ppm/℃之一熱膨脹係數。
  46. 如請求項36之經接合結構，其包括：該第三元件具有與該第一元件之該CTE之差異小於約1.0ppm/℃之一熱膨脹係數。
  47. 如請求項36之經接合結構，其中該第一接觸結構及該第二接觸結構之至少一者係銅和鎳中的一者。
  48. 如請求項36之經接合結構，其包括：該第一接觸結構及該第二接觸結構中至少一者具有的一表面比各自的該第一絕緣材料及該第二絕緣材料之一表面低0nm至10nm。
  49. 如請求項36之經接合結構，其包括：該第三材料具有約0.1nm至1nm之一範圍內之一厚度。
  50. 如請求項36之經接合結構，其包括：該第三材料具有約1nm至10nm之一範圍內之一厚度。
  51. 如請求項36之經接合結構，其包括：該第三材料具有約10nm至100nm之一範圍內之一厚度。
  52. 如請求項36之經接合結構，其包括：該第三材料具有約2nm至20nm之一範圍內之一厚度。
  53. 如請求項36之經接合結構，其包括：以導電材料填充形成之一通孔，其連接至該第一接觸結構及 該第二接觸結構之至少一者。
  54. 如請求項53之經接合結構，其包括：該通孔經曝露於該第一材料和該第二材料之一者的一表面上。
  55. 如請求項36之經接合結構，其中該第一接觸結構及該第二接觸結構之至少一者包括一直接金屬接合結構。
  56. 如請求項36之經接合結構，其中該第一元件具有1微米至10微米之一範圍內之一厚度。
  57. 如請求項36之經接合結構，其中該第一元件具有10微米至100微米之一範圍內之一厚度，以及比該第二材料的CTE之小2ppm/℃之一熱膨脹係數。
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US8735219B2 (en) 2014-05-27
US20230207322A1 (en) 2023-06-29
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US9184125B2 (en) 2015-11-10
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US9698126B2 (en) 2017-07-04
US20160099233A1 (en) 2016-04-07
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US20140061949A1 (en) 2014-03-06
US20200328193A1 (en) 2020-10-15
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US10777533B2 (en) 2020-09-15
US20170301656A1 (en) 2017-10-19

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