TW200305263A - Semiconductor chip with protective layer and production process - Google Patents

Semiconductor chip with protective layer and production process Download PDF

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Publication number
TW200305263A
TW200305263A TW092104462A TW92104462A TW200305263A TW 200305263 A TW200305263 A TW 200305263A TW 092104462 A TW092104462 A TW 092104462A TW 92104462 A TW92104462 A TW 92104462A TW 200305263 A TW200305263 A TW 200305263A
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protective layer
wafer
semiconductor wafer
contact area
semiconductor
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TW092104462A
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Chinese (zh)
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Erik Heinemann
Juergen Fischer
Ida Marbach-Fischbach
Volker Beyer
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Infineon Technologies Ag
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01052—Tellurium [Te]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dicing (AREA)
  • Wire Bonding (AREA)

Abstract

In the flip-chip mounting of semiconductor chips: for protection from mechanical stress or damage and for electrical insulation, a protective layer (7) is applied to the rear side of the semiconductor chip (2). This protective layer may also be present on the flanks (8) of the semiconductor chip. The protective layer may be applied before the beginning of the overall assembly process sequence or only when fixing the semiconductor chip upside down on a carrier 1.

Description

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敘述 具保護層之半導體 本發明係關於' 種 免於機械應力、損害及 在覆晶裝設的製造 器、拾取裝置、轉移裝 接接觸。即使在半導體 後’而後露出的後側及 於風險。在覆晶裝設期 作伴隨耆機械地損壞該 裝材料的外封）僅在製 為在覆晶裝設中建 佳為使用傳導性黏著劑 式彼此連接晶片接觸點 不可在晶片側面上，因 於小晶片的情況及特別 方側周圍外側，亦即在 本發明目的為提供 晶裝設的機械損壞或電 此目的可藉由具申 日 LJ 曰日片及具申請專利範圍 到。細節得自附屬申請 為免於機械應力或 的，一種保護層被施用 晶片及製造方法 覆晶裝詨尚半導體晶片，其被保護 電子短路。 方法中，晶片的背面重覆地與鑽孔 置及處理及輸送晶片的其他裝置直 晶片倒置在載體上的實際覆晶裝設 侧面因該晶片的進一步處理而被置 間及覆晶裝設之後的每一個加工操 晶片的兩風險。一種封裝（如具封 造方法結束時立即施用於該晶片。 立半導體晶片的電子終端接觸，較 或焊劑。這些物質提供以電傳導方 及載體接觸點的目的；然而，它們 此會導致短路。此風險尤其是存在 是在於晶片上的接觸區域被置於上 邊緣附近，的所有晶片之情況。 未封裝的半導體晶片，其具免於覆 子短路的保護。 f專利範圍第1項的特徵之半導體 第3項的特徵之覆晶裝設方法而達 專利範圍。 損^的保護及為進行電絕緣的目 於半導體晶片的後側。此保護層亦The present invention relates to a maker, pick-up device, and transfer contact that are free from mechanical stress, damage, and mounting on a flip chip. Even after the semiconductor 'is exposed, the rear side is exposed to risks. During the flip-chip installation period, it is used as an external seal that mechanically damages the package material.) Only in the flip-chip installation, Jianjia uses conductive adhesive to connect the wafers to each other. The contact points of the wafers cannot be on the side of the wafer. In the case of small wafers and around the outer side of the special square side, that is, the purpose of the present invention is to provide mechanical damage or electricity to the crystal device. This purpose can be achieved by applying the Japanese LJ Japanese film and the patent scope. Details from the attached application To protect against mechanical stress or damage, a protective layer is applied to the wafer and manufacturing method. In the method, the backside of the wafer is repeatedly overlapped with other devices for drilling and processing and transporting the wafer. The actual flip chip mounting side of the wafer is inverted on the carrier. The side is interposed and mounted after the flip chip is further processed. There are two risks to each processing wafer. An encapsulation (such as applied immediately to the wafer at the end of the encapsulation method). The electronic terminal contacts of the semiconductor wafer, or solder. These substances are provided for the purpose of electrical conduction and contact points on the carrier; however, they can cause short circuits. This risk especially exists in the case of all wafers where the contact area on the wafer is placed near the upper edge. Unpackaged semiconductor wafers are protected against short-circuiting of the cover. F Feature of item 1 of patent scope The method of flip-chip mounting of the third feature of the semiconductor reaches the scope of the patent. The protection of damage and the purpose of electrical insulation is on the rear side of the semiconductor wafer. This protective layer is also

第6頁 200305263Page 6 200305263

該保護層可在整體組裝方 可存在於該半導體晶片的側面 法順序開始前施用。 側面保護可在方法順序開兹俞施用於晶片，基於此目 具半導體晶片的晶圓最初在切割道自前側被蝕刻，其 提供積體電路及接觸區域或其類似物，故個別半導體晶片' 的側面為露出的。在此情況下蝕刻深度被選擇為符合所欲The protective layer may be applied before the whole assembly can be present on the side of the semiconductor wafer before the sequence starts. The side protection can be applied to the wafer in the method sequence. Based on this, the wafer of the semiconductor wafer is initially etched from the front side in the scribe line, which provides integrated circuits and contact areas or the like. Therefore, individual semiconductor wafers' The side is exposed. In this case, the etch depth is selected as desired

晶片厚度，此之後為PI或類似方法，故晶片的側面以 層覆蓋。 …I 之後’晶圓自與前側相對的後側被薄化，直到晶圓厚 度的未被姓刻元件被移除且晶片被接著單獨地分開。之 後’保護層可被施用於晶片的後側。此後側塗層可在半導 體晶片被置於載體後施用，此載體為進行覆晶裝設用，可 精由自後側壓下進行的固定晶片前或後選擇性地精確施 用0 因晶片邊緣為特別敏感，提供用做保護層的材料量較 佳為被設定以使當保護層被施用時，材料亦覆蓋在晶片側 面上的邊緣。 除了僅在晶片的單獨分開後被施用，該保護層亦可在 晶片被單獨分開前被施用於該半導體晶片的後側。在此情 況下，在切割前側之後，該晶圓被自後側薄化僅至晶片仍 連接在^一起的程度，雖然措由半導體材料的非常薄的橋， 該保護層可再被施用於後側，之後，該晶圓破裂以分開個 別半導體晶片。在此製造方法的變化之情況下，施用側面 保護及後側保護的方法步驟在製造方法為緊密在一起的，Wafer thickness, PI or similar methods thereafter, so the sides of the wafer are covered with layers. … I ”The wafer is thinned from the rear side opposite the front side until the un-engraved components of the wafer thickness are removed and the wafer is then separated separately. After that, a protective layer can be applied to the back side of the wafer. The backside coating can be applied after the semiconductor wafer is placed on a carrier. This carrier is used for flip-chip mounting. It can be selectively applied precisely before or after fixing the wafer by pressing from the backside. Particularly sensitive, the amount of material provided as a protective layer is preferably set so that when the protective layer is applied, the material also covers the edges on the side of the wafer. In addition to being applied only after the wafer is separately separated, the protective layer may be applied to the rear side of the semiconductor wafer before the wafer is individually separated. In this case, after cutting the front side, the wafer is thinned from the back side only to the extent that the wafers are still connected together, although the protective layer can be applied to the rear side even though the semiconductor material is a very thin bridge Later, the wafer is cracked to separate individual semiconductor wafers. In the case of a change in this manufacturing method, the method steps of applying side protection and back protection are close together in the manufacturing method,

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晶片已被置於載體時施用後側 + ^ 非傳導或至少不均向性沲傳導材料被用於保護層， r:的轭用較佳為藉由分配方法進行。在簡化細節的情 況下，晶片側面的保護可被省略。 在相關圖式中，在覆晶裝置中半導體晶片的實例以截 面表不。倒置放置於載體丨上的是半導體晶片2，故該載體 的接觸區域3及該半導體晶片2的接觸區域4被彼此相對放 、:別彼此指定的接觸區域藉由傳導性黏著劑或焊劑彼 此永m連接。該接觸區域4位於該半導體晶片2的前側5， 该半導體晶片2的後側6具保護層7，在此實例中，其亦以 元件9覆蓋側面8，但於此可省略。額外說明的為填充材料 (下方填充）1 0，以此材料，在該載體丨及該半導體晶片2 間的中間空間被填充。The back side is applied when the wafer has been placed on the carrier. A non-conductive or at least non-isotropic 沲 conductive material is used for the protective layer. The r: yoke is preferably made by a dispensing method. Where the details are simplified, the protection of the sides of the wafer can be omitted. In the related drawings, an example of a semiconductor wafer in a flip-chip device is shown in a cross section. The semiconductor wafer 2 is placed on the carrier upside down, so the contact area 3 of the carrier and the contact area 4 of the semiconductor wafer 2 are placed opposite to each other: the contact areas designated by each other are not permanently connected to each other by a conductive adhesive or solder. m connection. The contact area 4 is located on the front side 5 of the semiconductor wafer 2, and the rear side 6 of the semiconductor wafer 2 is provided with a protective layer 7. In this example, it also covers the side surface 8 with the element 9, but it can be omitted here. The additional description is a filling material (filling below) 10, with which the intermediate space between the carrier and the semiconductor wafer 2 is filled.

200305263 圖式簡單說明 第1圖式說明覆晶裝置中半導體晶片的實例以截面表示。 元件符號說明 1 載體 3 載體的接觸區域 5 半導體晶片的前側 7 保護層 9 保護層的元件 2半導體晶片 4 半導體晶片的接觸區域 6 半導體晶片的後側 8 側面 1 0填充材料200305263 Brief Description of Drawings Figure 1 illustrates an example of a semiconductor wafer in a flip-chip device in cross section. Description of component symbols 1 Carrier 3 Contact area of the carrier 5 Front side of the semiconductor wafer 7 Protective layer 9 Elements of the protective layer 2 Semiconductor wafer 4 Contact area of the semiconductor wafer 6 Back side of the semiconductor wafer 8 Side surface 1 0 Filling material

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Claims (1)

200305263 六、申請專利範圍 1· 一種具接觸區域的本道辨，# 热 於一盤# π〗的丰體日曰片其以一覆晶裝置連接 A 、的接觸區域，其特徵在於遠離該接觸區 / 白、“導體晶片（2 P的1後側（6 )被提供保護層 2 圍 範OC 利Γ 專面 請側 申的 據片 根晶 第 被 體9 導C 半件 該元 中步 其一 ，進 片更 晶的 體層 導護 半保 的該 項供 提 3 · 一種半導體晶片覆晶裝設的方法，其中一種電非傳導 或不均向傳導材料的保護層（7 )被施用於遠離該半導 體晶片的接觸區域（4 )的該半導體晶片的後侧（6 )0 4·根據申請專利範圍第3項的方法，其中該保護層係在該 半導體晶片被置於欲進行覆晶裝設的載體上後且於壓 力存在下該半導體晶片的固定前施用。 5 ·根據申請專利範圍第3項的方法，其中該保護層係在該 半導體晶片被置於欲進行覆晶裝設的載體上後且於壓 力存在下該半導體晶片的固定後施用。 6 ·根據申請專利範圍第3項的方法，其中在晶圓的該半導 體晶片被自前側切割，被提供接觸區域，以侧面露 出，該側面被提供一種保護層，該晶圓自與前側相對 的後側被薄化，該半導體晶片未被單獨地分開，該保 護層被施用於後側且該晶圓破裂以分開個別半導體晶 片。200305263 VI. Scope of patent application 1. A true identification with a contact area, # 热 于 一 盘 # π of the Fengtian Japanese film is connected to the contact area of A with a flip chip device, which is characterized by being far away from the contact area / White, "conductor wafer (2 P, 1 back side (6) is provided with a protective layer 2 range OC, benefit Γ, special side, please apply according to the piece of root crystal, 9th guide C, half of this element This method of providing a more crystalline body-layer guide protects the semiconductor device. 3 · A method for mounting a semiconductor wafer on a chip, in which a protective layer (7) of electrically non-conductive or non-uniform conductive material is applied away from the The rear side (6) of the semiconductor wafer in the contact area (4) of the semiconductor wafer. 4. The method according to item 3 of the patent application scope, wherein the protective layer is placed on the semiconductor wafer to be subjected to a flip-chip mounting. Apply on the carrier and before the fixing of the semiconductor wafer in the presence of pressure. 5 · The method according to item 3 of the scope of patent application, wherein the protective layer is after the semiconductor wafer is placed on a carrier to be flip-chip mounted And stored under pressure The semiconductor wafer is applied after being fixed. 6 · The method according to item 3 of the patent application scope, wherein the semiconductor wafer on the wafer is cut from the front side, provided with a contact area to be exposed on the side, and the side is provided with a protective layer The wafer is thinned from the back side opposite to the front side, the semiconductor wafer is not separately separated, the protective layer is applied to the back side and the wafer is cracked to separate individual semiconductor wafers. 第10頁Page 10
TW092104462A 2002-04-08 2003-03-03 Semiconductor chip with protective layer and production process TW200305263A (en)

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JPS5645056A (en) * 1979-09-21 1981-04-24 Hitachi Ltd Manufacture of semiconductor device
JPS61112345A (en) * 1984-11-07 1986-05-30 Toshiba Corp Manufacture of semiconductor device
JPH08204497A (en) * 1995-01-26 1996-08-09 Murata Mfg Co Ltd Surface acoustic wave device
JPH11102985A (en) * 1997-09-26 1999-04-13 Mitsubishi Electric Corp Semiconductor integrated circuit device
US6023094A (en) * 1998-01-14 2000-02-08 National Semiconductor Corporation Semiconductor wafer having a bottom surface protective coating
US6075290A (en) * 1998-02-26 2000-06-13 National Semiconductor Corporation Surface mount die: wafer level chip-scale package and process for making the same
EP1014444A1 (en) * 1999-05-14 2000-06-28 Siemens Aktiengesellschaft Integrated circuit with protection layer and fabrication method therefor
JP2001085560A (en) * 1999-09-13 2001-03-30 Sharp Corp Semiconductor device and manufacture thereof
JP3604988B2 (en) * 2000-02-14 2004-12-22 シャープ株式会社 Semiconductor device and manufacturing method thereof
JP3456462B2 (en) * 2000-02-28 2003-10-14 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP2002043251A (en) * 2000-07-25 2002-02-08 Fujitsu Ltd Semiconductor device and method of manufacturing

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