TWI548051B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI548051B
TWI548051B TW099112370A TW99112370A TWI548051B TW I548051 B TWI548051 B TW I548051B TW 099112370 A TW099112370 A TW 099112370A TW 99112370 A TW99112370 A TW 99112370A TW I548051 B TWI548051 B TW I548051B
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Taiwan
Prior art keywords
bonding
region
bonding pad
semiconductor wafer
semiconductor device
Prior art date
Application number
TW099112370A
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English (en)
Chinese (zh)
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TW201104816A (en
Inventor
安村文次
土屋文男
伊東久範
井手琢二
川邊直樹
佐藤齊尚
Original Assignee
瑞薩電子股份有限公司
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Publication of TW201104816A publication Critical patent/TW201104816A/zh
Application granted granted Critical
Publication of TWI548051B publication Critical patent/TWI548051B/zh

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    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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JP5160498B2 (ja) * 2009-05-20 2013-03-13 ルネサスエレクトロニクス株式会社 半導体装置
JP5618873B2 (ja) * 2011-03-15 2014-11-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2013062328A (ja) * 2011-09-12 2013-04-04 Toshiba Corp 半導体装置
JP5926988B2 (ja) 2012-03-08 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US9111847B2 (en) * 2012-06-15 2015-08-18 Infineon Technologies Ag Method for manufacturing a chip package, a method for manufacturing a wafer level package, a chip package and a wafer level package
WO2013010512A2 (en) * 2012-10-22 2013-01-24 Spreadtrum Communications (Shanghai) Co., Ltd. Apparatus and method of electrical testing for flip chip
CN103107128B (zh) * 2013-01-14 2014-12-17 武汉新芯集成电路制造有限公司 一种三维芯片结构的金属键合的方法
JP6149503B2 (ja) * 2013-05-17 2017-06-21 住友電気工業株式会社 半導体装置
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