JP5331934B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5331934B2 JP5331934B2 JP2012271050A JP2012271050A JP5331934B2 JP 5331934 B2 JP5331934 B2 JP 5331934B2 JP 2012271050 A JP2012271050 A JP 2012271050A JP 2012271050 A JP2012271050 A JP 2012271050A JP 5331934 B2 JP5331934 B2 JP 5331934B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- bonding pad
- region
- semiconductor device
- protective film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Description
本実施の形態1によるワイヤボンディング接続を採用したフェースアップボンディング構造のBGA(Ball Grid Array)型半導体装置について図1〜図4を用いて説明する。図1はワイヤボンディング接続を採用したBGA型半導体装置の構成を示す平面図、図2はワイヤボンディング接続を採用したBGA型半導体装置の構成を示す断面図、図3はボンディングパッドを拡大して示す要部平面図、図4はボンディングパッドの一部を拡大して示す要部断面図(図3のI−I′線に沿った断面図)である。
本実施の形態2は、前述した実施の形態1によるボンディングパッドBP1の変形例であり、ボンディングパッドおよび開口部の形状、ならびにボンディングパッドの配置が前述した実施の形態1で説明したものと異なる。本実施の形態2によるボンディングパッドの形状および配置を図7および図8を用いて説明する。図7はボンディングパッドを拡大して示す要部平面図、図8はボンディングパッドの一部を拡大して示す要部断面図(図7のII−II′線に沿った断面図)である。
近年、前述の図2に示したように、半導体チップ3が搭載される配線基板2または半導体チップ3を封止する樹脂封止体10を構成する樹脂部材(レジン材)に、環境保護および環境負荷物質の低減の観点からハロゲンフリー部材が使用されるようになってきている。具体的には、電気・電子機器の廃棄物の収集および回収が規定され、さらに、分別回収された廃棄物から除外すべき物質に臭素系難燃剤を含有するプラスチックがWEEE(Waste Electrical and Electronic Equipment)指令によって規定されている。このため、配線基板2または樹脂封止体10を構成する樹脂部材(レジン材)に対して、ハロゲンフリー部材を使用する要求が拡大している。配線基板2に使用するハロゲンフリー部材とは、塩素の含有率が0.09重量%以下で、臭素の含有率が0.09重量%以下であり、かつ、塩素と臭素の総量が0.15重量%以下である材料である。また、樹脂封止体10を構成する樹脂部材(レジン材)に使用するハロゲンフリー部材とは、塩素の含有率が0.09重量%以下で、臭素の含有率が0.09重量%以下であり、かつ、アンチモンの含有率が0.09重量%以下である材料である。つまり、配線基板2および樹脂封止体10を構成する樹脂部材(レジン材)にハロゲンフリー部材を使用した場合は、前述のWEEE指令によって規定されている材料を使用していることになる。
本実施の形態4は、電源用ボンディングパッドにおいて生じる保護膜のクラックを防止することのできる電源用ボンディングパッドおよび開口部の形状について説明する。
2 配線基板
2x 主面
2y 裏面
3 半導体チップ
3a パッド領域
3b コア領域
4 半田ボール
5 保護膜
5a 酸化シリコン膜
5b 窒化シリコン膜
6,6a 開口部
7 ボンディングリード
8 裏面電極パッド
9B バンプ
9W ボンディングワイヤ
10 樹脂封止体
11 反射防止膜
12 開口部
13 保護膜
13a 第1絶縁膜
13b 第2絶縁膜
13c 第3絶縁膜
14 スリット
51 保護膜
51a 酸化シリコン膜
51b 窒化シリコン膜
52 窒化チタン膜
53 クラック
54 金属ボール
55 開口部
56 保護膜
57 クラック
B1 ボンディングパッド
B1p プローブ領域
B1w ワイヤボンディング領域
BP1,BP2,BP3 ボンディングパッド
BP1p,BP2p,BP3p,BP4p プローブ領域
BP1w,BP2w,BP3w,BP4w ワイヤボンディング領域
VB 電源用ボンディングパッド
VBp プローブ領域
VBw ワイヤボンディング領域
VBP1,VBP2 電源用ボンディングパッド
Claims (18)
- ボンディング領域とプローブ領域とが区分された長方形状の複数のボンディングパッドが配置された主面と、前記主面とは反対側の裏面と、を有する四角形の半導体チップを搭載する半導体装置であって、
前記半導体チップは、前記ボンディングパッドの上層に保護膜を有し、
前記保護膜は、前記ボンディングパッドの周縁部を覆い、前記ボンディングパッドの上面が露出するように開口されており、
前記ボンディング領域における前記ボンディングパッドの周縁部と前記保護膜との重なり幅が、前記プローブ領域における前記ボンディングパッドの周縁部と前記保護膜との重なり幅よりも広く、
前記保護膜が開口された部分の形状が凸形状であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
複数のボンディングリードが形成された主面と、前記主面とは反対側の裏面と、を有する配線基板と、
前記半導体チップの前記主面に、前記半導体チップの各辺に沿って前記複数のボンディングパッドが配置されたパッド領域と、前記パッド領域の内側に集積回路が形成されたコア領域と、をさらに有し、
前記配線基板の前記主面と前記半導体チップの前記裏面とを対向させて、前記配線基板の前記主面上に前記半導体チップが搭載され、前記ボンディングパッドと前記ボンディングリードとは、ボンディングワイヤにより電気的に接続されており、
前記ボンディング領域は、前記プローブ領域よりも前記半導体チップの辺に近くなるように、前記ボンディングパッドが配置されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記ボンディングワイヤは、熱圧着に超音波振動を併用したボンディング法により、前記ボンディングパッドにそれぞれ電気的に接続されていることを特徴とする半導体装置。 - 請求項3記載の半導体装置において、
前記ボンディングワイヤは金線であり、前記ボンディングパッドはアルミニウム膜を主材料とする金属膜であることを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
隣接する前記ボンディングパッドの間は前記保護膜により埋め込まれていることを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記保護膜は複数の絶縁膜を成膜した積層膜からなり、最上層の絶縁膜は、窒化シリコン膜であることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記ボンディング領域における前記ボンディングパッドの周縁部と前記保護膜との重なり幅は2.5μmよりも広いことを特徴とする半導体装置。 - 請求項7記載の半導体装置において、
前記ボンディング領域における前記ボンディングパッドの周縁部と前記保護膜との重なり幅は5μm、前記プローブ領域における前記ボンディングパッドの周縁部と前記保護膜との重なり幅は2.5μmであることを特徴とする半導体装置。 - 請求項8記載の半導体装置において、
前記保護膜は、第1厚さを有する第1絶縁膜、前記第1絶縁膜上に前記第1厚さよりも厚い第2厚さを有する第2絶縁膜、および前記第2絶縁膜の上に最上層の第3絶縁膜により構成されており、
前記ボンディングパッドの周縁部は、前記第1絶縁膜および前記第2絶縁膜からなる積層膜で覆われており、さらに前記ボンディングパッド上の前記第1絶縁膜および前記第2絶縁膜の端部を前記第3絶縁膜が覆っていることを特徴とする半導体装置。 - 請求項9記載の半導体装置において、
前記ボンディングパッドと前記第3絶縁膜との重なり幅は2.5μmであることを特徴とする半導体装置。 - 請求項10記載の半導体装置において、
前記半導体チップ、前記ボンディングワイヤ、および前記配線基板の前記主面の一部は、絶縁性樹脂からなる樹脂封止体により封止されていることを特徴とする半導体装置。 - 請求項11記載の半導体装置において、
前記配線基板および前記樹脂封止体を構成する樹脂部材は、ハロゲンフリー部材であることを特徴とする半導体装置。 - 請求項12記載の半導体装置において、
前記配線基板の前記裏面には、半田ボールが備えられていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
複数のボンディングリードが形成された主面を有する配線基板と、
前記半導体チップの前記主面に、前記半導体チップの各辺に沿って前記複数のボンディングパッドが配置されたパッド領域と、前記パッド領域の内側に集積回路が形成されたコア領域と、をさらに有し、
前記配線基板の前記主面と前記半導体チップの前記主面とを対向させて、前記配線基板の前記主面上に前記半導体チップが搭載され、前記ボンディングパッドと前記ボンディングリードとは、バンプにより電気的に接続されており、
前記プローブ領域は、前記ボンディング領域よりも前記半導体チップの辺に近くなるように、前記ボンディングパッドが配置されていることを特徴とする半導体装置。 - 請求項14記載の半導体装置において、
前記集積回路は、CPU、DSP、RAM、PLL、およびDLLを含むことを特徴とする半導体装置。 - ボンディング領域とプローブ領域とが区分された凸形状の複数のボンディングパッドが配置された主面と、前記主面とは反対側の裏面と、を有する四角形の半導体チップを搭載する半導体装置であって、
前記半導体チップは、前記ボンディングパッドの上層に保護膜を有し、
前記保護膜は、前記ボンディングパッドの周縁部を覆い、前記ボンディングパッドの上面が露出するように開口されており、
前記ボンディング領域における前記ボンディングパッドの周縁部と前記保護膜との重なり幅が、前記プローブ領域における前記ボンディングパッドの周縁部と前記保護膜との重なり幅よりも広く、
前記複数のボンディングパッドのそれぞれは、前記半導体チップの辺に沿って前記ボンディングパッドの長手方向にそれぞれ交互にずらされ、かつ、前記凸形状が交互に反転するように配置されていることを特徴とする半導体装置。 - 請求項16記載の半導体装置において、
前記保護膜が開口された部分の形状は長方形状であることを特徴とする半導体装置。 - ボンディング領域とプローブ領域とを区分した四角形状の電源用ボンディングパッドを有する半導体チップを搭載する半導体装置であって、
前記電源用ボンディングパッドの上層に、前記電源用ボンディングパッドの上面の一部を前記ボンディング領域および前記プローブ領域を跨いで露出させる2つの開口部を有する保護膜が形成され、前記2つの開口部のそれぞれから前記電源用ボンディングパッドの前記ボンディング領域および前記プローブ領域が露出し、前記2つの開口部の間の前記電源用ボンディングパッドの前記ボンディング領域のみにスリットが入っており、
前記電源用ボンディングパッドの周縁部を覆って前記保護膜が形成されており、前記ボンディング領域における前記電源用ボンディングパッドの周縁部と前記保護膜との重なり幅が、前記プローブ領域における前記電源用ボンディングパッドの周縁部と前記保護膜との重なり幅よりも広いことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012271050A JP5331934B2 (ja) | 2012-12-12 | 2012-12-12 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012271050A JP5331934B2 (ja) | 2012-12-12 | 2012-12-12 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009121857A Division JP5160498B2 (ja) | 2009-05-20 | 2009-05-20 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013156482A Division JP5732493B2 (ja) | 2013-07-29 | 2013-07-29 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013058804A JP2013058804A (ja) | 2013-03-28 |
JP5331934B2 true JP5331934B2 (ja) | 2013-10-30 |
Family
ID=48134326
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012271050A Active JP5331934B2 (ja) | 2012-12-12 | 2012-12-12 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5331934B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7143879B2 (ja) | 2017-07-17 | 2022-09-29 | 株式会社村田製作所 | 分布型rc終端器 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0220034A (ja) * | 1988-07-07 | 1990-01-23 | Matsushita Electron Corp | 半導体装置 |
JP3022819B2 (ja) * | 1997-08-27 | 2000-03-21 | 日本電気アイシーマイコンシステム株式会社 | 半導体集積回路装置 |
JP4803966B2 (ja) * | 2004-03-31 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2009218264A (ja) * | 2008-03-07 | 2009-09-24 | Elpida Memory Inc | 半導体装置 |
JP5443827B2 (ja) * | 2009-05-20 | 2014-03-19 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
-
2012
- 2012-12-12 JP JP2012271050A patent/JP5331934B2/ja active Active
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7143879B2 (ja) | 2017-07-17 | 2022-09-29 | 株式会社村田製作所 | 分布型rc終端器 |
Also Published As
Publication number | Publication date |
---|---|
JP2013058804A (ja) | 2013-03-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5160498B2 (ja) | 半導体装置 | |
US9589921B2 (en) | Semiconductor device | |
US9362187B2 (en) | Chip package having terminal pads of different form factors | |
JP3999720B2 (ja) | 半導体装置およびその製造方法 | |
JP2009246218A (ja) | 半導体装置の製造方法および半導体装置 | |
JPH09330934A (ja) | 半導体装置及びその製造方法 | |
JP2006210438A (ja) | 半導体装置およびその製造方法 | |
JP5732493B2 (ja) | 半導体装置 | |
US20080258306A1 (en) | Semiconductor Device and Method for Fabricating the Same | |
JP2011222738A (ja) | 半導体装置の製造方法 | |
US20040012078A1 (en) | Folded tape area array package with one metal layer | |
EP1909323A2 (en) | Semiconductor device and method for manufacturing the same | |
JP3559554B2 (ja) | 半導体装置およびその製造方法 | |
JP2010186916A (ja) | 半導体装置の製造方法 | |
JP2007103733A (ja) | 基板およびそれを用いた半導体装置 | |
JP5331934B2 (ja) | 半導体装置 | |
TWI642159B (zh) | 封裝結構 | |
JP4498336B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2010093106A (ja) | 半導体装置およびその製造方法 | |
JP3923944B2 (ja) | 半導体装置 | |
KR100968008B1 (ko) | 반도체장치 및 그 제조방법 | |
JP2004296464A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130627 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130702 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130729 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5331934 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |