CN101894816B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101894816B
CN101894816B CN201010176519.7A CN201010176519A CN101894816B CN 101894816 B CN101894816 B CN 101894816B CN 201010176519 A CN201010176519 A CN 201010176519A CN 101894816 B CN101894816 B CN 101894816B
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bonding
bonding pad
protective film
region
semiconductor chip
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CN201010176519.7A
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CN101894816A (zh
Inventor
安村文次
土屋文男
伊东久范
井手琢二
川边直树
佐藤齐尚
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to CN201610424138.3A priority Critical patent/CN106024744A/zh
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Abstract

本发明提供了一种可以防止半导体器件的最上层中的保护膜断裂以及改进半导体器件可靠性的技术。在半导体芯片的主表面上方形成的键合焊盘为四边形形状，并且按照以下方式在每个键合焊盘上方的保护膜中形成开口，即，每个键合焊盘的接线键合区域中的保护膜交叠宽度变得宽于每个键合焊盘的探针区域中的保护膜交叠宽度。

Description

半导体器件
相关申请的交叉引用
在此通过引用并入提交于2009年5月20日的日本专利申请No.2009-121857的公开内容，包括说明书、附图和摘要。
技术领域
本发明涉及半导体器件，具体地，涉及有效适用于具有其上安装有键合焊盘的半导体芯片的半导体器件的技术。
背景技术
日本专利待审公开No.1991-79055(专利文献1)例如公开了一种电极焊盘，其具有用于键合接线或者薄膜引线的第一部分，以及一体化连接至第一部分的第二部分，该第二部分可以通过不同于第一部分的图案来识别，并且在晶片测试中与探针接触。
日本专利待审公开No.2000-164620(专利文献2)公开了一种能够进行半导体器件的安全检查和键合的技术，其是通过使电极焊盘具有用于键合的电极区域以及用于检查的键合区域，并且将用于键合的电极区域的中心与用于检查的键合区域的中心隔开预定的间隔或更多而实现的。
日本专利待审公开No.2001-338955(专利文献3)公开了一种接线键合技术，其中键合焊盘具有键合区域和探针接触区域，其中传导接线的一端键合至键合区域，并且测试探针的尖端与探针接触区域相接触。
日本专利待审公开No.2007-318014(专利文献4)公开了一种半导体器件，其中具有第一区域和第二区域的多个焊盘形成为矩形形状，其中每个焊盘在拐角的部分中具有倒角部分，并且焊盘呈锯齿状对齐，并且在锯齿对齐的内部和外部行中的焊盘中相对地提供进一步的倒角部分，并且将第一区域置于半导体芯片的核心逻辑区域之侧。
发明内容
在半导体器件中，接线键合连接系统被用作将在半导体芯片主表面上形成的集成电路与其上安装有半导体芯片的衬底的主表面上形成的连接端(键合引线、焊接区(land)、内引线)进行连接的方法之一。这种接线键合连接系统使用多个由金(Au)等金属细接线(例如，30μmΦ)形成的键合接线将与半导体芯片主表面上形成的集成电路电连接的键合焊盘(电极焊盘、金属焊盘)与其上安装有半导体芯片的衬底主表面上形成的多个连接端分别电连接。
在这种半导体器件的制造期间，在组装过程(安装过程，后处理)之前，通常对半导体芯片主表面上形成的集成电路的基本功能等进行检查(P检查、探测)。这种检查通常在晶片状态下利用探针同时接触多个键合焊盘，以测量半导体芯片主面上形成的集成电路的各种电学特性。为此测量，使用探针卡，在其中事先按照半导体芯片上所有键合焊盘的部署而布置了大量探针。探针卡电连接至测试器，并且从探针卡输出与所有探针相对应的信号。
键合焊盘有时会在将探针与键合焊盘接触时被损坏，并且构成键合焊盘的金属膜(例如，铝(Al)膜)可能因此剥落。在接线键合连接中，重点在于适当地形成构成键合焊盘的金属膜与构成键合接线尖端处金属球的金属的合金，以增强接合强度。然而，当由于探针接触而使构成键合焊盘的金属膜剥落时，用以形成合金的区域变得较小，并且有可能降低键合焊盘与金属球之间的接合可靠性。因此，近年来，使用了一种连接未被探针损坏的区域中的键合接线的方法，该方法是通过将一个键合焊盘的表面区域划分为结合键合接线的区域(接线键合区域)以及与探针进行接触的区域(探针区域)。
图16A和图16B示出了本发明人已经考察的键合焊盘的一个示例。图16A是键合焊盘的主要部分的平面图，图16B是沿图16A中的线A-A’取得的主要部分的放大剖面图。尽管图16A示出了两个键合焊盘作为示例，但是实际上在一个半导体芯片中实际上例如形成有约300个键合焊盘。
如图16A和图16B所示，键合焊盘B1包含金属膜作为主材料，该金属膜包含铝膜，其厚度约为0.85μm，并且具有例如第一方向上尺度为60μm、与第一方向垂直的第二方向上尺度为125μm的矩形形状。相邻键合焊盘B1之间的距离例如为5μm。每个键合焊盘B 1的表面区域被划分为：将与键合接线尖端的金属球结合的接线键合区域B1w，以及将与探针相接触的探针区域B1p。
每个键合焊盘B1的外围覆盖有保护膜(钝化膜)51。保护膜51由例如厚度为0.2μm的氧化硅膜51a和厚度为0.6μm的氮化硅膜51b的层压膜形成。蔓延在键合焊盘B1外围上并且覆盖键合焊盘B1外围的保护膜51具有例如2.5μm的宽度。厚度例如为0.075μm的氮化钛(TiN)膜52形成于保护膜51与键合焊盘B1之间，它是为了消晕而提供的膜，并且在处理构成键合焊盘B1的金属膜时充当光刻过程中的防反射膜。
然而，对于图16A和图16B中所示的具有彼此区别的接线键合区域B1w和探针区域B1p的键合焊盘B1，存在以下描述的各种技术问题。换言之，显然，当键合接线尖端处的金属球在键合焊盘B1的外围上蔓延同时金属球与键合焊盘B1的接线键合区域B1w结合时，由于应用了超声波，部分保护膜51将会断裂。图17示出了保护膜51中的断裂53的一个示例。断裂53主要产生在键合焊盘B1端部的侧面中，以及产生在由金属球54覆盖的部分中。此外，断裂53还可能导致故障的产生，诸如部分保护膜51剥落。
当这种故障产生时，潮气容易进入到键合焊盘B1中，例如，在作为半导体产品的防潮性测试之一的HAST(强加速温度和湿度应力测试，测试条件为85℃/85％/偏压)期间进入。由于进入相邻键合焊盘B1之间的短路的潮气，相邻键合焊盘B1之间将产生潜在的差异。此外，进入的潮气将使得为消晕而提供并且存留在保护膜51与每个键合焊盘B1之间的氮化钛膜52发生氧化。氮化钛膜52由于氧化而膨胀，并且该膨胀所产生的应力将破坏键合焊盘B1之下的层中的内部布线之间提供的层间绝缘膜，从而导致内部布线间的短路或者键合焊盘B1与内部布线间的短路。诸如键合焊盘B1间的短路、内部布线间的短路或键合焊盘B1与内部布线间的短路等电学故障严重地降低了半导体器件的可靠性。
例如可以通过改变金属球与键合焊盘的键合部分相结合的条件，来防止在保护膜中产生断裂。作为接线键合的接合条件的一个示例，存在这样的技术，其通过由超声波产生的振动来利用金属球摩擦键合焊盘，同时例如在约230度的温度下施加约120mN的恒定负载。重要的是在这种条件下执行接线键合连接，以适当地形成构成键合焊盘的金属膜与构成金属球的金属的合金，从而强化接合强度；并且在没有周密考虑的情况下，难以修改接合条件(例如，温度、负载、施加超声波的时间段等)。
还可以通过使金属球的直径较小从而不让金属球在键合焊盘的外围之上蔓延，来防止在保护膜中产生断裂。然而，用以形成构成键合焊盘的金属膜与构成金属球的金属的合金的区域变得较小，并且可能降低键合焊盘与金属球的接合可靠性。
还可以通过扩大键合焊盘的面积从而不让金属球在键合焊盘的外围之上蔓延，来防止在保护膜中产生断裂。然而，在不改变相邻键合焊盘之间距离的情况下扩大键合焊盘的面积时，键合焊盘所占据的区域增大，因此这继而需要扩大半导体芯片的尺寸。尽管一种通过缩窄相邻键合焊盘之间尺度的方法也可以被认为是扩大键合焊盘的面积，但是当考虑到处理精度等时，难以从目前的状态(约5μm)进一步缩窄尺度。
还可以通过使与键合焊盘外围交叠的保护膜的宽度变宽，来防止在保护膜中产生断裂。然而，随着与键合焊盘外围交叠的保护膜的宽度变宽，探针区域的面积减小，并且探针与保护膜接触并且保护膜被探针损坏的可能性较高。
还可以通过使用保护膜不与键合焊盘外围交叠的结构，来防止在保护膜中产生断裂。然而，由于在形成保护膜之后在键合焊盘之上的保护膜中形成开口时，键合焊盘被用作刻蚀停止膜，因此不可能采用保护膜不与键合焊盘外围交叠的结构。在通过形成布线和最上层的保护膜并且在保护膜中形成开口而暴露出最上层的部分布线之后，可以形成通过该开口与最上层的布线电连接的键合焊盘，以采用保护膜不与键合焊盘外围交叠的结构。然而，由于最上层的布线和键合焊盘是利用彼此不同的层中的金属膜形成的，因此步骤数目、材料成本等有所增加，从而产生了半导体器件的制造成本增加这一问题。
本发明是鉴于上述情况而做出的，并且提供了一种可以通过防止半导体器件的最上层保护膜中的断裂来改进半导体器件可靠性的技术。
通过本说明书和附图，本发明的其他目的和新颖特征将变得易见。
在这里公开的本发明的实施方式中，主要描述以下的一个代表性实施方式。
该实施方式是一种半导体器件，包括安装于其上的四边形半导体芯片，该半导体芯片具有主表面以及与主表面相对的背表面，在主面中布置有多个键合焊盘，每个键合焊盘均为矩形形状，并被分割为键合区域和探针区域。该半导体芯片在每个键合焊盘的较高层中具有保护膜，并且该保护膜覆盖每个键合焊盘的外围，并且具有开口以暴露每个键合焊盘的上表面。此外，保护膜与每个键合焊盘的外围在键合区域中的交叠宽度宽于保护膜与每个键合焊盘的外围在探针区域中的交叠宽度。
该实施方式还是一种半导体器件，包括安装于其上的四边形半导体芯片，该半导体芯片具有主表面以及主表面相对的背表面，其中在主表面上布置有多个凸形的键合焊盘，其分割为键合区域和探针区域。该半导体芯片在每个键合焊盘的较高层中具有保护膜，并且该保护膜覆盖每个键合焊盘的外围，并且具有开口以暴露每个键合焊盘的上表面。此外，保护膜与每个键合焊盘的外围在键合区域中的交叠宽度宽于保护膜与每个键合焊盘的外围在探针区域中的交叠宽度，并且各键合焊盘在键合焊盘的纵向上沿着半导体芯片的侧彼此交替地交错，并且在反向上交替布置凸形形状。
该实施方式还是一种半导体器件，包括安装于其上的半导体芯片，该半导体芯片具有四边形电源键合焊盘，其被分割为键合区域和探针区域。该电源键合焊盘具有上表面，该上表面的部分由电源键合焊盘的较高层中形成的保护膜中的两个开口横跨键合区域和探针区域而暴露出来，并且电源键合焊盘的键合区域和探针区域分别从这两个开口暴露出来，并且该电源键合焊盘仅在两个开口之间的键合区域中具有狭缝。保护膜形成为覆盖电源键合焊盘的外围，并且两个开口按照以下方式来形成，即保护膜与每个键合焊盘的外围在键合区域中的交叠宽度宽于保护膜与每个键合焊盘的外围在探针区域中的交叠宽度。
在这里公开的本发明的实施方式中，下面将主要描述代表性发明的实施方式所取得的效果。
可以防止半导体器件的最上层的保护膜中的断裂，并且改进半导体器件的可靠性。
附图说明
图1是示出了按照第一实施方式的使用接线键合连接的BGA半导体器件的配置的平面图；
图2是示出了按照第一实施方式的使用接线键合连接的BGA半导体器件配置的剖面图；
图3是示出了按照第一实施方式的键合焊盘的主要部分的放大平面图；
图4是示出了按照第一实施方式的键合焊盘的主要部分的部分放大的剖面图(沿图3中的线I-I’取得的剖面图)；
图5A和图5B是分别示出了按照第一实施方式的使用倒装芯片连接的BGA半导体器件的配置的平面图和部分放大剖面图；
图6是示出了按照第一实施方式的使用倒装芯片连接的BGA半导体器件的配置的剖面图；
图7是示出了按照第二实施方式的键合焊盘的主要部分的放大平面图；
图8是示出按照第二实施方式的键合焊盘的主要部分的部分放大剖面图(沿图7中的线II-II’取得的剖面图)；
图9是示出按照第三实施方式的键合焊盘的主要部分的放大平面图；
图10是示出按照第三实施方式的键合焊盘的主要部分的部分放大剖面图(沿图9中的线III-III’取得的剖面图)；
图11是示出本发明人已经考察的电源键合焊盘的主要部分的放大平面图；
图12是示出本发明人已经考察的电源键合焊盘的主要部分的部分放大剖面图(沿图11中的线B-B’取得的剖面图)；
图13是示出按照第四实施方式的电源键合焊盘的主要部分的放大平面图；
图14是示出按照第四实施方式的电源键合焊盘的主要部分的部分放大剖面图(沿图13中的线IV-IV’取得的剖面图)；
图15是示出按照第四实施方式的电源键合焊盘的修改的主要部分的部分放大剖面图；
图16A是示出本发明人已经考察的键合焊盘的主要部分的放大平面图；图16B是沿图16A中的线A-A’取得的键合焊盘的主要部分的放大剖面图；以及
图17是示出保护膜中的断裂的一个示例的键合焊盘的主要部分的剖面图。
具体实施方式
将阐释下文的实施方式，为方便起见，其将会被划分为多个部分或者实施方式。除了特别明确示出的情况之外，这些部分或实施方式并非彼此无关，并且一个部分或实施方式与其它或者所有部分或实施方式的关系可以是诸如修改、详述和补充说明。
在下面的实施方式中，当提及元件的数目等时(包括数目、数值、数量、范围等)，除了特别明确指定的情况以及这些数目在理论上明显限于特定数目的情况之外，其并不限于特定的数目，而是可以大于或者小于特定的数目。此外，在下面的实施方式中，元件(包括要素步骤等)显然未必是不可或缺的，除非特别明确地指定或者从理论的角度考虑其为明显不可或缺的情况等。类似地，在下面的实施方式中，当提及元件等的形状、位置关系等时，应当包括与该形状基本上相近或类似的形状，除非特别地明确指定以及从理论的角度看其明显不正确的情况。这一声明同样适用于上面所述的数值和范围。
在下面实施方式中使用的附图中，为了更好的附图可视化，即使是平面图也可能绘有剖面线。在下面的实施方式，尽管晶片主要指代单晶Si(硅)芯片，但是并不限制于此，而是还可以指代SOI(绝缘体上硅)晶片、用以在其上形成集成电路的绝缘膜衬底等。形状不仅可以是圆形或者近似圆形，而且还可以包括正方形形状、矩形形状等。
而且，在为了说明下面的实施方式的所有附图中，基本上为具有等同功能的那些元素指派了相同的标号或者文字，以省略对它们的重复描述。下面将基于附图给出对本发明实施方式的详细描述。
(第一实施方式)
将使用图1到图4来描述采用按照第一实施方式的接线键合连接的面向上的键合结构的BGA(球栅阵列)半导体器件。图1是示出使用接线键合连接的BGA半导体器件的配置的平面图，图2是示出使用接线键合连接的BGA半导体器件的剖面图，图3是示出键合焊盘的主要部分的放大平面图，并且图4是示出键合焊盘的主要部分的部分放大的剖面图(沿图3中的线I-I’取得的剖面图)。
如图1和图2所示，半导体器件1具有封装结构，其中，在布线衬底2的彼此相对定位的主表面2x和背表面2y之外，半导体芯片3安装在主表面2x上方，并且在布线衬底2的背表面2y上方布置有多个焊料球4以作为与外部的连接端，当然，结构不限于此。
半导体芯片3以粘贴形式或者以类似于DAF(管芯附接膜)的膜形状通过粘合而安装在布线衬底2的主表面2x上方，并且半导体芯片3在与厚度方向相交的平面上具有四边形形状。多个键合焊盘BP1的一行沿半导体芯片3的主表面的每侧(外围)布置。核心区域3b形成在提供有键合焊盘BP1的区域(焊盘区域)3a的内侧，并且在其中形成有诸如CPU(中央处理单元)、DSP(数字信号处理)、RAM(随机访问存储器)、PLL(锁相环路)以及DLL(延迟锁相环路)的集成电路。
键合焊盘BP1由半导体芯片3的多层布线层(在多层布线层中，多个绝缘膜和多个布线层彼此叠置)中的最上层中的布线组成。在每个键合焊盘BP1的较高层中形成保护膜5，从而覆盖多层布线层，并且每个键合焊盘BP1的部分上表面通过在保护层5中形成的开口6而暴露出来。
布线衬底2例如是积层(build up)衬底，并且在与厚度方向相交的平面上具有四边形形状。布线衬底2主要配置为具有核心材料、为了覆盖核心材料的主表面而形成的主表面保护膜、以及为了覆盖定位在核心材料主表面相对侧的背表面而形成的背表面保护膜。核心材料例如具有多层布线结构，其在主表面、背表面和内部具有布线。
多个键合引线7中的一行在布线衬底2的主表面2x上方、沿着布线衬底2的每一侧，布置在半导体芯片3的外围端与布线衬底2的外围端之间的区域中。键合引线7由布线衬底2的核心材料中形成的最上层的布线形成，并且每个键合引线7具有通过主表面保护膜中形成的开口而暴露出来的上表面。多个背表面电极焊盘8布置在布线衬底2的背表面2y上方。背表面电极焊盘8由布线衬底2的核心材料中形成的最上层的布线形成，并且每个背表面电极焊盘8的下表面由在背表面保护膜中形成的开口暴露出来。核心材料中形成的最上层布线由在穿透核心材料的多个通孔内形成的布线分别电耦合至最下层的布线。
布置在半导体芯片3的主表面上方的键合焊盘BP1由多个键合接线9W分别电耦合至布置在布线衬底2主面上方的键合引线7。例如，约20μmΦ到30μmΦ的金线被用于键合接线9W。为了接线键合连接，例如可以使用钉头键合(球键合)技术，其中超声波振动与热压一起使用。半导体芯片3和键合引线9W由形成在布线衬底2主表面上方的树脂密封材料10密封。树脂密封材料10例如包含绝缘树脂，诸如环氧树脂。
如图3所示，每个键合焊盘BP1为矩形形状，并且在沿半导体芯片各个侧部的方向上具有短边，而在与半导体芯片3的侧部相交的方向上具有长边。而且，键合焊盘BP1的表面区域沿着长边(纵向)被划分为用于结合相应键合接线的区域(接线键合区域)BP1w和将与检查探针相接触的区域(探针区域)BP1p。这里，对于接线键合区域BP1w和探针区域BP1p的布置，每个键合焊盘BP1期望按照这样的方式来布置，即接线键合区域BP1w较为靠近半导体芯片的相应侧。与将探针区域BP1p布置为较为靠近半导体芯片侧部的情况相比，通过将接线键合区域BP1w布置为较为靠近半导体芯片的侧部，可以使对键合焊盘BP1与布线衬底主表面上形成的相应键合引线7进行电耦合的相应键合接线的长度较短，并且可以使键合焊盘BP1与键合引线7之间的电感较小。
键合焊盘BP1由包含例如铝膜作为主要材料的金属膜构成，并且具有例如约0.85μm的厚度。在与沿半导体芯片的侧部布置的相邻键合焊盘BP1的节距P1为例如65μm的情况下，例如可以按照这样的方式来示出键合焊盘BP1的尺度的一个示例，即，一个纵边为120μm，一个横边为60μm，并且相邻键合焊盘BP1之间的距离为5μm。
由于键合焊盘BP1可以具有不使接线键合区域BP1w与探针区域BP1p交叠的近似宽度，因此探针区域BP1p的面积和接线键合区域BP1w的面积可以相同。然而，在第一实施方式中，在键合焊盘BP1的纵向，将探针区域BP1p的尺度设置为长于接线键合区域BP1w的尺度，以便拓宽探针区域BP1p。例如，如图3所示，接线键合区域BP1w在键合焊盘BP1中的纵向尺度为50μm，而探针区域BP1p在键合焊盘BP1中的纵向尺度例如为62.5μm。
每个键合焊盘BP 1包含半导体芯片的多层布线层中的最上层的布线，并且由保护膜5中对应于各键合焊盘BP1而形成的每个开口6暴露出来，其中保护膜是为了覆盖多层布线层而形成的。
如图4所示，保护膜5形成于每个键合焊盘BP1上方，并且包含沉积于其上的例如氧化硅膜5a和氮化硅膜5b的层压膜。氧化硅膜5a例如通过等离子CVD(化学气相沉积)方法形成，并且具有例如约0.2μm的厚度。氮化硅膜5b例如通过等离子CVD方法形成，并且具有例如约0.6μm的厚度。通过等离子CVD方法形成的氮化硅膜5b具有防止潮气从外部进入的功能。
防反射膜11位于键合焊盘BP1的上表面与保护膜5之间。防反射膜11是为了在通过光刻和刻蚀来形成键合焊盘BP1时的光刻过程期间防止晕光而提供的膜。也即，当在晶片的整个表面上方形成了金属膜(例如，铝膜)和防反射膜之后，通过利用光刻和刻蚀来处理金属膜和防反射膜，来形成键合焊盘BP1(同时还形成了最上层的布线)。随后，当在晶片的整个表面上方形成保护膜5之后，通过光刻和刻蚀在保护膜5中形成开口6，其暴露出键合焊盘BP1的上表面。此时，没有移除保护膜5之下的防反射膜11，使得防反射膜11保留在键合焊盘BP1的上表面与保护膜5之间。防反射膜11例如由氮化钛膜形成，并且例如具有约0.075μm的厚度。
在键合焊盘BP1上方提供保护膜5中形成的开口6。这是因为，当在键合焊盘BP1上方形成的保护膜5中形成开口6时，键合焊盘BP1被用作刻蚀保护膜5的停止膜。因此，保护膜5以预定的宽度交叠在键合焊盘BP1的外围上，并且键合焊盘BP1的外围覆盖有保护膜5。
在按照第一实施方式的每个键合焊盘BP1中，与键合焊盘BP1的外围交叠的保护膜5的宽度在接线键合区域BP1w中与在探针区域BP1p中有所不同，并且凸形的开口6以如下方式来形成，即，交叠在接线键合区域BP1w中的保护膜5的宽度比交叠在探针区域BP1p中的保护膜5的宽度要宽。作为示例，保护膜5在接线键合区域BP1w中的交叠宽度可以被示为例如5μm，而在探针区域BP1p中的交叠宽度例如为2.5μm。因此，开口6在接线键合区域BP1w中的横向尺度例如为50μm，而在探针区域BP1p中的横向尺度例如为55μm。
在具有上述尺度的键合焊盘BP1的情况下，对于直径为例如30μm的键合接线来说，金属球在其尖端的直径例如变为约40μm，并且只要金属球只在接线键合区域BP1w的中心结合，则金属球不会在键合焊盘BP1的外围与保护膜5相交叠的部分上蔓延。然而，在实际的接线键合过程中，难以按照金属球不在键合焊盘BP1的外围与保护膜5相交叠的部分上蔓延的方式来执行接线键合。
下面给出对原因的解释。在接线键合过程中使用的接线键合装置通过将超声波振动与热压一起使用来执行接线键合。接线键合装置利用键合接线来连接半导体芯片中提供的键合焊盘与布线衬底中提供的相应键合引线。在连接接线的步骤中，首先，在预定键合焊盘的接线键合区域上方降下毛细管，从而将金属球压力键合在键合接线的尖端处。此时，在例如约在230℃施加热量的同时，一起使用超声波振动。负载例如约为120mN。随后，将毛细管提升到预定高度，以便将毛细管移动到环路中的相应键合引线。通过在键合引线上方对毛细管施压，轻微地坍塌键合接线，并且通过提升将键合接线从毛细管分离。针对按行布置的键合焊盘的接线键合区域以及对应于接线键合区域的相应键合引线，顺序地执行这些步骤。利用键合接线来连接键合焊盘之一的接线键合区域与键合引线之一的时间段通常快至0.1秒或更短。在通过接线键合装置来连接接线的步骤中，存在各种因素将会导致金属球偏离接线键合区域的中心。
为了自动执行连接接线的步骤，事先向接线键合装置输入半导体芯片的键合焊盘以及布线衬底的键合引线的位置坐标，并且该装置将该数据保持在内部。尽管位置坐标通常是使用接线键合装置中提供的照相机通过图像识别来输入的，但是人可以确定输入图像是否良好，并且操作接线键合装置，从而使得识别误差的发生是不可避免的。进行键合的半导体芯片和布线衬底被设置在接线键合装置的基平台中所提供的XYθ台上，并且由于XYθ台在键合的同时多次重复快速移动，因此XYθ台的移动停止也会发生误差。尽管金属球由经由毛细管施加的负载和超声波来坍塌，但是坍塌之后球的直径也存在几μm量级的变化。此外，由于近年来半导体器件尺寸减小的趋势而使半导体芯片在尺寸上变得较小，键合焊盘也具有尺寸变小的趋势，使得这种键合焊盘的边缘与这种金属球的周边之间的空隙只剩下约几μm。
也就是说，由于图像识别误差的增长因素、XYθ台的移动停止误差、球直径的变化、键合焊盘的边缘与相应金属球的外部周边之间的空隙的减小以及其他原因，很多金属球转而在相应键合焊盘的外围与保护膜相交叠的部分上蔓延。
然而，如第一实施方式中，通过确保键合焊盘BP1的外围与保护膜5的交叠的较宽的宽度(例如，5μm)，改进了键合焊盘BP1的外围与保护膜5相交叠的部分中的强度，并且即使是在金属球在交叠部分之上蔓延时，也可以防止保护膜5中的断裂。对于在金属球与键合焊盘BP1之间良好形成合金层并且不出现接合问题来说，通过使金属球较小，键合焊盘BP1的外围与保护膜5在接线键合区域BP1w中的交叠宽度也可以变宽。这可以进一步降低保护膜5中断裂的风险。根据本发明人的考察结果，确定的是只要键合焊盘BP1的外围与保护膜5的交叠宽度为5μm，保护膜5便不会断裂，即使是在金属球在键合焊盘BP1的外围与保护膜5相交叠的部分上蔓延时也是如此。
另一方面，只要在半导体芯片检查过程期间探针只与探针区域BP1p的中心接触，则探针不会与键合焊盘BP1的外围与保护膜5相交叠的部分接触，即使在暴露出探针区域BP1p中的键合焊盘BP1的开口6的面积较小时也是如此。然而，在实际的半导体芯片检查过程中，难以使探针只接触探针区域BP1p的中心。
下面给出对原因的解释。例如，在通过切割将晶片分割为个体片之前，在晶片级中通过测试器来检查半导体芯片。使用探针卡将测试器耦合至半导体芯片以用于检查。探针卡的一面具有多个探针，并且其分别与半导体芯片中提供的键合焊盘的探针区域接触。继而，测试器通过探针来测量在半导体芯片的主表面上方形成的集成电路的电学特性。该检查同时针对多个半导体芯片(例如，对齐为4×8的半导体芯片)来进行，并且1000到2000个探针同时接触相应的键合焊盘。因此，探针经常偏离键合焊盘的探针区域的中心，并且在考虑未对准量的情况下，无法使暴露出探针区域的键合焊盘的开口的面积较小。
然而，如第一实施方式中，通过将键合焊盘BP1的外围与保护膜5在探针区域BP1p中的交叠宽度确定为较窄(例如，2.5μm)，来确保暴露出每个键合焊盘BP1的上表面的每个开口6的面积。当键合焊盘BP1的外围与保护膜5在探针区域BP1p中的交叠宽度更窄时，探针在键合焊盘BP1的外围处与保护膜5接触的风险也将变低。然而，在这种情况下，由于在保护膜5中形成开口6时键合焊盘BP1与开口6之间的未对准，在刻蚀保护膜5的同时，在低于键合焊盘BP1的层中形成的、键合焊盘BP1外围中的层间绝缘膜也可能被刻蚀。根据本发明人的考察结果，可以确认，只要键合焊盘BP1外围与保护膜5的交叠宽度为2.5μm，便不会发生工艺故障。
如刚刚所述，按照第一实施方式，键合焊盘BP1形成为矩形，并且按照以下方式在各个键合焊盘BP1上方的保护膜5中形成开口，即，接线键合区域BP1w中的保护膜5与键合焊盘BP1的交叠宽度变得比探针区域BP1p中的保护膜5与键合焊盘BP1的交叠宽度要宽。这能够防止键合焊盘BP1的接线键合区域BP1w中的保护膜5断裂，即使在金属球与接线键合区域BP1w结合的同时在键合焊盘BP1的外围上蔓延时也是如此。而且，在键合焊盘BP1的探针区域BP1p中暴露出键合焊盘BP1的开口6可以宽到探针不接触与键合焊盘BP1外围相交叠的保护膜5。前者允许防止潮气通过断裂进入键合焊盘BP1(因为没有产生断裂)，并且防止了诸如键合焊盘BP1之间的短路、内部布线之间的短路或者键合焊盘BP1与内部布线之间短路之类的电学故障。后者允许防止由于探针与保护膜5的接触而引起的保护膜5的损坏。
尽管上文描述是针对将本发明应用于采用接线键合连接的BGA半导体器件的情况而给出的，但是本发明不限于此。例如，本发明也可以应用于采用倒装芯片连接的半导体器件，其中半导体芯片与布线衬底通过焊块电极来连接。
使用图5A、图5B和图6来描述采用倒装芯片连接的面向下键合结构的BGA半导体器件。图5A和图5B是分别示出使用倒装芯片连接的BGA半导体器件的配置的平面图和部分放大剖面图，图6是示出使用倒装芯片连接的BGA半导体器件的配置的剖面图。尽管在图5A和图5B中示出了在其上形成键合焊盘的半导体芯片的主表面以描述键合焊盘的布置，但是半导体芯片的主表面实际上面对图6中所示的布线衬底的主表面。
如图5A、图5B和图6所示，键合焊盘BP1和开口6的形状与上文使用图3和图4描述的那些一样。也即，每个键合焊盘BP1是矩形形状，并且在沿半导体芯片3的各侧的方向上具有短边，而在沿与半导体芯片3的侧部相交的方向上具有长边。而且，一个键合焊盘BP 1的表面区域被纵向分为与焊块9B连接的焊块键合区域(与图3中所示的接线键合区域BP1w相同的区域)以及探针区域(与图3中所示的探针区域BP1p相同的区域)。与键合焊盘BP1外围相交叠的保护膜5的宽度在焊块键合区域中与在探针区域中不同，并且以如下方式形成凸形的开口6，即保护膜5在焊块键合区域中的交叠宽度比保护膜5在探针区域中的交叠宽度要宽。
在采用这种倒装芯片连接的面向下键合结构的情况下，每个键合焊盘BP1可以按照以下方式来布置，即焊块键合区域距核心区域3b比距半导体芯片3的各侧更靠近(按照探针区域距侧部比距半导体芯片3的核心区域3b更靠近的方式)。与将探针区域布置为较为靠近半导体芯片3的核心区域3b相比，通过将焊块键合区域布置为较为靠近半导体芯片3的核心区域3b，可以使对键合焊盘BP1与核心区域3b中形成的集成电路进行电耦合的相应电路布线的长度较短，并且可以使产生自电路布线的电感较小。
尽管第一实施方式中所描述的特性是通过应用于BGA封装的情况来示例说明的，但是本发明不限于此，而是可以适用于其他封装，诸如QFP(四方扁平封装)、SOP(小外型封装)和CSP(芯片尺寸封装)。
(第二实施方式)
第二实施方式是对按照第一实施方式的键合焊盘BP1的修改，并且在键合焊盘和开口的形状以及键合焊盘的布置方面不同于第一实施方式。使用图7和图8给出对按照第二实施方式的键合焊盘的形状和布置的描述。图7是示出键合焊盘的主要部分的放大平面图，图8是示出键合焊盘的主要部分的部分放大剖面图(沿图7中的线II-II’取得的剖面图)。
如图7和图8所示，类似于第一实施方式，一个键合焊盘BP2的表面区域被分为接线键合区域BP2w和探针区域BP2p。然而，不同于第一实施方式，接线键合区域BP2w中沿半导体芯片各侧的长度(LB)被形成为长于探针区域BP2p中沿半导体芯片侧部的长度(LP)，并且键合焊盘BP2具有凸形。此外，每个键合焊盘BP2按照接线键合区域BP2w靠近半导体芯片侧、靠近核心区域、靠近半导体芯片侧、以此类推的方式，在键合焊盘BP2的纵向上沿半导体芯片的侧部彼此交替地交错布置(按照锯齿形)，并且交替反向地布置为凸形。
在与半导体芯片的侧部相交的方向上(纵向)，键合焊盘BP2的尺度可以与按照第一实施方式的键合焊盘BP1相同，并且键合焊盘BP2的尺度例如可以通过以下方式来说明，即一个长边是120μm，接线键合区域BP2w中键合焊盘BP2的纵向尺度例如为50μm，并且探针区域BP2p中键合焊盘BP2的纵向尺度例如为62.5μm。
类似于第一实施方式，在沿着半导体芯片3的侧部以锯齿形布置的相邻键合焊盘BP2之间的节距P2为例如65μm并且相邻键合焊盘BP2之间的最小距离为例如5μm的情况下，键合焊盘BP2沿半导体芯片3的侧部(横向)的尺度例如可以是：接线键合区域BP2w的横向尺度为65μm，并且探针区域BP2p的横向尺度为60μm。由于交替布置的键合焊盘BP2中的接线键合区域BP2w之间的距离S2至少为5μm(这是最小距离)，因此接线键合区域BP2w的横向尺度可以大于上文所述的65μm，如图7中虚线所示。
类似于第一实施方式，每个键合焊盘BP2由保护膜5中对应于各键合焊盘BP2而形成的开口12暴露出来，保护膜5包含半导体芯片的多层布线层的最上层布线，并且是为了覆盖多层布线层而形成的。保护膜5中的开口12在键合焊盘BP2上方提供，并且保护膜5按照预定宽度与键合焊盘BP2的外围相交叠，由此键合焊盘BP2的外围覆盖有保护膜5。
然而，不同于第一实施方式，按照第二实施方式的键合焊盘BP2具有矩形形状的开口12。相应地，与键合焊盘BP2外围相交叠的保护膜5的宽度在接线键合区域BP2w中与在探针区域BP2p中有所不同，并且交叠在接线键合区域BP2w中的保护膜5的宽度变得比交叠在探针区域BP2p中的保护膜5的宽度要宽。开口12的尺度例如可以通过以下方式来说明，一个纵向侧部为112.5μm，而一个横向侧部为55μm。按照键合焊盘BP2和开口12的尺度，交叠在接线键合区域BP2w中的保护膜5的宽度可以是5μm，而交叠在探针区域BP2p中的保护膜5的宽度可以是2.5μm。在键合焊盘BP2在接线键合区域BP2w中的横向尺度大于65μm的情况下，交叠在接线键合区域BP2w中的保护膜5的宽度可以扩大。例如，在键合焊盘BP2在接线键合区域BP2w中的横向尺度为125μm的情况下，在接线键合区域BP2w中可以获得的保护膜5的交叠宽度可以为35μm。
如刚刚所述，按照第二实施方式，每个键合焊盘BP2是凸形，其在接线键合区域BP2w中沿半导体芯片侧部的长度被形成为长于探针区域BP2p中沿半导体芯片侧部的长度，并且在键合焊盘BP2上方的保护膜5中所形成的开口12是矩形形状，由此，交叠在键合焊盘BP2的接线键合区域BP2w中的保护膜5的宽度可以宽于交叠在键合焊盘BP2的探针区域BP2p中的保护膜5的宽度。当按照探针在键合焊盘BP2的探针区域BP2p中在键合焊盘BP2外围上方蔓延时不接触保护膜5这一方式确保开口12的宽度之后，这可以防止保护膜5的断裂，即使在键合接线尖端处金属球在键合焊盘BP2的接线键合区域BP2w中在键合焊盘BP2外围上蔓延时也是如此，从而可以获得类似于第一实施方式的效果。
此外，每个键合焊盘BP2按照布线键合区域BP2w靠近半导体芯片侧、靠近核心区域、靠近半导体芯片侧、以此类推的方式，在键合焊盘BP2的纵向上沿半导体芯片的侧部彼此交替地交错布置(按照锯齿形)，并且在反向上交替地布置凸形。
利用这种布置，确保了各键合焊盘BP2的接线键合区域BP2w之间对应于约一块探针区域BP2p的横向尺度(宽度)的间隔。接线键合区域BP2w的横向尺度可以在确保的间隔中扩大，并且与之关联地，保护膜5的交叠宽度可以扩大，从而进一步改善抗断裂能力。
(第三实施方式)
近年来，如上文图2所示，为了环保和降低导致环境负担的材料，无卤素的部件越来越多地被用于构成用以对其上安装有半导体芯片3的布线衬底2或者半导体芯片3进行密封的树脂密封材料10的树脂部件(树脂材料)。特别地，电子和电气设备的废弃物的收集和回收受到限定，并且包含基于溴的阻燃剂被定义为基本上排除在WEEE(电子电器废弃物)规章的可独立回收废弃物之外。这导致了将无卤素部件用于构成树脂密封材料10的布线衬底2或者树脂部件(树脂材料)的增加的需求。用于布线衬底2的无卤素部件是具有0.09％重量或更小的氯含量、0.09％重量或更小的溴含量以及0.15％重量或更小的氯和溴总量的材料。用于构成树脂密封材料10的树脂部件(树脂材料)的无卤素部件是具有0.09％重量或更小的氯含量、0.09％重量或更小的溴含量以及0.09％重量或更小的氯和溴总量的材料。也就是说，使用这种无卤素部件作为布线衬底2以及构成树脂密封部分10的树脂部件(树脂材料)的情况意味着使用由WEEE规章所限定的材料。
然而，已经发现，在将这种无卤素部件用于封装材料时，例如半导体芯片的表面与树脂部件(树脂材料)之间的附着(粘附)与传统封装材料相比有所下降，导致了潮气进入封装内部，并且由此可能降低半导体器件的防潮性。
下面描述的第三实施方式涉及具有防止保护膜中的断裂产生的效果的键合焊盘，即使在使用无卤素部件时也是如此，其能够确保半导体器件的防潮性。
使用图9和图10来描述按照第三实施方式的键合焊盘的形状。图9是示出键合焊盘的主要部分的平面图，图10是示出键合焊盘主要部分的部分放大剖面图(沿图9中的线III-III’取得的剖面图)。
如图9和图10所示，类似于第一实施方式，每个键合焊盘BP3具有矩形形状，并且一个键合焊盘BP3的表面区域被纵向分为接线键合区域BP3w和探针区域BP3p。
键合焊盘BP3由包含例如铝膜作为主要材料的金属膜构成，并且例如具有约0.85μm的厚度。在沿半导体芯片3各侧布置的相邻键合焊盘BP3之间的节距P3为例如65μm的情况下，键合焊盘BP3的尺度例如可以通过以下方式来说明，即，一个纵向侧部是120μm，一个横向侧部为60μm，并且相邻键合焊盘BP3之间的距离为例如5μm。键合焊盘BP3的接线键合区域BP3w的纵向尺度例如为50μm，而探针区域BP3p的键合焊盘BP3的纵向尺度例如为62.5μm。
每个键合焊盘BP3由半导体芯片的多层布线层中最上层的布线形成，并且由为了覆盖多层布线层而形成的保护膜13中对应于各键合焊盘BP3而形成的开口6暴露出来。
保护膜13具有例如具有第一厚度的第一绝缘膜13a、具有比第一厚度要厚的第二厚度的第二绝缘膜13b以及第三绝缘膜13c的层压结构。然而，在键合焊盘BP3的外围，形成第一绝缘膜13a和第二绝缘膜13b的层压膜，从而覆盖键合焊盘BP3的外围，并且进一步形成第三绝缘膜13c从而覆盖键合焊盘BP3上方的层压膜的端部。第一绝缘膜13a是通过例如等离子CVD形成的、具有例如约0.2μm的第一厚度的氧化硅膜。第二绝缘膜13b是通过例如高密度等离子CVD形成的、具有例如约0.9μm的第二厚度的氧化硅膜。第二绝缘膜13b的厚度不限于此，而是可以是能够填充相邻键合焊盘BP3之间间隙的厚度。由于期望第二绝缘膜13b填充相邻键合焊盘BP3之间的间隙，因此其优选地为具有良好的涂敷性的绝缘膜。第三绝缘膜13c是通过例如等离子CVD形成的、具有厚度例如约为0.6μm的氮化硅膜。第三绝缘膜13c具有防止潮气从外部进入的功能。
通过形成保护膜13以填充相邻键合焊盘BP3之间的间隙，保护膜13本身的抗破损强度提高，并且由此可以抑制由超声波振动引起的保护膜13中的断裂和剥落，即使在采用例如针头键合(其中，在键合焊盘BP3的接线键合区域BP3w中，在将键合接线尖端处的金属球与接线键合区域BP3w结合时，一起使用超声波振动与热压)时也是如此。
当在键合焊盘BP3上方形成第一绝缘膜13a和第二绝缘膜13b的层压膜以及形成层压膜中的开口6a之后，形成第三绝缘膜13c，以形成键合焊盘BP3上方的第三绝缘膜13c中的开口6，以覆盖层压膜的端部，由此，层压膜完全由第三层压膜13c覆盖，从而可以改进半导体芯片的防潮性。
即使在形成第三绝缘膜13c以覆盖由第一绝缘膜13a和第二绝缘膜13b形成的层压膜的情况下，接线键合区域BP3w的面积仍然优选地较大，以便获得金属球与接线键合区域BP3w中的键合焊盘BP3之间的良好接合；并且探针区域BP3p的面积优选地较宽，以便不要使探针与探针区域BP3p中与键合焊盘BP3外围相交叠的保护膜13发生接触。由此，在第三实施方式中，类似于第一实施方式，接线键合区域BP3w中键合焊盘BP3与保护膜13的交叠宽度为5μm，而探针区域BP3p中键合焊盘BP3与保护膜13的交叠宽度为2.5μm。因此，在接线键合区域BP3w中，构成例如保护膜13下部的、由第一绝缘膜13a和第二绝缘膜13b形成的层压膜的交叠宽度为2.5μm，而构成保护膜13上部的第三绝缘膜13c的交叠宽度为5μm；在探针区域BP3p中，构成例如保护膜13下部的、由第一绝缘膜13a和第二绝缘膜13b形成的层压膜的交叠宽度为1.25μm，而构成保护膜13上部的第三绝缘膜13c的交叠宽度为1.25μm。
如刚刚所述，按照第三实施方式，除了使键合焊盘BP3的接线键合区域BP3w中保护膜13的交叠宽度宽于键合焊盘BP3的探针区域BP3p中保护膜13的交叠宽度之外，保护膜13被形成为填充相邻键合焊盘BP3之间的间隙，并且由此可以增加保护膜13本身的抗破损强度。这甚至能够比第一实施方式更多地抑制键合焊盘BP3的接线键合区域BP3w中、保护膜13中的断裂产生，即使当金属球在键合焊盘BP3的外围上蔓延时也是如此。而且，由于除开口6之外的整个区域都可以由具有防止潮气从外部进入功能的第三绝缘膜13c覆盖，因此可以甚至比第一实施方式更多地防止潮气进入。即使是在将无卤素部件用于半导体器件并且例如半导体芯片的表面与树脂部件(树脂材料)之间的附着(粘附)降低并且因此潮气进入的情况下，这也能够确保半导体器件的防潮性。
尽管将第三实施方式描述为修改按照第一实施方式的键合焊盘BP1和开口6的一个示例，但是该修改也可以应用于第二实施方式中所示的键合焊盘BP2和开口12。
(第四实施方式)
第四实施方式描述了能够防止电源键合焊盘中的保护膜产生断裂的电源键合焊盘和开口的形状。
在描述第四实施方式之前，使用图11和图12来简要地描述本发明人已经考察的电源键合焊盘的形状，因为按照第四实施方式的电源键合焊盘的形状被认为更为清楚。图11是示出电源键合焊盘的主要部分的放大平面图，图12是示出电源键合焊盘的主要部分的部分放大剖面图(沿图11中的线B-B’取得的剖面图)。
如图11和图12所示，本发明人已经考察的电源键合焊盘VB具有矩形形状(例如，125μm×120μm)，并且在电源键合焊盘VB的较高层，形成具有两个矩形开口(例如，55μm×115μm)55的保护膜56。从两个开口55的角度考虑，电源键合焊盘VB被分为接线键合区域VBw和探针区域VBp的表面区域暴露出来。然而，在这种形状的电源键合焊盘VB中，由于从两个开口55暴露出来的两个接线键合区域VBw在例如通过超声波振动与热压一起使用的针头键合而与相应键合接线的尖端处金属球结合，因此断裂57不仅可能产生在与保护膜56相交叠的电源键合焊盘VB的外围区域中，而且还可能产生在位于两个开口55之间的保护膜56中。
使用图13和图14来描述按照第四实施方式的电源键合焊盘的形状。图13是示出电源键合焊盘的放大平面图，图14是示出电源键合焊盘的主要部分的部分放大剖面图(沿图13中的线IV-IV’取得的剖面图)。而且，图15示出了按照第四实施方式的电源键合焊盘的修改。
如图13和图14所示，按照第四实施方式的电源键合焊盘VBP1具有与耦合两个第三实施方式中描述的键合焊盘BP3大致相同的形状。然而，在电源键合焊盘VBP1中，尽管一个探针区域BP4p和其他探针区域BP4p彼此连接，但是一个接线键合区域BP4w与其他接线键合区域BP4w没有彼此连接。
也即，在电源键合焊盘VBP1的较高层形成具有两个开口6的保护膜13，开口6暴露出横跨接线键合区域BP4w和探针区域BP4p的、电源键合焊盘VBP1的部分上表面，而且电源键合焊盘VBP1的接线键合区域BP4w和探针区域BP4p分别从两个开口6暴露出来。仅在两个开口6之间的电源键合焊盘VBP1中的接线键合区域BP4w中提供狭缝14。狭缝14的宽度例如为5μm。
例如，在通过采用针头键合(其中一起使用超声波振动和热压的)来将金属球与两个接线键合区域BP4w中的每一个进行结合的情况下，通过如上所述在接线键合区域BP4w之一与其他接线键合区域之间提供狭缝14，超声波振动施加在保护膜13上的应力等可以由于狭缝14的切削而部分缓和，因此可以防止位于两个开口6之间的保护膜13中产生断裂。此外，类似于第一实施方式，通过将接线键合区域BP4W中与电源键合焊盘VBP1交叠的保护膜13的宽度确定为例如5μm，还可以防止在电源键合焊盘VBP1端部的侧壁中产生保护膜13中的断裂。通过将探针区域BP4p中与电源键合焊盘VBP1的外围交叠的保护膜13的宽度确定为例如2.5μm，可以防止探针造成电源键合焊盘VBP1上方保护膜13中的破损。
图15示出了对按照第四实施方式的电源键合焊盘的修改。图15是示出对电源键合焊盘的修改的主要部分的部分放大剖面图。
在上文图14所示的电源键合焊盘VBP1中，一旦在其上通过顺序沉积第一绝缘膜13a和第二绝缘膜13b而形成双层膜以及在该双层膜中形成开口6a之后，在该双层膜上形成第三绝缘膜13c以完全覆盖该双层膜，并且在第三绝缘膜13c中形成开口6。相反，在图15所示的电源键合焊盘VBP2中，当在其上通过顺序沉积第一绝缘膜13a、第二绝缘膜13b以及第三绝缘膜13c而形成三层膜之后，在该三层膜中形成开口6。与制造电源键合焊盘VBP1的情况相比，通过采用该电源键合焊盘VBP2的结构，可以降低制造步骤的数目。
如刚刚所述，按照第四实施方式，通过将电源键合焊盘VBP1的接线键合区域BP4w中的电源键合焊盘VBP1的外围的交叠宽度确定为不会宽到使保护膜13中产生断裂(即使在键合接线尖端处的金属球在电源键和焊盘VBP1的外围上蔓延时)以及进一步在两个接线键合区域BP4w之间提供狭缝14，还可以抑制电源键合焊盘VBP1中两个开口6之间的保护膜13中的断裂的产生。
尽管上文已经基于实施方式对发明人所做的本发明进行了具体描述，但是应当很自然地理解，本发明不限于这些实施方式，而是可以在不脱离实质范围的情况下进行各种修改。
本发明适用于具有安装于其上的半导体芯片的半导体器件，所述半导体芯片具有用于接线键合连接、倒装芯片连接等的键合焊盘。

Claims (19)

1.一种半导体器件，包括安装于其上的四边形半导体芯片，所述半导体芯片具有：
主表面，其中布置有多个键合焊盘，每个键合焊盘为矩形形状，被分为键合区域和探针区域；以及
与所述主表面相对的背表面，
其中：
所述半导体芯片在每个所述键合焊盘的较高层中具有保护膜；
所述保护膜覆盖每个所述键合焊盘的外围，并且具有开口以暴露每个所述键合焊盘的上表面；以及
所述保护膜与每个键合焊盘的外围在所述键合区域中的交叠宽度变得宽于所述保护膜与每个键合焊盘的外围在所述探针区域中的交叠宽度。
2.根据权利要求1所述的半导体器件，其中所述保护膜中的开口具有凸形形状。
3.根据权利要求2所述的半导体器件，进一步包括：
布线衬底，具有：主表面，其中形成有多个键合引线；以及与所述主表面相对的背表面；
焊盘区域，其中所述键合焊盘沿所述半导体芯片的各侧部布置在所述半导体芯片的所述主表面上方；以及
核心区域，其中集成电路形成于所述焊盘区域的内侧，其中：
所述半导体芯片按照所述布线衬底的所述主表面与所述半导体芯片的所述背表面彼此面对的方式安装在所述布线衬底的所述主表面上方；
所述键合焊盘与所述键合引线由键合接线电耦合；以及
所述键合焊盘按照所述键合区域比所述探针区域更为靠近所述半导体芯片的侧部的方式来布置。
4.根据权利要求3所述的半导体器件，其中：
所述键合接线通过超声波振动与热压一起使用的键合技术被分别电耦合至所述键合焊盘。
5.根据权利要求4所述的半导体器件，其中
所述键合接线是金线，以及
所述键合焊盘为包含铝膜作为主要材料的金属膜。
6.根据权利要求5所述的半导体器件，其中
所述保护膜填充在相邻的键合焊盘之间。
7.根据权利要求6所述的半导体器件，其中
所述保护膜包含其中形成有多个绝缘膜的层压膜，以及
在最上层中的绝缘膜为氮化硅膜。
8.根据权利要求7所述的半导体器件，其中
在所述键合区域中所述保护膜与每个键合焊盘的外围的交叠宽度宽于2.5μm。
9.根据权利要求8所述的半导体器件，其中
在所述键合区域中所述保护膜与每个键合焊盘的外围的交叠宽度为5μm，以及
在所述探针区域中所述保护膜与每个键合焊盘的外围的交叠宽度为2.5μm。
10.根据权利要求9所述的半导体器件，其中：
所述保护膜包含具有第一厚度的第一绝缘膜、具有厚于所述第一厚度的第二厚度的在所述第一绝缘膜上方的第二绝缘膜以及在所述第二绝缘膜上方作为最上层的第三绝缘膜；
每个键合焊盘的外围覆盖有包含所述第一绝缘膜和所述第二绝缘膜的层压膜；以及
所述第三绝缘膜进一步覆盖所述键合焊盘上方的所述第一绝缘膜和所述第二绝缘膜的端部。
11.根据权利要求10所述的半导体器件，其中
所述第三绝缘膜与每个所述键合焊盘的交叠宽度为2.5μm。
12.根据权利要求11所述的半导体器件，其中
所述半导体芯片、所述键合接线以及所述布线衬底的所述主表面的一部分由包含绝缘树脂的树脂密封材料密封。
13.根据权利要求12所述的半导体器件，其中
所述布线衬底以及构成所述树脂密封材料的树脂部件由无卤素部件制成。
14.根据权利要求13所述的半导体器件，其中
所述布线衬底的所述背表面提供有焊料球。
15.根据权利要求1所述的半导体器件，进一步包括：
布线衬底，具有其中形成有多个键合引线的主表面；
焊盘区域，其中在所述半导体芯片的所述主表面上方沿所述半导体芯片的各侧部布置有键合焊盘；以及
核心区域，其中集成电路形成于所述焊盘区域的内侧，其中：
所述半导体芯片按照所述布线衬底的所述主表面与所述半导体芯片的所述主表面彼此面对的方式安装在所述布线衬底的所述主表面上方；
所述键合焊盘与所述键合引线通过焊块来电耦合；以及
所述键合焊盘按照所述探针区域比所述键合区域更靠近所述半导体芯片的侧部的方式来布置。
16.根据权利要求15所述的半导体器件，其中
所述集成电路包括CPU、DSP、RAM、PLL和DLL。
17.一种半导体器件，包括安装于其上的四边形半导体芯片，所述半导体芯片具有：主表面，其上布置有多个凸形形状的键合焊盘，所述键合焊盘被分为键合区域和探针区域；以及与所述主表面相对的背表面，其中：
所述半导体芯片在每个所述键合焊盘的较高层中具有保护膜；
所述保护膜覆盖每个所述键合焊盘的外围，并且具有开口以暴露每个所述键合焊盘的上表面；
所述保护膜与每个键合焊盘的外围在所述键合区域中的交叠宽度宽于所述保护膜与每个键合焊盘的外围在所述探针区域中的交叠宽度；以及
各键合焊盘在所述键合焊盘的纵向上沿所述半导体芯片的长侧部彼此交替地交错，并且在反向上交替地布置凸形形状。
18.根据权利要求17所述的半导体器件，其中
所述保护膜中的开口具有矩形形状。
19.一种半导体器件，包括安装于其上的半导体芯片，具有：四边形电源键合焊盘，其被分为键合区域和探针区域，其中：
所述电源键合焊盘具有上表面，所述上表面的一部分由所述电源键合焊盘的较高层中形成的保护膜中的两个开口横跨所述键合区域和所述探针区域而暴露，
所述电源键合焊盘的所述键合区域和所述探针区域分别从所述两个开口暴露；
所述电源键合焊盘仅在所述两个开口之间的所述键合区域中具有狭缝；
所述保护膜形成为覆盖所述电源键合焊盘的外围；以及
所述保护膜与所述电源键合焊盘的外围在所述键合区域中的交叠宽度宽于所述保护膜与所述电源键合焊盘的外围在所述探针区域中的交叠宽度。
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Address after: Tokyo, Japan, Japan

Patentee after: Renesas Electronics Corporation

Address before: Kanagawa

Patentee before: Renesas Electronics Corporation