TWI545764B - Semiconductor device and method for manufacturing the same - Google Patents

Description

Semiconductor device and method of manufacturing semiconductor device

The present invention relates to a semiconductor device and a method of fabricating the same.

Note that in the present specification, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics, and thus the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

A technique of forming a transistor (also referred to as a thin film transistor (TFT)) by using a semiconductor thin film formed on a substrate having an insulating surface has been attracting attention. The transistor is widely used in electronic devices such as an integrated circuit (IC) and an image display device (display device). As a semiconductor thin film which can be applied to a transistor, a germanium-based semiconductor material is well known. As other materials, oxide semiconductors have attracted attention.

For example, a transistor in which an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) is used as an active layer of a transistor is disclosed (see Patent Document 1).

[Patent Document 1] Japanese Patent Application Publication No. 2006-165528

In order to achieve high speed operation of the transistor, low power consumption of the transistor, high collectivization, etc., it is necessary to achieve miniaturization of the transistor.

It is an object of the present invention to provide a structure and a method of fabricating the same that, in order to realize a semiconductor device of higher performance, an on-state characteristic (for example, on-current or field-effect mobility) of a miniaturized transistor is improved. High-speed response and high-speed driving of semiconductor devices.

Further, with the miniaturization of the transistor, there is a concern that the yield in the process is lowered.

One of the objects of the present invention is to provide a transistor having high electrical characteristics even with a micro structure even at a high yield.

Further, one of the objects of the present invention is to achieve high performance, high reliability, and high productivity in a semiconductor device including the transistor.

In a semiconductor device having a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer provided with a sidewall insulating layer are laminated in this order, a source is provided in contact with the oxide semiconductor film and the sidewall insulating layer a pole electrode layer and a drain electrode layer. In the process of the semiconductor device, the conductive film and the interlayer insulating film are laminated so as to cover the oxide semiconductor film, the sidewall insulating layer, and the gate electrode layer, and the interlayer insulating film and the conductive film are cut (polished, polished). The process removes the conductive film on the gate electrode layer to form a source electrode layer and a drain electrode layer. As the cutting (polishing, polishing) method, a chemical mechanical polishing (CMP) method can be suitably used.

Since the etching process using the photoresist mask is not used in the process of removing the conductive film on the gate electrode layer in the process of forming the source electrode layer and the gate electrode layer, precise processing can be accurately performed. Therefore, in the manufacturing process of the semiconductor device, variations in shape and characteristics can be produced with high yield. A transistor having a miniature structure.

Further, it is preferable to provide an insulating film on the gate electrode layer. In the process of removing the conductive film serving as the source electrode layer and the gate electrode layer provided on the insulating film, a part or the entire portion of the insulating film may be removed.

The dopant is introduced into the oxide semiconductor film in a self-aligned manner by using the gate electrode layer as a mask, and the oxide forming region is formed in the oxide semiconductor film with a lower resistance than the channel forming region and contains the doping. Low resistance zone of the dopant. The dopant is an impurity that changes the conductivity of the oxide semiconductor film. As a method of introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

The oxide semiconductor film having a low resistance region sandwiching the channel formation region in the channel length direction has high conduction characteristics (for example, on current and field effect mobility), and is capable of high-speed operation and high-speed response. .

One mode of the structure of the invention disclosed in the present specification is a semiconductor device comprising: an oxide semiconductor film including a channel formation region provided on an oxide insulating film; a gate insulating film on the oxide semiconductor film; gate insulating a stack of a gate electrode layer and an insulating film on the film; a sidewall insulating layer covering a side surface of the gate electrode layer and a side surface of the insulating film; and a side surface of the oxide semiconductor film, the side surface of the gate insulating film, and the sidewall insulating layer The source electrode layer and the drain electrode layer; and the interlayer insulating film on the source electrode layer and the drain electrode layer, wherein the upper surface of the source electrode layer and the drain electrode layer has a lower height than the insulating film and the sidewall insulating layer And the height and height of the upper layer of the interlayer insulating film In the upper surface of the gate electrode layer, and in the oxide semiconductor film, a region including a region overlapping the gate insulating film that does not overlap with the gate electrode layer contains a dopant.

In the above configuration, one embodiment of the structure of the invention disclosed in the present specification is a semiconductor device in which the heights of the upper surfaces of the insulating film, the sidewall insulating layer, and the interlayer insulating film are uniform.

Further, in the oxide semiconductor film, a region not overlapping the source electrode layer or the gate electrode layer may have a higher oxygen concentration than a region overlapping the source electrode layer or the gate electrode layer.

One mode of the structure of the invention disclosed in the present specification is a method of manufacturing a semiconductor device, comprising the steps of: forming an oxide insulating film; forming an oxide semiconductor film on the oxide insulating film; and forming a gate on the oxide semiconductor film An insulating film; a gate electrode layer and an insulating film overlapping the oxide semiconductor film are stacked on the gate insulating film; and the dopant is selectively introduced into the oxide semiconductor film using the gate electrode layer and the insulating film as a mask Forming a sidewall insulating layer covering the side surface of the gate electrode layer and the side surface of the insulating film on the gate insulating film; forming a conductive layer on the oxide semiconductor film, the gate insulating film, the gate electrode layer, the insulating film, and the sidewall insulating layer a film; forming an interlayer insulating film on the conductive film; and forming a source electrode layer and a germanium by chemical mechanical polishing until the insulating film on the gate electrode layer is exposed to remove the interlayer insulating film and the conductive film to separate the conductive film Electrode layer.

In the above structure, a dense insulating inorganic insulating film (typically an aluminum oxide film) serving as a protective insulating film may be provided on the insulating film, the source electrode layer, the gate electrode layer, the sidewall insulating layer, and the interlayer insulating film. ).

In the above configuration, an inorganic insulating film (typically an aluminum oxide film) having high density as a protective insulating film may be provided between the source electrode layer and the gate electrode layer and the interlayer insulating film.

Further, in the process of removing the conductive film on the gate electrode layer, in addition to the cutting (polishing, polishing) method such as chemical mechanical polishing, etching (dry etching, wet etching) or plasma treatment may be combined. For example, dry etching or plasma treatment may be performed after the removal process by the chemical mechanical polishing method to improve the flatness of the treated surface.

In the above configuration, the surface of the oxide insulating film on which the oxide semiconductor film is formed later may be planarized by a planarization process. Thereby, the oxide semiconductor film having a small thickness can be provided with high coverage. As the planarization treatment, a chemical mechanical polishing method, an etching method, a plasma treatment, or the like can be used singly or in combination.

Further, heat treatment (dehydration treatment or dehydrogenation treatment) for releasing hydrogen or moisture from the oxide semiconductor film may be performed. Further, when a crystalline oxide semiconductor film is used as the oxide semiconductor film, heat treatment for crystallization can also be performed.

In addition, oxygen may also be supplied to the oxide semiconductor film. Owing to the dehydration treatment or the dehydrogenation treatment, oxygen which is a main component material constituting the oxide semiconductor may be simultaneously desorbed and reduced. In the oxide semiconductor film, oxygen depletion occurs in a portion where oxygen is removed, and a donor energy level due to fluctuation in electrical characteristics of the transistor occurs due to the oxygen deficiency.

Therefore, it is preferred to supply oxygen to the oxide semiconductor film subjected to the dehydration treatment or the dehydrogenation treatment. By supplying oxygen to the oxide semiconductor film, Fill the oxygen deficiency in the membrane.

For example, oxygen can be supplied from the oxide insulating film to the oxide semiconductor film by providing an oxide insulating film containing a large amount (excess) of oxygen serving as a supply source of oxygen in contact with the oxide semiconductor film. . In the above configuration, the oxide semiconductor film which has been subjected to the heat treatment as the dehydration treatment or the dehydrogenation treatment is subjected to heat treatment in a state in which at least a part of the oxide insulating film is in contact with the oxide insulating film, and oxygen is supplied to the oxide semiconductor film. .

Further, oxygen may be introduced into the oxide semiconductor film subjected to the dehydration treatment or the dehydrogenation treatment (including at least any one of an oxygen radical, an oxygen atom, and an oxygen ion) to supply oxygen to the film. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

Further, it is preferable that the oxide semiconductor film provided in the transistor is a film in which the oxide semiconductor includes a region having an excessive oxygen content as compared with a stoichiometric composition when the oxide semiconductor is in a crystalline state. At this time, the oxygen content exceeds the stoichiometric composition of the oxide semiconductor. Alternatively, the oxygen content exceeds the oxygen content of the single crystal. Oxygen is sometimes present between the crystal lattices of the oxide semiconductor.

By removing hydrogen or moisture from an oxide semiconductor, highly purified without impurities, and supplying oxygen to fill oxygen defects, a type I (essential) oxide semiconductor or an infinitely close type I (essential) oxidation can be realized. Semiconductor. Thereby, the Fermi level (Ef) of the oxide semiconductor can be made to be the same as the essential Fermi level (Ei). Thus, borrow By using this oxide semiconductor film for a transistor, it is possible to reduce the variation of the threshold voltage Vth of the transistor due to the oxygen deficiency and the drift of the threshold voltage ΔVth.

One aspect of the present invention is directed to a semiconductor device having a transistor or a circuit including a transistor. For example, one aspect of the present invention relates to a semiconductor device having a transistor in which a channel formation region is formed of an oxide semiconductor or a circuit including a transistor. For example, the present invention relates to: an LSI; a CPU; a power device mounted in a power supply circuit; a semiconductor integrated circuit including a memory, a thyristor, a converter, and an image sensor; and a liquid crystal display mounted as a component The panel is a representative of an electro-optical device or an electronic device of a light-emitting display device having a light-emitting element.

The present invention can provide a transistor having high electrical characteristics even with a micro structure at a high yield.

Further, in the semiconductor device including the transistor, high performance, high reliability, and high productivity can be achieved.

Hereinafter, embodiments of the invention disclosed in the present specification will be described in detail with reference to the drawings. However, those skilled in the art can easily understand the fact that the manner and details of the invention disclosed in the specification can be changed to various forms without being limited to the following description. In addition, the invention disclosed in the present specification should not be construed as being limited to the contents described in the embodiments described below. In addition, for convenience Ordinal numbers such as "first" and "second" are appended, and do not denote a process sequence or a stacking order. In addition, the ordinal number does not indicate the inherent name of the item used for the specific invention in this specification.

Embodiment 1

In the present embodiment, one embodiment of a semiconductor device and a method of manufacturing a semiconductor device will be described with reference to FIGS. 1A and 1B. In the present embodiment, a transistor having an oxide semiconductor film is shown as an example of a semiconductor device.

The transistor may be of a single gate structure forming a channel formation region, a double-gate structure forming two channel formation regions, or a triple gate structure forming three channel formation regions. Alternatively, it may be a dual-gate type having two gate electrode layers disposed above and below the channel formation region via a gate insulating film.

The transistor 440a shown in Figs. 1A and 1B is an example of a transistor of a top gate structure. 1A is a plan view, and a section cut along a chain line X-Y in FIG. 1A corresponds to FIG. 1B.

As shown in FIG. 1B as a cross-sectional view of the channel length direction, the semiconductor device including the transistor 440a includes a channel formation region 409, a low resistance region 404a, and a substrate 400 having an insulating surface provided with an oxide insulating film 436. 044b oxide semiconductor film 403; source electrode layer 405a; drain electrode layer 405b; gate insulating film 402; gate electrode layer 401; sidewall insulating layers 412a, 412b provided on the side surface of gate electrode layer 401; An insulating film 413 on the gate electrode layer 401; disposed at the source An interlayer insulating film 415 on the electrode layer 405a and the gate electrode layer 405b; and an insulating film 407 covering the transistor 440a.

The interlayer insulating film 415 is provided to planarize the unevenness of the transistor 440a, and the height of the upper surface is substantially the same as the height of the sidewall insulating layers 412a, 412b and the insulating film 413. Further, the heights of the upper surfaces of the source electrode layer 405a and the drain electrode layer 405b are lower than the heights of the upper surfaces of the interlayer insulating film 415, the sidewall insulating layers 412a, 412b, and the insulating film 413 and higher than the upper surface of the gate electrode layer 401. . In addition, here, the height means the height from the upper surface of the substrate 400.

In addition, in FIG. 1A and FIG. 1B, the insulating film 407 is provided in contact with the interlayer insulating film 415, the source electrode layer 405a, the gate electrode layer 405b, the sidewall insulating layers 412a and 412b, and the insulating film 413.

In addition, the dopant is introduced into the oxide semiconductor film 403 in a self-aligned manner using the gate electrode layer 401 as a mask, and the resistance forming channel formation region is formed in the oxide semiconductor film 403 with the channel formation region 409 interposed therebetween. The low resistance region 404a, 404b of 409 is low and contains dopants. The dopant is an impurity that changes the conductivity of the oxide semiconductor film 403. As a method of introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

The oxide semiconductor film 403 having the low resistance regions 404a, 404b sandwiching the channel formation region 409 in the channel length direction has high on-characteristic characteristics (for example, on-current and field-effect mobility) and can High speed work and high speed response.

The oxide semiconductor used for the oxide semiconductor film 403 is preferably at least packaged Contains indium (In) or zinc (Zn). In particular, it is preferred to contain In and Zn. Further, as a stabilizer for reducing variations in electrical characteristics of a transistor using the oxide, gallium (Ga) is preferably contained in addition to the above elements. Further, it is preferable to have tin (Sn) as a stabilizer. Further, it is preferable to have hydrazine (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer. Further, it is preferable to have zirconium (Zr) as a stabilizer.

Further, as other stabilizers, lanthanum (La), cerium (Ce), strontium (Pr), cerium (Nd), strontium (Sm), cerium (Eu), cerium (Gd), cerium (which may have lanthanoid elements) Any one or more of Tb), Dy, Ho, Er, Tm, Yb, and Lu.

For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, an In-Zn-based oxide of a binary metal oxide, an Sn-Zn-based oxide, an Al-Zn-based oxide, or a Zn-Mg can be used. Oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide; ternary metal oxide-in-Ga-Zn-based oxide (also known as IGZO), In-Al-Zn Oxide-like, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In -La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn Oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In- Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn Oxide-like; and In-Sn-Ga-Zn-based oxide of quaternary metal oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al- A Zn-based oxide, an In-Sn-Hf-Zn-based oxide, or an In-Hf-Al-Zn-based oxide.

Note that, for example, the In—Ga—Zn-based oxide refers to an oxide having In, Ga, and Zn as a main component, and the ratio of In, Ga, and Zn is not limited. Further, a metal element other than In, Ga, or Zn may be contained.

Further, as the oxide semiconductor, a material represented by InMO ₃ (ZnO) _m (m>0, and m is not an integer) may be used. Here, M represents a metal element or a plurality of metal elements selected from the group consisting of Ga, Fe, Mn, and Co. Further, as the oxide semiconductor, a material represented by In ₂ SnO ₅ (ZnO) _n (n>0, and n is an integer) may be used.

For example, it is possible to use an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3), In:Ga:Zn=2:2:1 (=2/ 5:2/5:1/5) or In:Ga:Zn=3:1:2 (=1/2:1/6:1/3) of In-Ga-Zn-based oxide or its composition Oxide. Alternatively, it is also possible to use an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1) /3:1/6:1/2) or In:Sn:Zn=2:1:5 (=1/4:1/8:5/8) of In-Sn-Zn-based oxide or its composition Oxide.

However, it is not limited to the above materials, and a material having an appropriate composition can be used depending on the required semiconductor characteristics (mobility, threshold, variation, etc.). Further, in order to obtain desired semiconductor characteristics, it is preferred to appropriately set carrier concentration, impurity concentration, defect density, atomic number of metal elements and oxygen Conditions such as ratio, distance between atoms, density, etc.

For example, higher mobility can be easily obtained using an In-Sn-Zn-based oxide. However, when an In-Ga-Zn-based oxide is used, the mobility can also be improved by reducing the defect density in the bulk.

Here, for example, the composition of an oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=a:b:c(a+b+c=1) is in the atomic ratio of In:Ga:Zn= A: B: The vicinity of the composition of the oxide of C(A+B+C=1) means that a, b, and c satisfy (aA) ² + (bB) ² + (cC) ² The relationship of r ² . r can be, for example, 0.05. The same is true for other oxides.

The oxide semiconductor film 403 is in a state of single crystal, polycrystal, or amorphous.

A preferred oxide semiconductor film is a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film.

The CAAC-OS film is not a complete single crystal, nor is it completely amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure of a crystal portion in an amorphous phase. Further, in many cases, the size of the crystal portion is a size that can be accommodated in a cube shorter than one side of 100 nm. Further, in the image observed by a transmission electron microscope (TEM), the boundary between the amorphous portion and the crystal portion included in the CAAC-OS film is not clear. In addition, no grain boundary was observed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, the decrease in electron mobility due to the grain boundary is suppressed.

The c-axis of the crystal portion included in the CAAC-OS film is uniform in a direction perpendicular to the surface or surface on which the CAAC-OS film is formed, and has an atomic arrangement having a triangular shape or a hexagonal shape when viewed from a direction perpendicular to the ab plane. And layers each having a metal atom and an oxygen atom overlap each other. In addition, the direction of the normal vector of the layer is the c-axis direction. Further, the directions of the a-axis and the b-axis of the different crystal portions may be different from each other. In the present specification, when only "vertical" is described, a range of 85° or more and 95° or less is also included.

Further, in the CAAC-OS film, the distribution of the crystal portion may be uneven. For example, in the formation of the CAAC-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the proportion of the crystal portion in the vicinity of the surface may be higher than in the vicinity of the surface to be formed. Further, by adding an impurity to the CAAC-OS film, the crystal portion may be amorphized in the impurity addition region.

Since the c-axis of the crystal portion included in the CAAC-OS film is uniform in the direction perpendicular to the surface or surface on which the CAAC-OS film is formed, there are cases depending on the shape of the CAAC-OS film (the cross-sectional shape of the formed surface or The cross-sectional shape of the surface) faces different directions from each other. Further, the c-axis direction of the crystal portion is a direction perpendicular to the surface or surface to be formed when the CAAC-OS film is formed. The crystal portion is formed by performing a film formation or a crystallization treatment such as heat treatment after film formation.

A transistor using a CAAC-OS film can reduce variations in electrical characteristics caused by irradiation of visible light or ultraviolet light. Therefore, the reliability of the transistor is high.

Further, a part of oxygen constituting the oxide semiconductor film may also be nitrogen. Replace.

Further, an oxide semiconductor having a crystal portion such as CAAC-OS can further reduce defects in the bulk, and by improving the flatness of the surface, a mobility higher than the mobility of the oxide semiconductor in an amorphous state can be obtained. In order to improve the flatness of the surface, it is preferred to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is preferably 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. An oxide semiconductor is formed on the surface.

Ra means that the arithmetic mean roughness defined in JIS B0601:2001 (ISO4287:1997) is expanded to three dimensions so that it can be applied to a curved surface, and can be obtained by averaging the absolute values of deviations from the reference plane to the designated plane. The value "represents" is defined by the following formula.

Here, the designated face refers to the face that becomes the object of measuring roughness, and is a coordinate ((x ₁ , y ₁ , f(x ₁ , y ₁ ))) (x ₁ , y ₂ , f(x ₁ , y ₂ ) a region of a quadrangle represented by four points of (x ₂ , y ₁ , f(x ₂ , y ₁ )) (x ₂ , y ₂ , f(x ₂ , y ₂ )), a rectangle of a specified plane projected on the xy plane The area is S ₀ , and the height of the reference surface (the average height of the designated surface) is Z ₀ . Ra can be measured by an atomic force microscope (AFM: Atomic Force Microscope).

The thickness of the oxide semiconductor film 403 is set to 1 nm or more and 30 nm or less (preferably 5 nm or more and 10 nm or less), a sputtering method, an MBE (Molecular Beam Epitaxy) method, a CVD method, a pulsed laser deposition method, or an ALD (Atomic Layer Deposition) can be suitably used. Sedimentation method, etc. Further, the oxide semiconductor film 403 can also be formed by using a sputtering apparatus which performs film formation in a state in which a plurality of substrate surfaces are provided substantially perpendicular to the surface of the sputtering target.

The CAAC-OS film is used, for example, as a polycrystalline oxide semiconductor sputtering target, and is formed by a sputtering method. When ions collide with the sputtering target, the crystal region included in the sputtering target may be peeled off from the ab surface, that is, the flat or granular sputtering particles having a surface parallel to the ab surface. At this time, the CAAC-OS film can be formed by the flat sputtered particles remaining in a crystalline state and reaching the substrate.

Further, in order to form a CAAC-OS film, the following conditions are preferably applied.

By reducing the incorporation of impurities during film formation, it is possible to suppress the destruction of the crystal state due to impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the deposition chamber can be reduced. In addition, the concentration of impurities in the film forming gas can be lowered. Specifically, a film forming gas having a dew point of -80 ° C or lower, preferably -100 ° C or lower is used.

Further, by increasing the substrate heating temperature at the time of film formation, migration of sputtered particles occurs after the sputtered particles reach the substrate. Specifically, the film formation temperature is set in a state where the substrate heating temperature is set to 100° C. or higher and 740° C. or lower, preferably 200° C. or higher and 500° C. or lower. By increasing the base of the film formation At the plate heating temperature, when the plate-shaped sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

Further, it is preferable to reduce the plasma damage at the time of film formation by increasing the proportion of oxygen in the film forming gas and optimizing the electric power. The proportion of oxygen in the film forming gas is set to 30 vol.% or more, preferably 100 vol.%.

Hereinafter, an In-Ga-Zn-O compound target is shown as an example of a sputtering target.

The InO _X powder, the GaO _Y powder, and the ZnO _Z powder are mixed at a predetermined molar ratio, subjected to a pressure treatment, and then heat-treated at a temperature of 1000 ° C or higher and 1500 ° C or lower to obtain a poly indium. -Ga-Zn-O compound target. In addition, X, Y and Z are arbitrary positive numbers. Here, the predetermined molar ratio of the InO _X powder, the GaO _Y powder, and the ZnO _Z powder is, for example, 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2 :3 or 3:1:2. Further, the kind of the powder and the molar ratio of the mixture thereof may be appropriately changed depending on the sputtering target to be produced.

2A to 2D and 3A to 3D show an example of a method of manufacturing a semiconductor device having a transistor 440a.

First, an oxide insulating film 436 is formed on a substrate 400 having an insulating surface.

The substrate that can be used for the substrate 400 having an insulating surface is not particularly limited, but the substrate 400 needs to have at least heat resistance capable of withstanding heat treatment performed later. For example, a glass substrate such as bismuth borosilicate glass or aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate or the like can be used. In addition, as the substrate 400, it is also possible to adopt: germanium, carbon A single crystal semiconductor substrate or a polycrystalline semiconductor substrate which is a material such as ruthenium or the like; a compound semiconductor substrate made of ruthenium or the like; or an SOI substrate or the like, and a semiconductor element may be provided on these substrates.

Further, a semiconductor device can be manufactured using the flexible substrate as the substrate 400. When manufacturing a flexible semiconductor device, the transistor 440a including the oxide semiconductor film 403 may be directly formed on the flexible substrate, and the transistor 440a including the oxide semiconductor film 403 may be formed on other fabrication substrates and then It is peeled off from the manufacturing substrate and transferred onto a flexible substrate. Further, in order to peel off from the manufacturing substrate and transfer it onto the flexible substrate, it is preferable to provide a peeling layer between the manufacturing substrate and the transistor 440a having the oxide semiconductor film.

The oxide insulating film 436 can be formed by a plasma CVD method, a sputtering method, or the like using cerium oxide, cerium oxynitride, aluminum oxide, aluminum oxynitride, cerium oxide, gallium oxide, or a mixed material of these materials.

The oxide insulating film 436 may be a single layer or a laminate. For example, a ruthenium oxide film, an In-Hf-Zn-based oxide film, or an oxide semiconductor film 403 may be sequentially laminated on the substrate 400, or a ruthenium oxide film may be sequentially laminated on the substrate 400, and the atomic ratio thereof may be In:Zr. : an In—Zr—Zn-based oxide film or an oxide semiconductor film 403 having Zn=1:1:1, or a tantalum oxide film may be sequentially laminated on the substrate 400, and the atomic ratio thereof is In:Gd:Zn=1: 1:1 In-Gd-Zn-based oxide film or oxide semiconductor film 403.

In the present embodiment, a ruthenium oxide film is formed as a oxide insulating film 436 by a sputtering method.

In addition, it is also possible to provide between the oxide insulating film 436 and the substrate 400. A nitride insulating film is placed. The nitride insulating film can be formed by a plasma CVD method, a sputtering method, or the like using a tantalum nitride, hafnium oxynitride, aluminum nitride, aluminum oxynitride, or a mixed material of these materials.

Next, an oxide semiconductor film 403 is formed over the oxide insulating film 436 (see FIG. 2A).

Since the oxide insulating film 436 is in contact with the oxide semiconductor film 403, it is preferable that at least a stoichiometric amount of oxygen is present in the film (in the block). For example, when a hafnium oxide film is used as the oxide insulating film 436, a film of SiO _2+α (note that α>0) is used. By using such an oxide insulating film 436, oxygen can be supplied to the oxide semiconductor film 403, so that characteristics can be improved. By supplying oxygen to the oxide semiconductor film 403, oxygen deficiency in the film can be filled.

For example, by providing an oxide insulating film 436 containing a large amount (excess) of oxygen serving as a supply source of oxygen in contact with the oxide semiconductor film 403, oxygen can be supplied from the oxide insulating film 436 to the oxide. In the semiconductor film 403. Oxygen may be supplied to the oxide semiconductor film 403 by performing heat treatment in a state where the oxide semiconductor film 403 is in contact with at least a part of the oxide insulating film 436.

In the process of forming the oxide semiconductor film 403, in order to prevent hydrogen or water from being contained in the oxide semiconductor film 403 as much as possible, it is preferable to form a pretreatment in the preheating chamber of the sputtering apparatus as a pretreatment for forming the oxide semiconductor film 403. The substrate having the oxide insulating film 436 is preheated, and impurities such as hydrogen or moisture adhering to the substrate and the oxide insulating film 436 are removed and discharged. Further, as the exhaust unit provided in the preheating chamber, a cryopump is preferably used.

A region formed in the oxide insulating film 436 so as to be in contact with the oxide semiconductor film 403 may be planarized. The planarization treatment is not particularly limited, and a polishing treatment (for example, chemical mechanical polishing), a dry etching treatment, and a plasma treatment may be used.

As the plasma treatment, for example, reverse sputtering in which argon gas is introduced to generate a plasma can be performed. Reverse sputtering refers to a method of applying a voltage to a substrate side under an argon atmosphere using an RF power source to form a plasma in the vicinity of the substrate for surface modification. Further, nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. By performing reverse sputtering, powdery substances (also referred to as fine particles and dust) adhering to the surface of the oxide insulating film 436 can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times, or they may be combined. Further, when these are combined, the order of the process is not particularly limited, and can be appropriately set depending on the unevenness of the surface of the oxide insulating film 436.

As the planarization treatment, for example, the surface of the ruthenium oxide film used as the oxide insulating film 436 can be polished by a chemical mechanical polishing method (polishing conditions: polyurethane-based polishing cloth, silica-based slurry) -based slurry), the slurry temperature is room temperature, the polishing pressure is 0.001 MPa, the number of rotations during polishing (table/spindle) is 60 rpm/56 rpm, and the polishing time is 0.5 minutes), which will oxidize the surface of the ruthenium film. The average surface roughness (Ra) was set to about 0.15 nm.

Further, it is preferred to form a film under conditions in which a large amount of oxygen is contained during film formation (for example, film formation by sputtering in an atmosphere of 100% oxygen). The oxide semiconductor film 403 is a film containing a large amount of oxygen (preferably including a region having an excessive oxygen content as compared with a stoichiometric composition when the oxide semiconductor is in a crystalline state).

In the present embodiment, an oxide target of In:Ga:Zn=3:1:2 [atomic ratio] is used as a target for forming the oxide semiconductor film 403 by a sputtering method. An In-Ga-Zn-based oxide film (IGZO film) was formed.

Further, the relative density (filling ratio) of the metal oxide target is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. A dense oxide semiconductor film can be formed by using a metal oxide target having a high relative density.

As the sputtering gas used in forming the oxide semiconductor film 403, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or a hydride are removed is preferably used.

The substrate is held in a deposition chamber maintained in a reduced pressure state. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while removing residual moisture in the deposition chamber, and an oxide semiconductor film 403 is formed on the substrate 400 using the above target. In order to remove residual moisture in the deposition chamber, it is preferred to use an adsorption type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, as the exhaust unit, a turbo molecular pump to which a cold trap is added may be used. In a deposition chamber using a cryopump for exhausting, for example, a compound containing a hydrogen atom such as a hydrogen atom or water (H ₂ O) (more preferably, a compound containing a carbon atom) is exhausted, The concentration of impurities contained in the oxide semiconductor film 403 formed in the deposition chamber can be lowered.

Further, it is preferable to continuously form the oxide insulating film 436 and the oxide semiconductor film 403 so as not to be exposed to the atmosphere. By continuously forming the oxide insulating film 436 and the oxide semiconductor film 403 without being exposed to the atmosphere, impurities such as hydrogen or moisture can be prevented from adhering to the surface of the oxide insulating film 436.

The oxide semiconductor film 403 can be formed by processing the film-shaped oxide semiconductor film into an island-shaped oxide semiconductor film by photolithography.

Further, a photoresist mask for forming the island-shaped oxide semiconductor film 403 may be formed by an inkjet method. A photomask is not required when the photoresist mask is formed by an inkjet method, whereby the manufacturing cost can be reduced.

In addition, the etching of the oxide semiconductor film may employ one or both of dry etching and wet etching. For example, as an etchant for wet etching of an oxide semiconductor film, a solution in which phosphoric acid, acetic acid, and nitric acid are mixed can be used. Further, ITO-07N (manufactured by Kanto Chemical Co., Ltd., Japan) can also be used. Alternatively, the etching may be performed by dry etching using an ICP (Inductively Coupled Plasma) etching method. For example, the IGZO film can be etched by ICP etching (etching conditions: etching gas (BCl ₃ : Cl ₂ = 60 sccm: 20 sccm), power supply power is 450 W, bias power is 100 W, pressure is 1.9 Pa), and It is processed into an island shape.

Further, the oxide semiconductor film 403 may be subjected to a heat treatment for removing excess hydrogen (including water or a hydroxyl group) (dehydration or dehydrogenation). The temperature of the heat treatment is set to 300 ° C or more and 700 ° C or less, or set to be lower than the strain point of the substrate. Can be under reduced pressure or under nitrogen Wait for heat treatment. For example, the substrate is introduced into an electric furnace of one of the heat treatment apparatuses, and the oxide semiconductor film 403 is heat-treated at 450 ° C for 1 hour in a nitrogen atmosphere.

Further, the heat treatment device is not limited to the electric furnace, and a device that heats the object to be processed by heat conduction or heat radiation generated by a heat generating body such as a resistance heating body may be used. For example, an RTA (Rapid Thermal Anneal) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats a workpiece by using radiation (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high temperature gas. As the high-temperature gas, a rare gas such as argon or an inert gas such as nitrogen which does not react with the object to be treated by heat treatment is used.

For example, as the heat treatment, the GRTA may be placed in an inert gas heated to a high temperature of 650 ° C to 700 ° C, and after heating for a few minutes, the substrate is taken out from the inert gas.

Further, in the heat treatment, nitrogen or a rare gas such as helium, neon or argon preferably does not contain water, hydrogen or the like. Alternatively, it is preferable to set the purity of nitrogen or a rare gas such as helium, neon or argon introduced into the heat treatment apparatus to 6 N (99.9999%) or more, more preferably 7 N (99.999999%) or more (that is, to set the impurity concentration). It is set to 1 ppm or less, preferably set to 0.1 ppm or less.

In addition, it is also possible to heat the oxide semiconductor film by heat treatment. After 403, high-purity oxygen gas, high-purity nitrous oxide gas or ultra-dry air (using a CRDS (cavity ring-down laser spectroscopy) dew point meter) is introduced into the same furnace. The moisture content at the time of measurement is 20 ppm (the dew point is converted to -55 ° C) or less, preferably 1 ppm or less, more preferably 10 ppb or less. The oxygen gas or the nitrous oxide gas preferably does not contain water, hydrogen or the like. Alternatively, the purity of the oxygen gas or the nitrous oxide gas introduced into the heat treatment apparatus is preferably set to 6 N or more, preferably 7 N or more (that is, the impurity concentration in the oxygen gas or the nitrous oxide gas is set. It is 1 ppm or less, preferably set to 0.1 ppm or less. The oxide semiconductor film 403 can be made highly high by supplying oxygen of a main component material constituting the oxide semiconductor which is simultaneously reduced by the dehydration treatment or the dehydrogenation treatment by the action of the oxygen gas or the nitrous oxide gas. Purification and type I (essential).

Further, the heat treatment for dehydration or dehydrogenation may be performed after the formation of the film-like oxide semiconductor film, or the heat treatment for dehydration or dehydrogenation may be performed after the formation of the island-shaped oxide semiconductor film 403.

Further, the heat treatment for dehydration or dehydrogenation may be carried out a plurality of times, or it may be used as another heat treatment.

The heat treatment for dehydration or dehydrogenation is performed in a state where the film-like oxide semiconductor film is processed into an island shape as the oxide semiconductor film 403, that is, in a state where the film-like oxide semiconductor film covers the oxide insulating film 436. It is preferable to prevent the oxygen contained in the oxide insulating film 436 from being released by the heat treatment.

Further, oxygen may be introduced into the oxide semiconductor film 403 subjected to the dehydration treatment or the dehydrogenation treatment (at least one of an oxygen radical, an oxygen atom, and an oxygen ion) to supply oxygen to the film.

Further, due to the dehydration treatment or the dehydrogenation treatment, oxygen which is a main component material constituting the oxide semiconductor may be simultaneously desorbed and reduced. In the oxide semiconductor film, oxygen depletion occurs in a portion where oxygen is removed, and a donor energy level due to fluctuation in electrical characteristics of the transistor occurs due to the oxygen deficiency.

The oxide semiconductor film 403 can be highly purified and type I (essentially) by introducing oxygen into the oxide semiconductor film 403 subjected to the dehydration treatment or the dehydrogenation treatment to supply oxygen. The variation in electrical characteristics of the transistor having the highly purified and type I (essentially) oxide semiconductor film 403 is suppressed, so that the transistor is electrically stable.

As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

When oxygen is introduced into the oxide semiconductor film 403, oxygen can be directly introduced into the oxide semiconductor film 403, and oxygen can be introduced into the oxide semiconductor film 403 through another film such as the gate insulating film 402 or the insulating film 407. When oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used, but when oxygen is directly introduced into the exposed oxide semiconductor film 403, it may be used. Plasma treatment, etc.

It is preferable to introduce oxygen into the oxide semiconductor film 403 after the dehydration treatment or the dehydrogenation treatment, but there is no particular limitation. Further, oxygen may be introduced into the oxide semiconductor film 403 subjected to the above dehydration treatment or dehydrogenation treatment a plurality of times.

Next, a gate insulating film 442 covering the oxide semiconductor film 403 is formed (see FIG. 2B).

Further, in order to improve the coverage of the gate insulating film 442, the above-described planarization treatment may be performed on the surface of the oxide semiconductor film 403. In particular, when a thin insulating film is used as the gate insulating film 442, the surface of the oxide semiconductor film 403 preferably has good flatness.

The thickness of the gate insulating film 442 is set to 1 nm or more and 20 nm or less, and a sputtering method, an MBE method, a CVD method, a pulsed laser deposition method, an ALD method, or the like can be suitably used. Further, the gate insulating film 442 may be formed using a sputtering apparatus that performs film formation in a state in which a plurality of substrate surfaces are provided substantially perpendicular to the surface of the sputtering target.

As a material of the gate insulating film 442, a hafnium oxide film, a gallium oxide film, an aluminum oxide film, a tantalum nitride film, a hafnium oxynitride film, an aluminum oxynitride film, or a hafnium oxynitride film can be used. The portion of the gate insulating film 442 that is in contact with the oxide semiconductor film 403 preferably contains oxygen. In particular, the gate insulating film 442 preferably has at least a stoichiometric amount of oxygen in its film (in the bulk), for example, when a yttrium oxide film is used as the gate insulating film 442, SiO _{2+α is used} ( Note that the film of α>0). In the present embodiment, as the gate insulating film 442, a yttrium oxide film of SiO _2+α (note that α>0) is used. By using the yttrium oxide film as the gate insulating film 442, oxygen can be supplied to the oxide semiconductor film 403 with good characteristics. Further, the gate insulating film 442 is preferably formed in consideration of the size of the transistor to be fabricated and the step coverage of the gate insulating film 442.

Further, ruthenium oxide, ruthenium oxide, ruthenium ruthenate (HfSi _x O _y (x>0, y>0)), and lanthanum ruthenate (HfSiO _x N _y added with nitrogen) are used as the material of the gate insulating film 442. (x> 0, y> 0 )), hafnium aluminate _{(HfAl x O y (x>} 0, y> 0)) , and lanthanum oxide, high-k materials, can reduce gate leakage. Further, the gate insulating film 442 may have a single layer structure or a stacked structure.

Next, a laminate of a conductive film and an insulating film is formed on the gate insulating film 442, and the conductive film and the insulating film are etched to form a stack of the gate electrode layer 401 and the insulating film 413 (see FIG. 2C).

The material of the gate electrode layer 401 can be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, niobium or tantalum or an alloy material containing them as a main component. In addition, as the gate electrode layer 401, a semiconductor film such as a polycrystalline germanium film doped with an impurity element such as phosphorus or a vaporized film such as a nickel telluride can be used. The gate electrode layer 401 may be a single layer structure or a stacked structure.

Further, the material of the gate electrode layer 401 may also be indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide. A conductive material such as indium oxide zinc oxide or indium tin oxide added with cerium oxide. Further, a laminated structure of the above conductive material and the above metal material may also be employed.

Further, as a layer of the gate electrode layer 401 which is in contact with the gate insulating film 442, a metal oxide film containing nitrogen can be used, and specifically, an In-Ga-Zn-O film containing nitrogen and In containing nitrogen can be used. -Sn-O film, In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen, In-O film containing nitrogen, and metal nitride film (InN, SnN Wait). These films have a work function of 5 eV (electron volts) or more, preferably a work function of 5.5 eV (electron volts) or more. When these films are used as the gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, and a so-called normally off switching element can be realized.

As the insulating film 413, an inorganic layer such as a hafnium oxide film, a hafnium oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a tantalum nitride film, an aluminum nitride film, a hafnium oxynitride film, or an aluminum nitride oxide film can be typically used. Insulating film. The insulating film 413 can be formed by a plasma CVD method, a sputtering method, or the like.

Next, the dopant 421 is introduced into the oxide semiconductor film 403 using the gate electrode layer 401 and the insulating film 413 as a mask to form low-resistance regions 404a and 404b (see FIG. 2D).

The dopant 421 is an impurity that changes the conductivity of the oxide semiconductor film 403. As the dopant 421, those selected from Group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), and argon (which may be used) One or more elements of Ar), ruthenium (He), iridium (Ne), indium (In), fluorine (F), chlorine (Cl), titanium (Ti), and zinc (Zn).

The dopant 421 may also be introduced into the oxide semiconductor film 403 through another film (for example, the gate insulating film 442) by an implantation method. As a method of introducing the dopant 421, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used. In this case, it is preferred to use ions of a monomer of the dopant 421 or ions of a fluoride or a chloride.

The introduction process of the dopant 421 can be appropriately controlled by setting the implantation conditions of the acceleration voltage, the dose, and the like, or the thickness of the film through which the dopant 421 is transmitted. In the present embodiment, phosphorus is used as the dopant 421, and phosphorus ions are implanted by ion implantation. Further, the dose of the dopant 421 can be set to 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less.

The concentration of the dopant 421 in the low resistance region is preferably 5 × 10 ¹⁸ /cm ³ or more and 1 × 10 ²² /cm ³ or less.

It is also possible to heat the substrate 400 while introducing the dopant 421.

In addition, a process of introducing the dopant 421 into the oxide semiconductor film 403 may be performed a plurality of times, and various dopants may also be used.

Further, heat treatment may be performed after the introduction treatment of the dopant 421 is performed. As the heating conditions, it is preferred to use a temperature of 300 ° C or more and 700 ° C or less, preferably 300 ° C or more and 450 ° C or less; and under an oxygen atmosphere; for 1 hour. Further, the heat treatment may be carried out under a nitrogen atmosphere, under reduced pressure, or under air (ultra-dry air).

In the present embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by ion implantation. Further, as the implantation condition of the phosphorus (P) ions, the following conditions were employed: the acceleration voltage was 30 kV; and the dose was 1.0 × 10 ¹⁵ ions/cm ² .

When the oxide semiconductor film 403 is a CAAC-OS film, the introduction of the dopant 421 sometimes causes amorphization of a part of the CAAC-OS film. In this case, the crystallinity of the oxide semiconductor film 403 can be recovered by performing heat treatment after the introduction of the dopant 421.

Thereby, the oxide semiconductor film 403 in which the low-resistance regions 404a, 404b are provided via the channel formation region 409 is formed.

Next, an insulating film is formed on the gate electrode layer 401 and the insulating film 413, and the insulating film is etched to form sidewall insulating layers 412a and 412b. Further, the gate insulating film 442 is etched using the gate electrode layer 401 and the sidewall insulating layers 412a and 412b as a mask to form a gate insulating film 402 (see FIG. 3A).

The sidewall insulating layers 412a, 412b can be formed using the same material and method as the insulating film 413. In the present embodiment, a hafnium oxynitride film formed by a CVD method is used.

Next, a source electrode layer and a drain electrode layer are formed on the oxide semiconductor film 403, the gate insulating film 402, the gate electrode layer 401, the sidewall insulating layers 412a and 412b, and the insulating film 413 (including use of the same The conductive film formed by the wiring of the layer).

As the conductive film, a material capable of withstanding the subsequent heat treatment is used. As the conductive film for the source electrode layer and the gate electrode layer, for example, a metal film containing an element selected from the group consisting of Al, Cr, Cu, Ta, Ti, Mo, and W or a metal nitrogen containing the above element as a component can be used. a compound film (titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like. Further, a high melting point metal film such as Ti, Mo, or W or a metal nitride film thereof (titanium nitride film, nitriding) may be laminated on one or both of the lower side and the upper side of the metal film such as Al or Cu. Structure of molybdenum film, tungsten nitride film). Further, as the conductive film used for the source electrode layer and the gate electrode layer, a conductive metal oxide can also be used. As the conductive metal oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ -SnO ₂ ), indium oxide zinc oxide (In ₂ O ₃ -ZnO) or a material in which their metal oxide material contains cerium oxide.

A photoresist mask is formed on the conductive film by a photolithography process, and etching is selectively performed to form an island-shaped conductive film 445, and then the photoresist mask is removed. In addition, in the etching process, the conductive film 445 on the gate electrode layer 401 is not removed.

In the case where a tungsten film having a thickness of 30 nm is used as the conductive film, the etching of the conductive film can be performed, for example, by dry etching (etching conditions: etching gas (CF ₄ :Cl ₂ :O ₂ =55 sccm: 45 sccm: 55 sccm), power supply of 3000 W, bias power of 140 W, and pressure of 0.67 Pa), forming an island-shaped tungsten film.

An insulating film 446 serving as the interlayer insulating film 415 is laminated on the island-shaped conductive film 445 (refer to FIG. 3B).

The insulating film 446 can be formed using the same material and method as the insulating film 413. The insulating film 446 is formed to have a thickness capable of flattening the unevenness generated by the transistor 440a. In the present embodiment, a 300 nm yttrium oxynitride film is formed by a CVD method.

Next, the insulating film 446 and the conductive film 445 are subjected to a polishing treatment by a chemical mechanical polishing method to remove a part of the insulating film 446 and the conductive film 445 so that the insulating film 413 is exposed.

The insulating film 446 is processed into the interlayer insulating film 415 by the polishing process, and the conductive film 445 on the gate electrode layer 401 is removed to form the source electrode layer 405a and the gate electrode layer 405b.

In the present embodiment, the chemical mechanical polishing method is used when the insulating film 446 and the conductive film 445 are removed, but other cutting (grinding, grinding, Polishing) method. In addition, in the process of removing the conductive film 445 on the gate electrode layer 401, in addition to the cutting (polishing, polishing) method such as chemical mechanical polishing, combined etching (dry etching, wet etching) or plasma processing may be combined. Wait. For example, dry etching or plasma processing (reverse sputtering, etc.) may be performed after the removal process by the chemical mechanical polishing method to improve the flatness of the treated surface. When the cutting (polishing, polishing) method is combined with an etching method, a plasma treatment, or the like, the order of the process is not particularly limited, and may be appropriately set depending on the material, the thickness of the insulating film 446 and the conductive film 445, and the unevenness of the surface.

Further, in the present embodiment, the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the side faces of the side wall insulating layers 412a and 412b provided on the side faces of the gate electrode layer 401, and cover the sidewall insulating layer 412a. The position of the side surface of 412b is slightly lower than the upper end portion thereof. The shape of the source electrode layer 405a and the drain electrode layer 405b differs depending on the conditions of the polishing process for removing the conductive film 445, and as described in the present embodiment, the sidewall insulating layers 412a and 412b and the insulating film 413 may be polished. The surface is retracted from the shape in the thickness direction. However, depending on the conditions of the polishing process, the heights of the upper end portions of the source electrode layer 405a and the drain electrode layer 405b may substantially coincide with the heights of the upper end portions of the sidewall insulating layers 412a and 412b.

The transistor 440a of the present embodiment is manufactured by the above process (see FIG. 3C).

In the transistor 440a, the gate electrode layer 401, the insulating film 413, and the sidewall insulation are removed by chemical mechanical polishing treatment in the process. The conductive film 445 is separated from the conductive film 445 on the layers 412a and 412b to form the source electrode layer 405a and the drain electrode layer 405b.

Further, the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the exposed oxide semiconductor film 403 and the sidewall insulating layer 412a or the sidewall insulating layer 412b. Therefore, the distance (the shortest distance) between the region (contact region) where the source electrode layer 405a or the drain electrode layer 405b contacts the oxide semiconductor film 403 and the gate electrode layer 401 is the channel length of the sidewall insulating layers 412a, 412b. The width in the direction can not only achieve further miniaturization, but can be further controlled in the process without deviation.

Thus, since the distance between the region (contact region) where the source electrode layer 405a or the drain electrode layer 405b is in contact with the oxide semiconductor film 403 and the gate electrode layer 401 can be shortened, the source electrode layer 405a or the drain electrode The electric resistance between the region (contact region) where the layer 405b is in contact with the oxide semiconductor film 403 and the gate electrode layer 401 is lowered, and the conduction characteristics of the transistor 440a can be improved.

In addition, since the etching process using the photoresist mask is not used in the process of removing the conductive film 445 on the gate electrode layer 401 in the process of forming the source electrode layer 405a and the gate electrode layer 405b, it can be accurately performed. Precision machining. Therefore, in the manufacturing process of the semiconductor device, the transistor 440a having a micro structure having a small variation in shape and characteristics can be manufactured at a high yield.

Alternatively, the conductive film 445 on the gate electrode layer 401 can be removed in the process of forming the source electrode layer 405a and the drain electrode layer 405b. In the process, a part of the insulating film 413 or the entire insulating film 413 is removed. 4C shows an example of a transistor 440c that removes the entire insulating film 413 and exposes the gate electrode layer 401. In addition, a portion above the gate electrode layer 401 may also be removed. The structure in which the gate electrode layer 401 is exposed as in the transistor 440c can be applied to an integrated circuit in which other wirings or semiconductor elements are stacked on the transistor 440c.

It is also possible to provide a highly dense inorganic insulating film (typically an aluminum oxide film) serving as a protective insulating film on the transistor 440a.

In the present embodiment, the insulating film 407 is formed in contact with the insulating film 413, the source electrode layer 405a, the gate electrode layer 405b, the sidewall insulating layers 412a and 412b, and the interlayer insulating film 415 (see FIG. 3D).

Further, an inorganic insulating film (typically an aluminum oxide film) having high density as a protective insulating film may be provided between the source electrode layer 405a and the drain electrode layer 405b and the interlayer insulating film 415.

4B shows an example of a transistor 440b in which an insulating film 410 is provided between the source electrode layer 405a and the gate electrode layer 405b and the interlayer insulating film 415. In the transistor 440b, the upper surface of the insulating film 410 is also subjected to a planarization process by a cutting (polishing, polishing) process used in the process of forming the source electrode layer 405a and the gate electrode layer 405b.

The insulating films 407, 410 may have a single layer structure or a stacked structure, and preferably contain at least an aluminum oxide film.

The insulating films 407 and 410 can be formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like.

As the insulating films 407 and 410, in addition to the aluminum oxide film, it is typically An inorganic insulating film such as a hafnium oxide film, a hafnium oxynitride film, an aluminum oxynitride film or a gallium oxide film is used. Further, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a hafnium oxide film, a hafnium oxide film or a metal nitride film (for example, an aluminum nitride film) may also be used.

In the present embodiment, an aluminum oxide film is formed as a insulating film 407, 410 by a sputtering method. By setting the film density of the aluminum oxide film to a high density (having a film density of 3.2 g/cm ³ or more, preferably 3.6 g/cm ³ or more), it is possible to impart stable electrical characteristics to the transistors 440a and 440b. The film density can be measured by Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectometry (XRR: X-Ray Reflectometry).

The aluminum oxide film which can be used for the insulating films 407 and 410 provided on the oxide semiconductor film 403 has a high blocking effect (barrier effect), that is, an effect of not allowing both impurities such as hydrogen and moisture and oxygen to pass through the film.

Therefore, the aluminum oxide film is used as a protective film, that is, impurities such as hydrogen and moisture which are caused by variations in the process and after the production are prevented from being mixed into the oxide semiconductor film 403, and are prevented from being released from the oxide semiconductor film 403 as an oxide semiconductor. The main component of the material is oxygen.

The insulating films 407 and 410 are preferably formed by a method (preferably, a sputtering method or the like) in which impurities such as water or hydrogen are not mixed into the insulating films 407 and 410.

Similarly to the case of forming the oxide semiconductor film, in order to remove moisture remaining in the deposition chamber of the insulating films 407 and 410, it is preferable to use an adsorption type vacuum pump (such as a cryopump). When formed in a deposition chamber using a cryopump exhaust In the case of the insulating films 407 and 410, the concentration of impurities contained in the insulating films 407 and 410 can be lowered. Further, as the exhaust unit for removing moisture remaining in the deposition chambers of the insulating films 407, 410, a turbo molecular pump equipped with a cold trap may be employed.

As the sputtering gas used when forming the insulating films 407 and 410, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group or a hydride are removed.

Further, in order to reduce surface unevenness caused by the transistor, a planarization insulating film may be formed. As the planarization insulating film, an organic material such as a polyimide resin, an acrylic resin, or a benzocyclobutene resin can be used. Further, in addition to the above organic materials, a low dielectric constant material (low-k material) or the like can be used. Further, a planarization insulating film may be formed by laminating a plurality of insulating films formed of these materials.

In addition, FIG. 4A shows an example in which the openings reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the interlayer insulating film 415 and the insulating film 407, and the wiring layers 435a and 435b are formed in the openings. The wiring 435a, 435b can be used to connect the transistor 440a to other transistors or elements to form various circuits.

The wiring layer 435a and the wiring layer 435b may be formed by using the same material and method as the gate electrode layer 401, the source electrode layer 405a, or the gate electrode layer 405b, and for example, may be selected from the group consisting of Al, Cr, Cu, Ta, A metal film of an element in Ti, Mo, or W, or a metal nitride film (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above elements as a component. Further, a high melting point metal film such as Ti, Mo, or W or a metal nitride film thereof (titanium nitride film, nitriding) may be laminated on one or both of the lower side and the upper side of the metal film such as Al or Cu. Structure of molybdenum film, tungsten nitride film). Further, as the conductive film used for the wiring layer 435a and the wiring layer 435b, a conductive metal oxide can also be used. As the conductive metal oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ -SnO ₂ ), indium oxide zinc oxide (In ₂ O ₃ -ZnO) or a material in which their metal oxide material contains cerium oxide.

For example, as the wiring layer 435a and the wiring layer 435b, a single layer of a molybdenum film, a laminate of a tantalum nitride film and a copper film, a laminate of a tantalum nitride film and a tungsten film, or the like can be used.

As described above, in the manufacturing process of the semiconductor device, the transistors 440a, 440b, and 440c having high micro-conductivity with high conductivity can be provided with high variation in shape and characteristics.

Thereby, it is possible to provide a semiconductor device which realizes miniaturization and imparts high electric characteristics, and a method of manufacturing the semiconductor device.

Embodiment 2

In the present embodiment, an example of a semiconductor device that uses the transistor shown in the present specification to hold data stored without power supply and has no write number is described with reference to the drawings. limit.

5A to 5C are examples of the structure of a semiconductor device. 5A is a cross-sectional view of the semiconductor device, FIG. 5B is a plan view of the semiconductor device, and FIG. 5C is a circuit diagram of the semiconductor device. Here, Figure 5A is quite A section along C1-C2 and D1-D2 in Fig. 5B.

The semiconductor device shown in FIGS. 5A and 5B has a transistor 160 using a first semiconductor material at its lower portion and a transistor 162 using a second semiconductor material at its upper portion. The transistor 162 is an example of a configuration in which the transistor 440a shown in Embodiment 1 is applied.

Here, the first semiconductor material and the second semiconductor material are preferably materials having different energy gaps. For example, a semiconductor material other than an oxide semiconductor (germanium or the like) may be used for the first semiconductor material, and an oxide semiconductor may be used for the second semiconductor material. A transistor using a material other than an oxide semiconductor is easy to operate at a high speed. On the other hand, a transistor using an oxide semiconductor can retain a charge for a long time by utilizing its characteristics.

Further, although the case where the above-described transistors are all n-channel type transistors will be described, it is of course possible to use a p-channel type transistor. Further, the specific structure of the semiconductor device used for the material of the semiconductor device or the structure of the semiconductor device or the like is not necessarily limited to this, except that the oxide semiconductor is used for the transistor 162 as shown in Embodiment 1 in order to maintain information. The structure shown.

The transistor 160 in FIG. 5A includes: a channel formation region 116 disposed in a substrate 185 including a semiconductor material (eg, germanium, etc.); an impurity region 120 disposed in a manner sandwiching the channel formation region 116; and contacting the impurity region 120 The intermetallic compound region 124; the gate insulating film 108 disposed on the channel forming region 116; and the gate electrode 110 disposed on the gate insulating film 108. Note that although the source electrode or the drain electrode is sometimes not apparent in the drawings, this state is sometimes referred to as electricity for convenience. Crystal. Further, in this case, in order to explain the connection relationship of the transistors, the source region or the drain region is sometimes referred to as a source electrode or a drain electrode. That is, in the present specification, the source electrode may include a source region.

An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160, and an insulating layer 128 and an insulating layer 130 are provided to cover the transistor 160. Further, in the transistor 160, the sidewall insulating layer may be provided on the side surface of the gate electrode 110, and the impurity region 120 may also include a region having a different impurity concentration.

The transistor 160 using a single crystal semiconductor substrate can perform high speed operation. Therefore, by using the transistor as a readout transistor, information can be read at high speed. Two insulating films are formed in such a manner as to cover the transistor 160. As a process before forming the transistor 162 and the capacitor 164, the two insulating films are subjected to CMP treatment to form the planarized insulating layer 128 and the insulating layer 130, and the upper surface of the gate electrode 110 is exposed.

As the insulating layer 128 and the insulating layer 130, a hafnium oxide film, a hafnium oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a tantalum nitride film, an aluminum nitride film, a hafnium oxynitride film, or an oxynitride can be typically used. An inorganic insulating film such as an aluminum film. The insulating layer 128 and the insulating layer 130 can be formed by a plasma CVD method, a sputtering method, or the like.

Further, an organic material such as a polyimide resin, an acrylic resin or a benzocyclobutene resin can be used. Further, in addition to the above organic materials, a low dielectric constant material (low-k material) or the like can also be used. When an organic material is used, the insulating layer 128 and the insulating layer 130 may be formed by a wet process such as a spin coating method or a printing method.

Further, in the present embodiment, a tantalum nitride film is used as the insulating layer 128, and a hafnium oxide film is used as the insulating layer 130.

Preferably, the region on the surface of the insulating layer 130 on which the oxide semiconductor film 144 is formed is planarized. In the present embodiment, the oxide semiconductor film 144 is formed on the insulating layer 130 by being sufficiently planarized by a polishing process (for example, CMP process) (preferably, the average surface roughness of the surface of the insulating layer 130 is 0.15 nm or less). .

The transistor 162 shown in Fig. 5A is a transistor in which an oxide semiconductor is used for the channel formation region. Here, the oxide semiconductor film 144 included in the transistor 162 is preferably a highly purified oxide semiconductor film. By using a highly purified oxide semiconductor, a transistor 162 having extremely excellent cut-off characteristics can be obtained.

Since the off current of the transistor 162 is small, the storage of data can be maintained for a long period of time by using such a transistor. In other words, since it is possible to form a semiconductor memory device having an extremely low frequency that does not require an update operation or an update operation, power consumption can be sufficiently reduced.

In the process of the transistor 162, a process for removing the conductive film provided on the gate electrode 148, the insulating film 137, and the sidewall insulating layers 136a, 136b by a chemical mechanical polishing process is used to form a source electrode layer and a drain electrode. Electrode layers 142a, 142b of the electrode layer.

Therefore, since the distance between the region (contact region) where the electrode layers 142a, 142b serving as the source electrode layer or the gate electrode layer are in contact with the oxide semiconductor film 144 and the gate electrode 148 can be shortened in the transistor 162, Therefore, the electrode layers 142a, 142b are in contact with the region of the oxide semiconductor film 144. The electric resistance between the domain (contact region) and the gate electrode 148 is lowered, so that the conduction characteristics of the transistor 162 can be improved.

Since the etching process using the photoresist mask is not utilized in the process of removing the conductive film on the gate electrode 148 in the process of forming the electrode layers 142a, 142b, precise processing can be accurately performed. Therefore, in the process of the semiconductor device, it is possible to manufacture a transistor having a micro structure having a small variation in shape and characteristics at a high yield.

A single layer or a laminated interlayer insulating film 135 and an insulating film 150 are provided on the transistor 162. In the present embodiment, an aluminum oxide film is used as the insulating film 150. By setting the film density of the aluminum oxide film to a high density (film density of 3.2 g/cm ³ or more, preferably 3.6 g/cm ³ or more), it is possible to impart stable electrical characteristics to the transistor 162.

Further, a conductive layer 153 is provided in a region overlapping the electrode layer 142a of the transistor 162 via the interlayer insulating film 135 and the insulating film 150, and the capacitor layer 142a, the interlayer insulating film 135, the insulating film 150, and the conductive layer 153 constitute a capacitor. Element 164. In other words, the electrode layer 142a of the transistor 162 serves as an electrode of one of the capacitance elements 164, and the conductive layer 153 serves as the other electrode of the capacitance element 164. In addition, when a capacitor is not required, a configuration in which the capacitor element 164 is not provided may be employed. In addition, the capacitor element 164 may be separately disposed above the transistor 162.

An insulating film 152 is provided on the transistor 162 and the capacitor 164. Further, a transistor 162 and a wiring 156 for connecting other transistors are provided on the insulating film 152. Although not shown in FIG. 5A, the wiring 156 is formed on the insulating film 150, the insulating film 152, and the gate insulating film. The electrode in the opening in 146 or the like is electrically connected to the electrode layer 142b. Here, it is preferable that the electrode is provided at least in such a manner as to overlap with a part of the oxide semiconductor film 144 of the transistor 162.

In FIGS. 5A and 5B, it is preferable that the transistor 160 and the transistor 162 are disposed in such a manner that at least a part thereof overlap, and a source region or a drain region of the transistor 160 overlaps with a portion of the oxide semiconductor film 144. Way to set. Further, a transistor 162 and a capacitor 164 are provided so as to overlap at least a portion of the transistor 160. For example, the conductive layer 153 of the capacitive element 164 and the gate electrode 110 of the transistor 160 are disposed in such a manner as to overlap at least partially. By adopting such a planar layout, the area occupied by the semiconductor device can be reduced, and high collectivization can be realized.

In addition, the electrical connection between the electrode layer 142b and the wiring 156 can be achieved by directly contacting the electrode layer 142b with the wiring 156, or by providing an electrode in the insulating film between the electrode layer 142b and the wiring 156. The electrodes are electrically connected. In addition, there may be a plurality of electrodes in between.

Next, Fig. 5C shows an example of the circuit configuration corresponding to Figs. 5A and 5B.

In FIG. 5C, the first wiring (1st Line) is electrically connected to the source electrode of the transistor 160, and the second wiring (2nd Line) is electrically connected to the drain electrode of the transistor 160. Further, the third wiring (3rd line) is electrically connected to one of the source electrode and the drain electrode of the transistor 162, and the fourth wiring (4th line) is electrically connected to the gate electrode of the transistor 162. And, the gate electrode of the transistor 160 and the source electrode and the gate electrode of the transistor 162 The other of the poles is electrically connected to one of the electrodes of the capacitive element 164, and the fifth wiring (5th Line) is electrically connected to the other of the electrodes of the capacitive element 164.

In the semiconductor device shown in FIG. 5C, by effectively utilizing the feature of the potential of the gate electrode capable of holding the transistor 160, information can be written, held, and read as described below.

Explain the writing and maintenance of information. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. Thereby, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitance element 164. That is, a predetermined charge (writing) is applied to the gate electrode of the transistor 160. Here, any one of electric charges (hereinafter, referred to as Low level charge and High level charge) imparting two different potential levels is applied. Then, by setting the potential of the fourth wiring to a potential at which the transistor 162 is turned off, the transistor 162 is turned off, and the charge applied to the gate electrode of the transistor 160 is held (held).

Since the off current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is maintained for a long time.

Next, the reading of the information will be described. When an appropriate potential (readout potential) is applied to the fifth wiring in a state where a predetermined potential (constant potential) is applied to the first wiring, the second wiring has a charge amount according to the gate electrode held in the transistor 160. Different potentials. This is because, in general, in the case where the transistor 160 is of the n-channel type, the appearance threshold _{Vth_H} when the high-level charge is applied to the gate electrode of the transistor 160 is lower than that of the transistor 160. The appearance threshold _{Vth_L} when the gate electrode is applied with a low level charge. Here, the threshold voltage in appearance refers to the potential of the fifth wiring required to make the transistor 160 "on". Therefore, by setting the potential of the fifth wiring to the potential V ₀ between V _{th — H} and V _{th — L} , the electric charge applied to the gate electrode of the transistor 160 can be discriminated. For example, in writing, when the High level charge is supplied, if the potential of the fifth wiring is V ₀ (>V _{th — H} ), the transistor 160 becomes “on state”. When the Low level charge is supplied, the transistor 160 maintains the "off state" even if the potential of the fifth wiring is V ₀ (<V _{th_L} ). Therefore, the held information can be read out based on the potential of the second wiring.

Note that when the memory cells are arranged in an array, it is necessary to read only the information of the desired memory cells. In the case of a memory cell that does not read information, a potential that causes the transistor 160 to be "off state" regardless of the state of the gate electrode, that is, a potential smaller than _{Vth_H} , may be applied to the fifth wiring. Alternatively, the potential of the transistor 160 to be "on" may be made regardless of the state of the gate electrode, that is, a potential greater than _{Vth_L} may be applied to the fifth wiring.

In addition, FIG. 19A and FIG. 19B show another example of the structure of the semiconductor device. 19A is a plan view of a semiconductor device, and FIG. 19B is a cross-sectional view of the semiconductor device. Here, FIG. 19B corresponds to a cross section taken along line D3-D4 of FIG. 19A. In addition, for the sake of clarity, a part of the constituent elements of the semiconductor device shown in FIG. 19B is omitted in FIG. 19A.

In FIGS. 19A and 19B, the capacitive element 164 is composed of a gate electrode 110. The oxide semiconductor film 144, the insulating film 173, and the conductive layer 174 are formed. The conductive layer 174 is fabricated by the same process as the gate electrode 148, the upper surface of which is covered by the insulating film 176, and the side faces thereof are covered by the sidewall insulating layers 175a, 175b.

The electrode layer 142b of the transistor 162 is electrically connected to the wiring 156 in an opening formed in the interlayer insulating film 135 and the insulating film 150 reaching the electrode layer 142b. Further, a conductive layer 172 is provided in contact with the underside of the oxide semiconductor film 144, and the transistor 160 is electrically connected to the transistor 162 by the conductive layer 172.

As shown in FIG. 19A and FIG. 19B, by densely laminating the transistor 160, the transistor 162, and the capacitor 164, the area occupied by the semiconductor device can be reduced, and high collectivization can be realized.

In the semiconductor device shown in the present embodiment, by using an oxide semiconductor for a transistor having a very small off-state current in the channel formation region, it is possible to maintain the stored data for a long period of time. That is to say, since the update work is not required, or the frequency of the update work can be reduced to an extremely low level, the power consumption can be sufficiently reduced. In addition, even in the case where there is no power supply (however, the preferred potential is fixed), the stored data can be kept for a long time.

Further, in the semiconductor device described in the present embodiment, writing of information does not require a high voltage, and there is no problem that the element is deteriorated. For example, unlike the case of the conventional non-volatile memory, there is no need to inject electrons into the floating gate or extract electrons from the floating gate, so that there is no problem such as deterioration of the gate insulating film. That is, in accordance with the disclosed invention In the semiconductor device, the number of times that can be rewritten as a problem of the conventional non-volatile memory is not limited, and the reliability is remarkably improved. Further, information writing is performed according to the on state or the off state of the transistor, and high speed operation can be easily realized.

As described above, it is possible to provide a semiconductor device that realizes miniaturization and high collectivization and imparts high electric characteristics, and a method of manufacturing the semiconductor device.

As described above, the configuration, the method, and the like described in the present embodiment can be used in combination with any of the structures, methods, and the like described in the other embodiments.

Embodiment 3

In the present embodiment, a structure different from the configuration shown in the second embodiment will be described with reference to FIGS. 6A to 7B with respect to the semiconductor device using the transistor described in the first embodiment or the second embodiment. The semiconductor device is capable of holding stored data even in the absence of power supply, and there is no limitation on the number of writes.

FIG. 6A shows an example of a circuit configuration of a semiconductor device, and FIG. 6B is a schematic view showing an example of a semiconductor device. First, the semiconductor device shown in FIG. 6A will be described, and then the semiconductor device shown in FIG. 6B will be described.

In the semiconductor device shown in FIG. 6A, the bit line BL is electrically connected to one of the source electrode and the drain electrode of the transistor 162, the word line WL is electrically connected to the gate electrode of the transistor 162, and the transistor 162 The other of the source electrode and the drain electrode is electrically connected to the first terminal of the capacitive element 254.

Next, a case where information is written and held to the semiconductor device (memory unit 250) shown in FIG. 6A will be described.

First, the transistor 162 is turned on by setting the potential of the word line WL to a potential at which the transistor 162 is turned on. Thereby, the potential of the bit line BL is applied to the first terminal (write) of the capacitive element 254. Then, by setting the potential of the word line WL to a potential at which the transistor 162 is turned off, the transistor 162 is turned off, whereby the potential of the first terminal of the capacitor 254 is stored (held).

The transistor 162 using an oxide semiconductor has a feature that the off current is extremely small. Therefore, by causing the transistor 162 to be in an off state, the potential of the first terminal of the capacitive element 254 (or the charge accumulated in the capacitive element 254) can be stored for a very long time.

Next, the reading of the information will be described. When the transistor 162 is turned on, the bit line BL in the floating state is electrically connected to the first terminal of the capacitor 254, and thus the charge is redistributed between the bit line BL and the capacitor 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL takes a different value depending on the potential of the first terminal of the capacitive element 254 (or the charge accumulated in the capacitive element 254).

For example, when the potential of the first terminal of the capacitive element 254 is denoted by V, the capacitance of the capacitive element 254 is denoted by C, and the capacitance component (hereinafter also referred to as a bit line capacitance) of the bit line BL is denoted by CB, and VB0 represents the potential of the bit line BL before the charge is redistributed, and the potential of the bit line BL after the charge is redistributed becomes (CB*VB0+C*V)/ (CB+C). Therefore, as the state of the memory cell 250, when the potential of the first terminal of the capacitive element 254 is in two states of V1 and V0 (V1 > V0), the potential of the bit line BL when the potential V1 is held (= (CB*) VB0+C*V1)/(CB+C)) is higher than the potential of the bit line BL when the potential V0 is held (=(CB*VB0+C*V0)/(CB+C)).

Also, information can be read by comparing the potential of the bit line BL with the specified potential.

As such, the semiconductor device shown in FIG. 6A can maintain the electric charge accumulated in the capacitance element 254 for a long time by utilizing the characteristic that the off current of the transistor 162 is extremely small. In other words, since the update work is not required, or the frequency of the update work can be made extremely low, the power consumption can be sufficiently reduced. In addition, the stored data can be kept for a long period of time even in the absence of power supply.

Next, the semiconductor device shown in FIG. 6B will be described.

The semiconductor device shown in FIG. 6B has a memory cell array 251a and 251b as a memory circuit at its upper portion, and the memory cell arrays 251a and 251b have a plurality of memory cells 250 shown in FIG. 6A. Further, the semiconductor device shown in FIG. 6B has a peripheral circuit 253 at its lower portion for operating the memory cell array 251 (memory cell arrays 251a and 251b). In addition, the peripheral circuit 253 is electrically connected to the memory cell array 251.

By adopting the configuration shown in FIG. 6B, the peripheral circuit 253 can be disposed directly under the memory cell array 251 (memory cell arrays 251a and 251b), so that the miniaturization of the semiconductor device can be realized.

As the transistor provided in the peripheral circuit 253, it is more preferably used and The transistor 162 is a different semiconductor material. For example, ruthenium, osmium, iridium, ruthenium carbide or gallium arsenide or the like can be used, and a single crystal semiconductor is preferably used. In addition, organic semiconductor materials can also be used. A transistor using such a semiconductor material can perform sufficient high speed operation. Therefore, by using the transistor, various circuits (logic circuits, drive circuits, and the like) that are required to operate at high speed can be smoothly realized.

In addition, the semiconductor device shown in FIG. 6B exemplifies a configuration in which two memory cell arrays 251 (memory cell array 251a and memory cell array 251b) are stacked, but the number of stacked memory cell arrays is not limited thereto. A structure in which three or more memory cell arrays are stacked may also be employed.

Next, a specific structure of the memory unit 250 shown in FIG. 6A will be described with reference to FIGS. 7A and 7B.

7A and 7B show an example of the structure of the memory unit 250. FIG. 7A shows a cross-sectional view of the memory unit 250, and FIG. 7B shows a plan view of the memory unit 250. Here, FIG. 7A corresponds to a cross section along F1-F2 and G1-G2 in FIG. 7B.

The transistor 162 shown in FIGS. 7A and 7B can have the same configuration as that shown in the first embodiment or the second embodiment.

A single layer or a laminated insulating film 256 is provided on the transistor 162 provided on the insulating film 180. Further, a conductive layer 262 is provided in a region overlapping the electrode layer 142a of the transistor 162 via the insulating film 256, and the capacitor element 254 is composed of the electrode layer 142a, the interlayer insulating film 135, the insulating film 256, and the conductive layer 262. In other words, the electrode layer 142a of the transistor 162 serves as one electrode of the capacitive element 254, and the conductive layer 262 functions as a capacitive element The other electrode of 254.

An insulating film 258 is provided on the transistor 162 and the capacitor element 254. Further, a memory unit 250 and a wiring 260 for connecting the adjacent memory cells 250 are provided on the insulating film 258. Although not shown, the wiring 260 is electrically connected to the electrode layer 142b of the transistor 162 by an opening formed in the insulating film 256, the insulating film 258, or the like. However, it is also possible to provide another conductive layer in the opening, and electrically connect the wiring 260 and the electrode layer 142b by the other conductive layer. In addition, the wiring 260 corresponds to the bit line BL in the circuit diagram of FIG. 6A.

In FIGS. 7A and 7B, the electrode layer 142b of the transistor 162 can also be used as a source electrode of a transistor included in an adjacent memory cell. By adopting such a planar layout, the area occupied by the semiconductor device can be reduced, and high collectivization can be realized.

By adopting the planar layout shown in FIG. 7A, the area occupied by the semiconductor device can be reduced, and high collectivization can be realized.

In addition, FIG. 20A and FIG. 20B show another example of the structure of the semiconductor device.

20A is a plan view of a semiconductor device, and FIG. 20B is a cross-sectional view of the semiconductor device. Here, FIG. 20B corresponds to a cross section taken along line F5-F6 of FIG. 20A. In addition, for the sake of clarity, a part of the components of the semiconductor device shown in FIG. 20B is omitted in FIG. 20A.

In FIGS. 20A and 20B, the capacitance element 254 is composed of a conductive layer 192, an insulating film 193, and a conductive film 194, and is formed in the insulating film 196. Further, the insulating film 193 is preferably made of an insulating material having a high dielectric constant. Electricity The capacitance element 254 is electrically connected to the transistor 162 by a conductive layer 191 provided in an opening of the electrode layer 142a reaching the transistor 162 formed in the interlayer insulating film 135, the insulating film 150, and the insulating film 195.

As shown in FIG. 20A and FIG. 20B, by densely laminating the transistor 162 and the capacitor element 254 so as to overlap each other, the area occupied by the semiconductor device can be reduced, and high collectivization can be realized.

As described above, the plurality of memory cells formed in the upper layer are formed of a transistor using an oxide semiconductor. Since the off-state current of the transistor using the oxide semiconductor is small, the storage of the data can be maintained for a long period of time by using such a transistor. In other words, the frequency of the update operation can be made extremely low, so that the power consumption can be sufficiently reduced.

As described above, a peripheral circuit using a transistor using a material other than an oxide semiconductor (in other words, a transistor capable of performing a sufficiently high-speed operation) and a transistor using an oxide semiconductor (for a broader explanation, The storage circuit of the transistor having a sufficiently small off current is integrated, and a semiconductor device having novel features can be realized. In addition, the collectiveization of the semiconductor device can be realized by using a laminated structure of the peripheral circuit and the storage circuit.

As described above, it is possible to provide a semiconductor device that realizes miniaturization and high collectivization and imparts high electric characteristics, and a method of manufacturing the semiconductor device.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Embodiment 4

In the present embodiment, an example in which the semiconductor device described in the above embodiment is applied to a mobile device such as a mobile phone, a smart phone, or an e-book reader will be described with reference to FIGS. 8A to 11 .

In mobile devices such as mobile phones, smart phones, and e-book readers, SRAM or DRAM is used to temporarily store image data. The use of SRAM or DRAM is due to the slow response speed of flash memory and is not suitable for processing images. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following features are obtained.

As shown in FIG. 8A, in a general SRAM, one memory cell is composed of six transistors of a transistor 801 to a transistor 806, and the transistor 801 to the transistor 806 are driven by an X decoder 807 and a Y decoder 808. . The transistor 803 and the transistor 805 and the transistor 804 and the transistor 806 constitute an inverter which enables high speed driving. However, since one memory cell is composed of six transistors, there is a disadvantage that the memory cell area is large. In the case where the minimum size of the design rule is set to F, the memory cell area of the SRAM is generally 100 to 150 F ² . Therefore, the unit price of each bit of the SRAM is the highest among the various memories.

On the other hand, in the DRAM, as shown in FIG. 8B, the memory unit is constituted by the transistor 811 and the storage capacitor 812, and the transistor 811 and the storage capacitor 812 are driven by the X decoder 813 and the Y decoder 814. Since a unit is composed of a transistor and a capacitor, its area is small. The storage area of DRAM is generally 10F ² or less. Note that the DRAM needs to be updated all the time, so power is consumed even without rewriting.

On the other hand, the memory cell area of the semiconductor device of the embodiment described above is about 10F ^2, and does not require frequent updating. Thereby, the memory cell area can be reduced, and power consumption can also be reduced.

Figure 9 shows a block diagram of a mobile device. The mobile device shown in FIG. 9 has an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, and a storage circuit 912. A display 913; a touch sensor 919; an audio circuit 917; and a keyboard 918 and the like. The display 913 has a display portion 914, a source driver 915, and a gate driver 916. The application processor 906 has a CPU (Central Processing Unit) 907, a DSP (Digital Signal Processor) 908, and an interface 909 (IF 909). The storage circuit 912 is generally composed of an SRAM or a DRAM. By using the semiconductor device described in the above embodiments for the portion, information can be written and read at a high speed, and data can be stored for a long period of time, and the memory can be sufficiently reduced. Electricity.

FIG. 10 shows an example in which the semiconductor device described in the above embodiment is used for the storage circuit 950 of the display. The storage circuit 950 shown in FIG. 10 has a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. In addition, the storage circuit 950 is connected to: a display controller 956 for reading and controlling image data (input image data) input from the signal line and data (storing image data) stored in the memory 952 and the memory 953; And a display 957 that displays in accordance with signals from display controller 956.

First, an image data (input image data A) is formed by an application processor (not shown). The input image data A is stored in the memory 952 by the switch 954. Then, the image data (storage image data A) stored in the memory 952 is transmitted to the display 957 by the switch 955 and the display controller 956 for display.

When there is no change in the input image data A, the stored image data A is generally read from the memory 952 by the display controller 956 via the switch 955 at a cycle of about 30 to 60 Hz.

Further, for example, when the user performs an operation of rewriting the screen (that is, when the input image data A changes), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 by the switch 954. During this period, the stored image data A is also continuously read from the memory 952 by the switch 955. When a new image (storing image data B) is stored in the memory 953, the stored image data B is read from the next frame of the display 957, and the stored image data B is controlled by the switch 955 and the display controller. 956 is sent to display 957 for display. The reading continues until the next new image data is stored in the memory 952.

As described above, the display of the display 957 is performed by alternately writing the image data and reading the image data by the memory 952 and the memory 953. Further, the memory 952 and the memory 953 are not limited to two different memories, and one memory may be divided and used. By using the semiconductor device described in the above embodiment in the memory 952 and the memory 953, it is possible to write and read information at high speed, and it is possible to protect the data for a long period of time. With stored data, you can also fully reduce power consumption.

Figure 11 shows a block diagram of an e-book reader. The e-book reader shown in FIG. 11 has: battery 1001; power supply circuit 1002; microprocessor 1003; flash memory 1004; audio circuit 1005; keyboard 1006; storage circuit 1007; touch screen 1008; display 1009; 1010.

Here, the semiconductor device described in the above embodiment can be used for the storage circuit 1007 of FIG. The storage circuit 1007 has a function of temporarily holding the contents of the book. As an example of this function, for example, there is a case where a user uses a highlight function. When users look at e-book readers, they sometimes need to mark a part. This marking function is called highlighting, that is, by changing the display color; underlining; changing the text to bold; changing the font of the text, etc., so that the part is not the same as the surrounding and highlighted. The highlight function is a function of storing and retaining information of a part designated by the user. When the information is held for a long time, the information can also be copied to the flash memory 1004. Even in this case, by using the semiconductor device described in the above embodiment, information can be written and read at a high speed, data can be stored for a long period of time, and power consumption can be sufficiently reduced.

As described above, the mobile device shown in the present embodiment is mounted with the semiconductor device according to the above embodiment. Therefore, it is possible to realize a mobile device that reads information at a high speed, stores data for a long period of time, and sufficiently reduces power consumption.

The structure, method, and the like described in the present embodiment can be implemented in appropriate combination with the structures, methods, and the like described in the other embodiments.

Embodiment 5

A semiconductor device (also referred to as a display device) having a display function can be manufactured by using the transistor exemplified in the above embodiment. Further, a system-on-panel can be formed by integrally forming a part or the entire portion of the driving circuit including the transistor on the same substrate as the pixel portion.

In FIG. 12A, the sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and the sealing is performed using the second substrate 4006. In FIG. 12A, a scanning line driving circuit 4004 formed on a separately prepared substrate using a single crystal semiconductor film or a polycrystalline semiconductor film is mounted in a region different from a region surrounded by the sealing material 4005 on the first substrate 4001, Signal line driver circuit 4003. Further, various signals and potentials supplied to the separately formed signal line driver circuit 4003, scanning line driver circuit 4004, or pixel portion 4002 are supplied from FPC (Flexible Print Circuit) 4018a, 4018b.

In FIGS. 12B and 12C, a sealing material 4005 is provided in such a manner as to surround the pixel portion 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001. Further, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005, and the second substrate 4006. In FIGS. 12B and 12C, a single crystal semiconductor film or a polycrystalline semiconductor film shape is mounted in a region on the first substrate 4001 different from a region surrounded by the sealing material 4005. The signal line driver circuit 4003 is formed on a separately prepared substrate. In FIGS. 12B and 12C, various signals and potentials supplied to the separately formed signal line driver circuit 4003, scanning line driver circuit 4004, or pixel portion 4002 are supplied from the FPC 4018.

Further, FIGS. 12B and 12C illustrate an example in which the signal line driver circuit 4003 is separately formed and the signal line driver circuit 4003 is mounted to the first substrate 4001, but is not limited to this structure. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

Further, the connection method of the separately formed drive circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, a TAB (Tape Automated Bonding) method, or the like can be used. 12A is an example in which the signal line driver circuit 4003 and the scanning line driver circuit 4004 are mounted by the COG method, FIG. 12B is an example in which the signal line driver circuit 4003 is mounted by the COG method, and FIG. 12C is a signal line driver mounted by the TAB method. An example of circuit 4003.

Further, the display device includes a panel (display panel, light-emitting panel) sealed with display elements, and a module in which an IC or the like including a controller is mounted.

Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). In addition, the display device further includes: a module mounted with a connector such as FPC, TAB tape or TCP; a module provided with a printed wiring board at the end of the TAB tape or TCP; or The IC (integrated circuit) is directly mounted to the module of the display element by the COG method.

Further, the pixel portion and the scanning line driving circuit provided on the first substrate have a plurality of transistors, and the transistor illustrated in the above embodiment can be applied.

As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, and the like. Further, it is also possible to apply a display medium such as electronic ink that changes the contrast due to electrical action.

One mode of the semiconductor device will be described with reference to FIGS. 12A to 12C and FIGS. 13A and 13B. 13A and 13B correspond to a cross-sectional view taken along line M-N of Fig. 12B.

As shown in FIGS. 12A to 12C and FIGS. 13A and 13B, the semiconductor device includes a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are electrically connected to the FPC 4018 by an anisotropic conductive film 4019. Terminal.

The connection terminal electrode 4015 is formed of the same conductive film as the first electrode layer 4030, and the terminal electrode 4016 is formed of the same conductive film as the source electrode layer and the gate electrode layer of the transistors 4010 and 4011.

Further, the pixel portion 4002 disposed on the first substrate 4001, the scanning line driving circuit 4004 has a plurality of transistors, and the transistors included in the pixel portion 4002 are illustrated in FIGS. 12A to 12C and FIGS. 13A and 13B. 4010. A transistor 4011 included in the scan line driver circuit 4004. In FIG. 13A, an interlayer insulating film 4020 and an insulating film 4024 are provided on the transistors 4010 and 4011, and an insulating film 4021 is provided. In addition, the insulating film 4023 is an insulating film used as a base film. Further, a light shielding film 4050 is provided in a region overlapping the transistors 4010 and 4011.

As the transistors 4010 and 4011, the transistor described in the above embodiment can be used. In the present embodiment, an example of using a transistor having the same structure as that of the transistor 440a shown in Embodiment 1 is shown.

In the transistors 4010 and 4011, in the process, the conductive film provided on the gate electrode layer, the insulating film and the sidewall insulating layer is removed by chemical mechanical polishing, and the conductive film is separated to form a source electrode layer and a germanium electrode. Electrode layer.

Therefore, since the distance between the region (contact region) where the source electrode layer or the gate electrode layer is in contact with the oxide semiconductor film and the gate electrode layer can be shortened, the source electrode layer or the gate electrode layer is in contact with the oxide The electric resistance between the region (contact region) of the semiconductor film and the gate electrode layer is lowered, and the conduction characteristics of the transistors 4010 and 4011 can be improved.

Since the etching process using the photoresist mask is not used in the process of removing the conductive film on the gate electrode layer in the process of forming the source electrode layer and the gate electrode layer, precise processing can be accurately performed. Therefore, in the process of the semiconductor device, the transistors 4010 and 4011 having a micro structure with little variation in shape and characteristics can be manufactured with high yield.

Therefore, as the semiconductor device of the present embodiment shown in FIGS. 12A to 12C and FIGS. 13A and 13B, a highly reliable semiconductor can be provided. Device.

Further, a conductive layer may be further provided at a position overlapping with the channel formation region of the oxide semiconductor film of the driver circuit transistor 4011. By providing the conductive layer at a position overlapping the channel formation region of the oxide semiconductor film, the amount of change in the threshold voltage of the transistor 4011 before and after the bias-heat stress test (BT test) can be further reduced. Further, the potential of the conductive layer may be the same as or different from the potential of the gate electrode layer of the transistor 4011, and may also be used as the second gate electrode layer. In addition, the potential of the conductive layer can also be GND, 0V or floating.

Further, the conductive layer also has an electric field that shields the outside, that is, a function that does not cause an external electric field to act inside (including a circuit portion of the transistor) (in particular, an electrostatic shielding function that shields static electricity). By the shielding function of the conductive layer, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity.

The transistor 4010 provided in the pixel portion 4002 is electrically connected to the display element to constitute a display panel. The display element is not particularly limited as long as it can be displayed, and various display elements can be used.

Fig. 13A shows an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 13A, a liquid crystal element 4013 as a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Further, insulating films 4032 and 4033 serving as alignment films are provided to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is disposed on the side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 are laminated with the liquid crystal layer 4008 interposed therebetween.

Further, the spacer 4035 is a column spacer obtained by selectively etching the insulating film, and it is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. In addition, a spherical spacer can also be used.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. The liquid crystal material (liquid crystal composition) exhibits a cholesterol phase, a smectic phase, a cubic phase, a chiral nematic phase, and homogeneous in accordance with conditions.

Further, as the liquid crystal layer 4008, a liquid crystal composition exhibiting a blue phase without using an alignment film may be used. At this time, the liquid crystal layer 4008 is in contact with the first electrode layer 4030 and the second electrode layer 4031. The blue phase is a kind of liquid crystal phase, and refers to a phase which occurs immediately before the temperature of the liquid crystal of the cholesterol phase rises from the cholesterol phase to the homogeneous phase. The blue phase can be exhibited using a liquid crystal composition in which a liquid crystal and a chiral agent are mixed. In addition, in order to increase the temperature range in which the blue phase is exhibited, a polymerizable monomer, a polymerization initiator, or the like is added to the liquid crystal composition exhibiting a blue phase, and a polymer stabilization treatment is performed to form a liquid crystal layer. Since the liquid crystal composition exhibiting a blue phase has a short response time and is optically isotropic, alignment processing is not required, and viewing angle dependence is small. In addition, since it is not necessary to provide an alignment film and no rubbing treatment is required, it is possible to prevent electrostatic breakdown due to the rubbing treatment, and it is possible to reduce malfunction or breakage of the liquid crystal display device in the process. Thereby, the productivity of the liquid crystal display device can be improved. In a transistor using an oxide semiconductor film, the electrical characteristics of the transistor may be significantly changed due to the influence of static electricity. Wai. Therefore, it is more effective to use a liquid crystal composition exhibiting a blue phase for a liquid crystal display device having a transistor using an oxide semiconductor film.

In addition, the inherent resistance of the liquid crystal material is 1 × 10 ⁹ Ω. Above cm, preferably 1 x 10 ¹¹ Ω. More than cm, more preferably 1 × 10 ¹² Ω. More than cm. In addition, the value of the intrinsic resistance in this specification is a value measured at 20 degreeC.

The size of the storage capacitor provided in the liquid crystal display device is set in consideration of the drain current or the like of the transistor disposed in the pixel portion so that the electric charge can be held for a predetermined period. The size of the storage capacitor can be set in consideration of the off current of the transistor or the like.

The transistor using the oxide semiconductor film used in the present embodiment can reduce the current value (off current value) in the off state. Therefore, the holding time of the electric signal such as the image signal can be prolonged, and the writing interval can be extended even when the power source is turned on. Therefore, the frequency of the update work can be reduced, so that the effect of suppressing the power consumption can be achieved.

Further, the transistor using the oxide semiconductor film used in the present embodiment can obtain high field-effect mobility, so that high-speed driving can be performed. For example, by using such a transistor capable of high-speed driving for a liquid crystal display device, a switching transistor of a pixel portion and a driving transistor for driving a circuit portion can be formed on the same substrate. In other words, since it is not necessary to separately use a semiconductor device formed of a germanium wafer or the like as the driving circuit, the number of components of the semiconductor device can be reduced. Further, in the pixel portion, a high-quality image can be provided by using a transistor capable of high-speed driving.

The liquid crystal display device can adopt TN (Twisted Nematic) Nematic mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB ( Optical Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti Ferroelectric Liquid Crystal) mode, and the like.

Further, a normally black liquid crystal display device such as a transmissive liquid crystal display device in a vertical alignment (VA) mode may be used. As the vertical alignment mode, for example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used. In addition, it can also be used for a VA liquid crystal display device. The VA type liquid crystal display device is one way of controlling the arrangement of liquid crystal molecules of the liquid crystal display panel. The VA type liquid crystal display device is a mode in which liquid crystal molecules are directed in a direction perpendicular to the panel when no voltage is applied. Further, a method called a multi-domain or multi-domain design in which a pixel is divided into several regions (sub-pixels) and molecules are respectively inverted in different directions can also be used.

Further, in the display device, an optical member (optical substrate) or the like of a black matrix (light shielding layer), a polarizing member, a phase difference member, an antireflection member, or the like is appropriately provided. For example, circular polarization using a polarizing substrate and a phase difference substrate can also be used. Further, as the light source, a backlight, a sidelight, or the like can also be used.

Further, as the display method in the pixel portion, a progressive scanning method, an interlaced scanning method, or the like can be employed. Further, as a color factor controlled in the pixel when color display is performed, it is not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W indicates white) or RGB may be added to one of yellow (yellow), cyan (myan), magenta (magenta) or the like. In addition, the size of the display area may be different depending on the point of each color factor. However, the disclosed invention is not limited to a display device for color display, but can also be applied to a display device for monochrome display.

Further, as the display element included in the display device, a light-emitting element utilizing electroluminescence can be applied. The light-emitting element utilizing electroluminescence is distinguished according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In the organic EL element, by applying a voltage to the light-emitting element, electrons and holes are respectively injected from a pair of electrodes to a layer including an organic compound having luminescence so that a current flows. Further, by recombination of these carriers (electrons and holes), the organic compound having luminescence forms an excited state, and emits light when returning from the excited state to the ground state. Due to this mechanism, such a light-emitting element is called a current-excitation type light-emitting element.

The inorganic EL elements are classified into a dispersion type inorganic EL element and a thin film type inorganic EL element according to their element structures. The dispersion-type inorganic EL element has a light-emitting layer in which particles of the light-emitting material are dispersed in a binder, and a light-emitting mechanism thereof is a donor-acceptor recombination type light emission using a donor energy level and a receptor energy level. The thin film type inorganic EL element has a structure in which a light emitting layer Sandwiched between the dielectric layers, and the dielectric layer sandwiching the light-emitting layer is sandwiched by the electrodes, and the light-emitting mechanism is a localized type light emission utilizing the electronic transition of the inner shell of the metal ions. In addition, here, the description will be made using an organic EL element as a light-emitting element.

In order to take out the light emission, at least one of the pair of electrodes of the light-emitting element may be made translucent. Further, a transistor and a light-emitting element are formed on the substrate, and the light-emitting element includes: a top emission that emits light from a surface opposite to the substrate; and a bottom emission that emits light from a surface on the substrate side; and The light-emitting element of the light-emitting double-sided emission structure is taken out from the surface on the side opposite to the substrate, and the light-emitting element of any of the above-described emission structures can be applied.

Fig. 13B shows an example of a light-emitting device (light-emitting panel) using a light-emitting element as a display element. The light emitting element 4513 as a display element is electrically connected to the transistor 4010 provided in the pixel portion 4002. Further, the structure of the light-emitting element 4513 is a laminated structure of the first electrode layer 4030, the electroluminescent layer 4511, and the second electrode layer 4031, but is not limited to the illustrated structure. The structure of the light-emitting element 4513 can be appropriately changed in accordance with the direction of light taken out from the light-emitting element 4513 and the like.

The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to form an opening portion on the first electrode layer 4030 using a photosensitive resin material, and to form a side wall of the opening portion as an inclined surface having a continuous curvature.

The electroluminescent layer 4511 may be formed using one layer or a laminate of a plurality of layers.

In order to prevent oxygen, hydrogen, moisture, carbon dioxide, or the like from entering the light-emitting element 4513, a protective film may be formed on the second electrode layer 4031 and the partition wall 4510. As the protective film, a tantalum nitride film, a hafnium oxynitride film, a DLC film, or the like can be formed. Further, a filling material 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005 and sealed. In order to prevent exposure to external air, it is preferable to use a protective film (adhesive film, ultraviolet curable resin film, or the like) having a high airtightness and low deaeration, and a covering material to be encapsulated (sealed).

As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin may be used, and PVC (polyvinyl chloride), an acrylic resin, a polyimide resin, an epoxy resin, an anthrone resin, or the like may be used. PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate). For example, nitrogen may be used as the filler.

In addition, if necessary, it is also possible to appropriately set such as a polarizing plate, or a circularly polarizing plate (including an elliptically polarizing plate), a phase difference plate (λ/4 plate, λ/2 plate), and a color filter on the emitting surface of the light emitting element. An optical film such as a sheet. Further, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. For example, anti-glare treatment can be performed, which is a treatment that reduces the glare by diffusing the reflected light by the unevenness of the surface.

Further, as the display device, electronic paper that drives electronic ink can also be provided. Electronic paper is also called an electrophoretic display device (electrophoretic display) and has the following advantages: the same legibility as paper; its power consumption is lower than that of other display devices; its shape is thin and light.

As an electrophoretic display device, various forms are conceivable, but It is a plurality of microcapsules including a first particle having a positive charge and a second particle having a negative charge dispersed in a solvent or a solute, and by applying an electric field to the microcapsule, the particles in the microcapsule are moved to each other to a relative Direction, to display only the color of the particles collected on one side. Additionally, the first or second particles comprise a dye that does not move when there is no electric field. Further, the color of the first particle is different from the color of the second particle (including colorless).

Thus, the electrophoretic display device is a display that uses a substance having a high dielectric constant to move to a high electric field region, a so-called dielectrophoretic effect.

The solvent in which the above microcapsules are dispersed is referred to as electronic ink, and the electronic ink can be printed on the surface of glass, plastic, cloth, paper, or the like. Further, color display can also be performed by using a color filter or a particle having a pigment.

Further, as the first particle and the second particle in the microcapsule, a material selected from the group consisting of a conductive material, an insulating material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, and a magnetophore A material in the material or a composite material of these materials.

Further, as the electronic paper, a display device using a twisting ball display method can also be applied. The rotating ball display manner is a method in which spherical particles respectively coated with white and black are disposed between the first electrode layer and the second electrode layer as electrode layers for display elements, and the first electrode layer and the second electrode are disposed. A potential difference is generated between the layers to control the direction of the spherical particles for display.

In addition, in FIGS. 12A to 12C and FIGS. 13A and 13B, As the first substrate 4001 and the second substrate 4006, a flexible substrate may be used in addition to the glass substrate. For example, a plastic substrate having light transmissivity or the like can be used. As the plastic, FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride) film, polyester film or acrylic film can be used. Further, a metal substrate (metal thin film) such as aluminum or stainless steel may be used if translucency is not required. For example, a sheet having a structure in which an aluminum foil is sandwiched by a PVF film or a polyester film can also be used.

The interlayer insulating film 4020 and the insulating film 4024 may be an oxide insulating film by a plasma CVD method, a sputtering method, or the like, and using yttrium oxide, yttrium oxynitride, aluminum oxide, aluminum oxynitride, lanthanum oxide, gallium oxide or A mixture of these materials is formed. Further, a nitride insulating film may be laminated on the oxide insulating film, and the nitride insulating film may be formed using tantalum nitride, hafnium oxynitride, aluminum nitride, aluminum oxynitride or a mixed material of these materials.

In the present embodiment, an aluminum oxide film is used as the insulating film 4024. The insulating film 4024 can be formed by a sputtering method or a plasma CVD method.

The aluminum oxide film provided as the insulating film 4024 on the oxide semiconductor film has a high blocking effect (blocking effect), that is, an effect of not allowing both impurities such as hydrogen and moisture and oxygen to pass through the film.

Therefore, the aluminum oxide film is used as a protective film, and impurities such as hydrogen and moisture which are a cause of variation in the process and after the production are prevented from being mixed into the oxide semiconductor film, and are prevented from being released from the oxide semiconductor film as an oxide semiconductor. The main component of the material is oxygen.

In addition, as the insulating film 4021 used as the planarization insulating film, it can be made An organic material having heat resistance such as an acrylic resin, a polyimide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. Further, in addition to the above organic materials, a low dielectric constant material (low-k material), a siloxane oxide resin, PSG (phosphorus phosphide), BPSG (boron bismuth glass), or the like may be used. Further, the insulating film may be formed by laminating a plurality of insulating films formed of these materials.

The method for forming the insulating film 4021 is not particularly limited, and may be a sputtering method, a SOG method, a spin coating method, a dipping method, a spray coating method, a droplet discharge method (inkjet method, etc.), or a printing method depending on the material thereof. The insulating film 4021 is formed by printing, offset printing, etc., a doctor blade, a roll coater, a curtain coater, a knife coater, or the like.

The display device performs display by transmitting light from a light source or a display element. Therefore, all of the thin films such as the substrate, the insulating film, and the conductive film provided in the pixel portion through which the light passes are translucent to the light in the wavelength region of visible light.

The first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, and the like) for applying a voltage to the display element may be based on a direction in which the light is extracted, a place where the electrode layer is provided, and an electrode layer. The pattern structure is selected to be light transmissive and reflective.

As the first electrode layer 4030 and the second electrode layer 4031, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, or indium can be used. A light-transmitting conductive material such as tin oxide, indium zinc oxide, indium tin oxide added with cerium oxide, or graphene.

In addition, the first electrode layer 4030 and the second electrode layer 4031 can be used. Tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), One or more of a metal such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), or silver (Ag), an alloy thereof, or a metal nitride thereof.

Further, the first electrode layer 4030 and the second electrode layer 4031 may be formed using a conductive composition including a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer composed of two or more of aniline, pyrrole and thiophene or a derivative thereof can be given.

Further, since the transistor is easily broken by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably constructed using a non-linear element.

As described above, by applying the transistor shown in the above embodiment, it is possible to provide a semiconductor device having various functions.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Embodiment 6

By using the transistor exemplified in the first embodiment, it is possible to manufacture a semiconductor device having an image sensor function for reading information of a target.

FIG. 14A shows an example of a semiconductor device having an image sensor function. Fig. 14A is an equivalent circuit of the photo-inductor, and Fig. 14B is a view A cross-sectional view of a portion of a photoinductor.

One electrode of the photodiode 602 is electrically connected to the photodiode weight setting signal line 658, and the other electrode of the photodiode 602 is electrically connected to the gate of the transistor 640. One of the source and drain of transistor 640 is electrically coupled to photoinductor reference signal line 672, while the other of the source and drain of transistor 640 is electrically coupled to the source and drain of transistor 656. one of the. The gate of transistor 656 is electrically coupled to gate signal line 659, and the other of the source and drain of transistor 656 is electrically coupled to photoinductor output signal line 671.

Note that in the circuit diagram of the present specification, in order to make the transistor using the oxide semiconductor film clear at a glance, the symbol of the transistor using the oxide semiconductor film is represented as "OS". In FIG. 14A, the transistor 640 and the transistor 656 can be applied to the transistor shown in the above embodiment, which is a transistor using an oxide semiconductor film. In the present embodiment, an example in which a transistor having the same configuration as that of the transistor 440a shown in the first embodiment is applied is shown.

14B is a cross-sectional view showing the photodiode 602 and the transistor 640 in the photo-inductor, in which a photodiode 602 serving as a sensor is disposed on a substrate 601 (TFT substrate) having an insulating surface, and Transistor 640. A substrate 613 is provided on the photodiode 602 and the transistor 640 by using the adhesive layer 608.

An interlayer insulating film 632, an insulating film 633, and an interlayer insulating film 634 are provided on the transistor 640 provided on the insulating film 631. The photodiode 602 is disposed on the insulating film 633, and the photodiode 602 has the following The first semiconductor film 606a and the second semiconductor film 606b are laminated in this order from the side of the insulating film 633 between the electrode layers 641a and 641b formed on the insulating film 633 and the electrode layer 642 provided on the interlayer insulating film 634. And a third semiconductor film 606c.

Further, a light shielding film 650 is provided in a region overlapping the transistor 640.

The electrode layer 641b is electrically connected to the conductive layer 643 formed in the interlayer insulating film 634, and the electrode layer 642 is electrically connected to the conductive layer 645 via the electrode layer 641a. The conductive layer 645 is electrically connected to the gate electrode layer of the transistor 640, and the photodiode 602 is electrically connected to the transistor 640.

Here, a pin type photodiode in which a semiconductor film having a p-type conductivity type used as the first semiconductor film 606a and a high resistance semiconductor film (type I semiconductor film) serving as the second semiconductor film 606b are laminated is exemplified. A semiconductor film having an n-type conductivity as the third semiconductor film 606c.

The first semiconductor film 606a is a p-type semiconductor film, and may be formed of an amorphous germanium film containing an impurity element imparting p-type. The first semiconductor film 606a is formed by a plasma CVD method using a semiconductor material gas containing an impurity element belonging to Group 13 of the periodic table (for example, boron (B)). As the semiconductor material gas, decane (SiH ₄ ) can be used. Further, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ or the like can be used. In addition, a method of introducing an impurity element into the amorphous germanium film by a diffusion method or an ion implantation method after forming an amorphous germanium film containing no impurity element may also be used. It is preferable to carry out heating or the like after introducing an impurity element by ion implantation or the like to diffuse the impurity element. In this case, as a method of forming the amorphous germanium film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like can be used. The thickness of the first semiconductor film 606a is preferably set to 10 nm or more and 50 nm or less.

The second semiconductor film 606b is an I-type semiconductor film (essential semiconductor film), and may be formed of an amorphous germanium film. In order to form the second semiconductor film 606b, an amorphous germanium film is formed by a plasma CVD method using a semiconductor material gas. As the semiconductor material gas, decane (SiH ₄ ) can be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ or SiF ₄ may also be used. The second semiconductor film 606b may be formed by an LPCVD method, a vapor phase growth method, a sputtering method, or the like. The thickness of the second semiconductor film 606b is preferably set to 200 nm or more and 1000 nm or less.

The third semiconductor film 606c is an n-type semiconductor film, and may be formed of an amorphous germanium film containing an impurity element imparting an n-type. The third semiconductor film 606c is formed by a plasma CVD method using a semiconductor material gas containing an impurity element (for example, phosphorus (P)) belonging to Group 15 of the periodic table. As the semiconductor material gas, decane (SiH ₄ ) can be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ or SiF ₄ may also be used. In addition, a method of introducing an impurity element into the amorphous germanium film by a diffusion method or an ion implantation method after forming an amorphous germanium film containing no impurity element may also be used. It is preferable to carry out heating or the like after introducing an impurity element by ion implantation or the like to diffuse the impurity element. In this case, as a method of forming the amorphous germanium film, an LPCVD method, a vapor phase growth method, a sputtering method, or the like can be used. The thickness of the third semiconductor film 606c is preferably set to 20 nm or more and 200 nm or less.

Further, the first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c may be formed using a polycrystalline semiconductor or a semi-crystalline semiconductor (SAS) without using an amorphous semiconductor.

When considering Gibbs free energy, microcrystalline semiconductors belong to the intermediate metastable state between amorphous and single crystal. That is, the microcrystalline semiconductor is in a third state in which the free energy is stable, and has short-range order and lattice distortion. Further, the columnar or needle crystals grow in a normal direction with respect to the surface of the substrate. As a typical example of the microcrystalline semiconductor, the Raman spectrum shifts to the low wave number side of 520 cm ^-1 which represents the single crystal germanium. That is, the peak of the Raman spectrum of the microcrystalline germanium is between 520 cm ^-1 representing a single crystal germanium and 480 cm ^-1 representing an amorphous germanium. In addition, at least 1 at.% or more of hydrogen or halogen is included to terminate the dangling bonds. Further, by including a rare gas element such as helium, argon, neon or xenon, the lattice distortion is further promoted, and the stability is improved to obtain an excellent microcrystalline semiconductor film.

The microcrystalline semiconductor film can be formed by a high frequency plasma CVD method having a frequency of several tens of MHz to several hundreds of MHz or a microwave plasma CVD apparatus having a frequency of 1 GHz or more. Typically, the microcrystalline semiconductor film can be formed by diluting a ruthenium-containing compound such as SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ or the like with hydrogen. Further, in addition to the ruthenium-containing compound (for example, ruthenium hydride) and hydrogen, it may be diluted with one or more rare gas elements selected from the group consisting of ruthenium, argon, osmium, and iridium to form a microcrystalline semiconductor film. In the above case, the flow rate ratio of hydrogen is set to be 5 times or more and 200 times or less, preferably 50 times or more and 150 times or less, more preferably 100 times or less, of the compound containing ruthenium (for example, ruthenium hydride). . Further, a carbide gas such as CH ₄ or C ₂ H ₆ , a deuterated gas such as GeH ₄ or GeF ₄ , F ₂ or the like may be mixed into the gas containing ruthenium.

Further, since the mobility of the hole generated by the photoelectric effect is lower than the mobility of electrons, the pin type photodiode has better characteristics when the surface on the side of the p-type semiconductor film is used as a light receiving surface. Here, an example in which the photodiode 602 is converted into an electric signal from the surface of the substrate 601 on which the pin-type photodiode is formed is shown. Further, since the light from the side of the semiconductor film whose conductivity type is opposite to the side of the semiconductor film serving as the light receiving surface is interference light, it is preferable to use a conductive film having a light blocking property as the electrode layer. Further, the surface on the side of the n-type semiconductor film may be used as a light receiving surface.

By using an insulating material and using a sputtering method, a plasma CVD method, a SOG method, a spin coating method, a dipping method, a spray method, a droplet discharge method (inkjet method, etc.), a printing method (screen printing, offset printing) depending on the material. An insulating film 631, an interlayer insulating film 632, and an insulating film 633 can be formed by printing, etc., a doctor blade, a roll coater, a curtain coater, a knife coater or the like.

In the present embodiment, an aluminum oxide film is used as the insulating film 633. The insulating film 633 can be formed by a sputtering method or a plasma CVD method.

The aluminum oxide film provided as the insulating film 633 on the oxide semiconductor film has a high blocking effect (barrier effect), that is, an effect of not allowing both impurities such as hydrogen and moisture and oxygen to pass through the film.

Therefore, the aluminum oxide film is used as a protective film, and impurities such as hydrogen and moisture which are caused by variations in the process and after the production are prevented from being mixed into the oxide semiconductor film, and are prevented from being released from the oxide semiconductor film as the constituent oxide semiconductor. The main ingredient of the material is oxygen.

In the present embodiment, the transistor 640 is removed by chemical mechanical polishing treatment on the conductive film provided on the gate electrode layer, the insulating film and the sidewall insulating layer in the process, and the conductive film is separated to form a source electrode layer and Bipolar electrode layer.

Therefore, since the distance between the region (contact region) where the source electrode layer or the gate electrode layer is in contact with the oxide semiconductor film and the gate electrode layer can be shortened, the source electrode layer or the gate electrode layer is in contact with the oxide The electric resistance between the region (contact region) of the semiconductor film and the gate electrode layer is lowered, and the conduction characteristics of the transistor 640 can be improved.

Since the etching process using the photoresist mask is not used in the process of removing the conductive film on the gate electrode layer in the process of forming the source electrode layer and the gate electrode layer, precise processing can be accurately performed. Therefore, in the manufacturing process of the semiconductor device, the transistor 640 having a micro structure having a small variation in shape and characteristics can be manufactured at a high yield.

As the insulating film 631, the interlayer insulating film 632, and the insulating film 633, an inorganic insulating material can be used. For example, an oxide insulating film such as a hafnium oxide film, a hafnium oxynitride film, an aluminum oxide film or an aluminum oxynitride film, or an antimony nitride film, a hafnium oxynitride film, an aluminum nitride film or an aluminum nitride oxide film can be used. A single layer or a laminate of a nitride insulating film.

Further, as the interlayer insulating film 634, an insulating film which is used as a planarizing insulating film for reducing surface unevenness is preferably used. As the interlayer insulating film 634, for example, a heat-resistant organic insulating material such as a polyimide resin, an acrylic resin, a benzocyclobutene resin, a polyamide or an epoxy resin can be used. In addition to the above organic insulating material, a single layer or a laminate of a low dielectric constant material (low-k material), a siloxane oxide resin, PSG (phosphorus phosphide), BPSG (boron bismuth glass), or the like may be used. .

By detecting the light 622 incident on the photodiode 602, the information of the detection target can be read. Further, when reading the information of the detection target, a light source such as a backlight can be used.

As described above, it is possible to provide a semiconductor device that realizes miniaturization and high collectivization and imparts high electric characteristics, and a method of manufacturing the semiconductor device.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Embodiment 7

In the present embodiment, an electronic device according to one embodiment of the present invention will be described. Specifically, an electronic device in which a display panel or a light-emitting panel having the transistor described in the above embodiment is mounted will be described with reference to FIGS. 15A to 15F.

As an electronic device using a semiconductor device, for example, a television (also referred to as a television or a television receiver), a display for a computer or the like, a digital camera, a digital camera, a digital photo frame, and a mobile phone (also referred to as a mobile phone) can be cited. , mobile phone devices), portable game consoles, portable information terminals, audio reproduction devices, marble machines and other large game consoles. Specific examples of these electronic devices are shown in Figs. 15A to 15F.

Fig. 15A shows an example of a television set. In the television set 7100, the housing 7101 is assembled with a display portion 7103. Display by the display unit 7103 For example, a display panel can be used for the display portion 7103. Further, the structure in which the outer casing 7101 is supported by the bracket 7105 is shown here.

The operation of the television set 7100 can be performed by using an operation switch provided in the casing 7101 and a separately provided remote controller 7110. By using the operation keys 7109 provided in the remote controller 7110, the operation of the channel and the volume can be performed, and the image displayed on the display unit 7103 can be operated. Further, a configuration in which the display unit 7107 that displays information output from the remote controller 7110 is provided in the remote controller 7110 may be employed.

Further, the television set 7100 is configured to include a receiver, a data machine, and the like. A general television broadcast can be received by the receiver. Furthermore, by connecting the data machine to a wired or wireless communication network, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver or between receivers, etc.). Information communication.

Fig. 15B shows a computer including a main body 7201, a casing 7202, a display portion 7203, a keyboard 7204, an external connection port 7205, a pointing device 7206, and the like. In addition, the computer is manufactured by using a display panel for its display portion 7203.

Fig. 15C shows a portable game machine which is constituted by two outer casings of a casing 7301 and a casing 7302, and is openably and closably connected by a connecting portion 7303. The housing 7301 is assembled with a display portion 7304, and the housing 7302 is assembled with a display portion 7305. In addition, the portable game machine shown in FIG. 15C further includes a speaker portion 7306, a storage medium insertion portion 7307, an LED lamp 7308, an input unit (operation key 7309, connection terminal 7310, and sensor 7311 (including functions for measuring the following factors). : strength, position Shift, position, velocity, acceleration, angular velocity, number of revolutions, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow, humidity, slope, vibration , smell or infrared), microphone 7312), etc. Needless to say, the configuration of the portable game machine is not limited to the above configuration, and a display panel may be used in either or both of the display unit 7304 and the display unit 7305, and a configuration in which other accessory devices are appropriately provided may be employed. The portable game machine shown in FIG. 15C has the functions of reading out a program or data stored in a storage medium and displaying it on the display unit, and realizing information by wirelessly communicating with other portable game machines. Share. In addition, the function of the portable game machine shown in FIG. 15C is not limited thereto, and may have various functions.

Fig. 15D shows an example of a mobile phone. The mobile phone 7400 includes an operation button 7403, an external connection 埠 7404, a speaker 7405, a microphone 7406, and the like in addition to the display unit 7402 incorporated in the casing 7401. Further, the mobile phone 7400 is manufactured by using a display panel for its display portion 7402.

The mobile phone 7400 shown in FIG. 15D can also input information by touching the display portion 7402 with a finger or the like. Further, the display unit 7402 can be touched with a finger or the like to perform an operation such as making a call or making an e-mail.

The display portion 7402 has three main screen modes. The first is a display mode in which the display of the image is dominant, the second is an input mode in which the input of information such as characters is dominant, and the third is a display + input mode in two modes of the mixed display mode and the input mode.

For example, in the case of a phone call or an email, you can use The display unit 7402 is mainly used to input a character input mode of a character and input a character displayed on the screen. In this case, it is preferable to display a keyboard or a number button in most portions of the screen of the display portion 7402.

Further, by providing a detecting device having a sensor for detecting the inclination such as a gyroscope and an acceleration sensor inside the mobile phone 7400, it is possible to determine the direction (vertical or horizontal) of the mobile phone 7400 and automatically perform the screen of the display portion 7402. The switching of the display.

Further, switching of the screen mode is performed by touching the display portion 7402 or operating the operation button 7403 of the casing 7401. Alternatively, the screen mode may be switched in accordance with the type of the image displayed on the display portion 7402. For example, when the image signal displayed on the display unit is the data of the motion picture, the screen mode is switched to the display mode, and when the image signal displayed on the display unit is the text material, the screen mode is switched to the input mode.

Further, when the touch operation input of the display portion 7402 is not detected for a certain period of time by detecting the signal detected by the photo sensor of the display portion 7402 in the input mode, control can be performed to input the screen mode from the input. The mode is switched to the display mode.

The display portion 7402 can also be used as an image sensor. For example, by touching the display portion 7402 with the palm or the finger, a palm print, a fingerprint, or the like is photographed, and personal identification can be performed. Further, by using a backlight that emits near-infrared light or a light source for sensing that emits near-infrared light in the display portion, it is also possible to take a finger vein, a palm vein, or the like.

Fig. 15E shows an example of a flat computer. The flat computer 7450 includes a housing 7451L and a housing 7451R that are connected by a hinge 7544. Further, in addition to the operation button 7453, the left speaker 7455L, and the right speaker 7455R, an external connection 埠7456 (not shown) is provided on the side surface of the computer 7450. Further, by folding the hinge 7544 so that the display portion 7452L provided on the outer casing 7451L and the display portion 7452R provided on the outer casing 7451R are opposed to each other, the display portion can be protected by the outer casing.

The display portion 7452L and the display portion 7452R can display not only images but also information by touching them with a finger or the like. For example, the program can be launched by selecting an icon indicating the end of the installation by touching with a finger. Alternatively, the image may be enlarged or reduced by changing the spacing of the fingers that are in contact with the two portions of the displayed image. Alternatively, the image can be moved by moving a finger that is in contact with a portion of the displayed image. Alternatively, information may be input by causing them to display an image of the keyboard and touching with a finger to select the displayed character or symbol.

In addition, a gyroscope, an acceleration sensor, a GPS (Global Positioning System) receiver, a fingerprint sensor, and a camera may be installed in the computer 7450. For example, by setting a detecting device having a sensor that detects a tilt such as a gyroscope, an acceleration sensor, or the like, the direction (longitudinal or lateral direction) of the computer 7450 is determined, and the direction of the displayed image can be automatically switched.

In addition, the computer 7450 can be connected to the network. The computer 7450 can not only display information on the Internet, but also can be used as a terminal for remote control and other devices connected to the network.

Fig. 15F shows an example of a lighting device. In the lighting device 7500, the light-emitting panels 7503a to 7503d of one embodiment of the present invention are assembled in It is used as a light source in the outer casing 7501. The lighting device 7500 can be mounted on a ceiling or a wall or the like.

Further, since the light-emitting device of one embodiment of the present invention includes a film-shaped light-emitting panel, it is possible to realize a semiconductor device having a curved surface by attaching it to a substrate having a curved surface. Further, by arranging the light-emitting panel in a housing having a curved surface, an electronic device or a lighting device having a curved surface can be realized.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

Example 1

In the present embodiment, the transistor shown in Embodiment 1 was produced, and the cross-sectional observation of the transistor was performed.

As the transistor, the embodiment transistor 1 having the same structure as the transistor 440a shown in Figs. 1A and 1B was fabricated. A method of manufacturing the transistor 1 of the embodiment is shown below.

As the insulating film 11, a yttrium oxide film having a thickness of 100 mm was formed on the ruthenium substrate 10 by a sputtering method (film formation conditions: oxygen (oxygen is 50 sccm) atmosphere, pressure was 0.4 Pa, and power supply power (power output) was 5.0. kW, the distance between the substrate and the target is 60 mm, and the substrate temperature is 100 ° C).

As the oxide semiconductor film 12, an IGZO film having a thickness of 20 nm was formed on the hafnium oxide film by a sputtering method using an oxide target of In:Ga:Zn=3:1:2 [atomic ratio]. As a film formation condition, the following conditions were employed: an atmosphere of argon and oxygen (argon: oxygen = 30 sccm: 15 sccm), pressure It is 0.4 Pa, the power supply is 0.5 kW, and the substrate temperature is 200 °C.

Next, as a gate insulating film, a yttrium oxynitride film having a thickness of 20 nm was formed on the IGZO film by a CVD method (film formation conditions: SiH ₄ : N ₂ O = 1 sccm: 800 sccm, pressure: 40 Pa, RF power supply ( The power output is 150W, the power frequency is 60MHz, and the substrate temperature is 400°C.

A tungsten film having a thickness of 100 nm was formed on the gate insulating film by a sputtering method (film formation conditions: a pressure of 0.2 Pa under an atmosphere of argon (100 sccm), a power of 1 kW), and a tungsten film was formed by a CVD method. A yttrium oxynitride film having a thickness of 200 nm was laminated (film formation conditions: SiH ₄ : N ₂ O = 27 sccm: 1000 sccm, pressure 133.3 Pa, RF power supply 60 W, power supply frequency 13.56 MHz, substrate temperature 325 ° C).

The yttrium oxynitride film is etched by dry etching (etching conditions: etching gas (CHF ₃ : He: CH ₄ = 22.5 sccm: 127.5 sccm: 5 sccm), ICP power supply is 475 W, bias power is 300 W, pressure The insulating film 15 is formed to be 3.5 Pa.

Next, the tungsten film was etched by dry etching (etching conditions: etching gas (CF ₄ : Cl ₂ : O ₂ = 25 sccm: 25 sccm: 10 sccm), ICP power supply was 500 W, bias power was 100 W, and pressure was 1.0. Pa, the substrate temperature is 70 ° C) to form the gate electrode layer 14.

As the insulating film, a 70 nm yttrium oxynitride film was formed on the gate electrode layer 14 and the insulating film 15 by a CVD method (film formation conditions: SiH ₄ : N ₂ O = 1 sccm: 800 sccm, pressure: 40 Pa, RF power supply) (power supply output is 150 W, power supply frequency is 60 MHz, substrate temperature is 400 ° C), and the yttrium oxynitride film is etched by dry etching (etching conditions: etching gas (CHF ₃ : He = 56 sccm: 144 sccm), The ICP power supply was 25 W, the bias power was 425 W, the pressure was 7.5 Pa, and the substrate temperature was 70 ° C. The sidewall insulating layers 16a, 16b were formed. The gate insulating film is etched by using the gate electrode layer 14 and the sidewall insulating layers 16a and 16b as a mask to form the gate insulating film 13.

A tungsten film having a thickness of 30 nm is formed on the oxide semiconductor film 12, the gate insulating film 13, the sidewall insulating layers 16a and 16b, and the insulating film 15 by a sputtering method (film formation conditions: argon (80 sccm) atmosphere, pressure It is 0.8 Pa, the power supply is 1 kW, and the substrate temperature is 230 ° C).

Further, a yttrium oxynitride film having a thickness of 500 nm was formed on the tungsten film by a CVD method (film formation conditions: SiH ₄ : N ₂ O = 27 sccm: 1000 sccm, pressure 133.3 Pa, RF power supply 60 W, power supply frequency) It is 13.56 MHz and the substrate temperature is 325 ° C).

Next, the yttrium oxynitride film and the tungsten film are polished by a chemical mechanical polishing method (polishing conditions: rigid polyurethane polishing cloth, alkaline cerium-based slurry, slurry temperature at room temperature, polishing pressure of 0.08 MPa, polishing) The number of rotations (table/spindle) was 50 rpm/50 rpm, and the polishing time was 2 minutes), and the yttrium oxynitride film and the tungsten film on the gate electrode layer 14 were removed in such a manner that the insulating film 15 was exposed.

The yttrium oxynitride film is processed into the insulating film 18 by the polishing treatment, and the tungsten film is separated to form the source electrode layer 17a and the gate electrode layer 17b.

The embodiment transistor 1 was fabricated by the above process.

Cutting off the edge portion of the embodiment transistor 1 using scanning transmission electrons A cross-sectional observation of the transistor 1 of the example was carried out by a microscope (STEM: Scanning Transmission Electron Microscopy). In the present embodiment, the "ultra-thin film evaluation system HD-2300" (manufactured by Hitachi High-Tech Co., Ltd.) was used as the STEM. Figure 16 shows a cross-sectional STEM image of a transistor.

Fig. 16 is a cross-sectional STEM image of the transistor 1 of the embodiment in the longitudinal direction of the channel, and it was confirmed that the source electrode layer 17a and the gate electrode layer 17b were separated by the polishing treatment. The source electrode layer 17a and the drain electrode layer 17b are provided in contact with the side faces of the sidewall insulating layers 16a, 16b provided on the side faces of the gate electrode layer 14, and in the present embodiment, cover the sidewall insulating layers 16a, 16b. A position in the side that is slightly lower than the upper end. The shape of the source electrode layer 17a and the drain electrode layer 17b is different depending on the conditions of the polishing process of the separation conductive film, and as shown in this embodiment, it may be polished with the sidewall insulating layers 16a and 16b and the insulating film 15. The shape of the surface is retracted in the thickness direction.

In addition, in FIG. 16, the width of the lower bottom of the trapezoidal gate electrode layer 14 is about 382 nm, the width of the upper base is about 364 nm, and the width of the sidewall insulating layers 16a, 16b in the channel length direction is about 51.6 nm. The thickness of the insulating film 15 provided on the gate electrode layer 14 is about 44.1 nm, and the thickness from the source electrode layer 17a and the gate electrode layer 17b of the insulating film 18 in contact with the oxide semiconductor film 12 to the surface is about 139.8. Nm.

In the transistor 1 of the present embodiment, the conductive film provided on the gate electrode layer 14, the insulating film 15, and the sidewall insulating layers 16a, 16b is formed. The mechanical polishing treatment is removed to separate the conductive film to form the source electrode layer 17a and the drain electrode layer 17b.

Therefore, since the distance between the region (contact region) where the source electrode layer 17a or the gate electrode layer 17b contacts the oxide semiconductor film 12 and the gate electrode layer 14 can be shortened, the source electrode layer 17a or the drain electrode The electric resistance between the region (contact region) where the layer 17b is in contact with the oxide semiconductor film 12 and the gate electrode layer 14 is lowered, and the conduction characteristics of the transistor can be improved.

Since the etching process using the photoresist mask is not used in the process of removing the conductive film on the gate electrode layer 14 in the process of forming the source electrode layer 17a and the gate electrode layer 17b, precise processing can be accurately performed. . Therefore, in the process of the semiconductor device, it is possible to manufacture a transistor having a micro structure having a small variation in shape and characteristics at a high yield.

As described above, as shown in the present embodiment, a transistor having high electrical characteristics even with a micro structure can be provided at a high yield. Further, in the semiconductor device including the transistor, high performance, high reliability, and high productivity can be achieved.

Example 2

In the present embodiment, a transistor of one embodiment of the semiconductor device disclosed in the present specification is fabricated and evaluated for electrical characteristics.

As the transistor, an embodiment transistor 2 having the same structure as that of the transistor 340 shown in Fig. 17 was fabricated. A method of manufacturing the transistor 2 of the embodiment is shown below.

As the insulating film 336, a yttrium oxide film having a thickness of 300 nm was formed on the ruthenium substrate 300 by a sputtering method (film formation conditions: oxygen (oxygen is 50 sccm) atmosphere, pressure was 0.4 Pa, and power supply power (power output) was 1.5. kW, the distance between the substrate and the target is 60 mm, and the substrate temperature is 100 ° C).

The surface of the insulating film 336 was subjected to a polishing treatment by a chemical mechanical polishing method (polishing pressure was 0.08 MPa, polishing time was 0.5 minutes).

As the oxide semiconductor film, IGZO having a thickness of 10 nm is formed on the polished insulating film 336 by a sputtering method using an oxide target of In:Ga:Zn=3:1:2 [atomic ratio] membrane. As the film formation conditions, the following conditions were employed: an atmosphere of argon and oxygen (argon: oxygen = 30 sccm: 15 sccm), a pressure of 0.4 Pa, a power supply of 0.5 kW, and a substrate temperature of 200 °C.

The oxide semiconductor film is etched by dry etching (etching conditions: etching gas (BCl ₃ : Cl ₂ = 60 sccm: 20 sccm), ICP power supply 450 W, bias power 100 W, pressure 1.9 Pa) to form an island shape Oxide semiconductor film 303.

Next, as a gate insulating film, a hafnium oxynitride film having a thickness of 20 nm was formed on the island-shaped oxide semiconductor film 303 by a CVD method (film formation conditions: SiH ₄ : N ₂ O = 1 sccm: 800 sccm, pressure: 40 Pa) The RF power (power output) is 150W, the power frequency is 60MHz, and the substrate temperature is 400°C.

A tantalum nitride film having a thickness of 30 nm was formed on the gate insulating film by a sputtering method (film formation conditions: argon and nitrogen (argon: nitrogen = 50 sccm: 10 sccm), a pressure of 0.6 Pa, and a power supply of 1 kW. And thickness is A laminate of a 135 nm tungsten film (film formation conditions: a pressure of 2.0 Pa under a argon (100 sccm) atmosphere, and a power supply of 4 kW).

Next, a yttrium oxynitride film having a thickness of 200 nm was laminated on the tungsten film by a CVD method (film formation conditions: SiH ₄ : N ₂ O = 27 sccm: 1000 sccm, pressure 133.3 Pa, RF power supply 60 W, power supply frequency was 13.56MHz, substrate temperature is 325 ° C).

The yttrium oxynitride film is etched by dry etching (etching conditions: etching gas (CHF ₃ : He: CH ₄ = 22.5 sccm: 127.5 sccm: 5 sccm), ICP power supply is 475 W, bias power is 300 W, pressure An insulating film 313 is formed at 3.5 Pa.

The tantalum nitride film and the tungsten film are etched by dry etching (first etching condition: etching gas (CF ₄ : Cl ₂ : O ₂ = 25 sccm: 25 sccm: 10 sccm), ICP power supply is 500 W, and the bias power is 100W, pressure is 1.0Pa), (second etching condition: etching gas (Cl ₂ = 100sccm), power supply power is 2kW, bias power is 50W, pressure is 1.0Pa), (third etching condition: etching gas (Cl ₂ = 100 sccm), the power supply was 1 kW, the bias power was 25 W, and the pressure was 2.0 Pa), and the gate electrode layer 301 was formed.

Phosphorus (P) ions are implanted into the oxide semiconductor film 303 by ion implantation using the gate electrode layer 301 as a mask to form a low resistance region 304a and a low resistance region 304b. Further, as the implantation condition of the phosphorus (P) ions, the following conditions were employed: the acceleration voltage was 25 kV, and the dose was 1.0 × 10 ¹⁵ ions/cm ² .

As the insulating film, a 90 nm yttrium oxynitride film was formed on the gate electrode layer 301 and the insulating film 313 by a CVD method (film formation conditions: SiH ₄ : N ₂ O = 1 sccm: 800 sccm, pressure: 40 Pa, RF power supply) The power output frequency was 150 W, the power supply frequency was 60 MHz, and the substrate temperature was 400 ° C. The yttrium oxynitride film was etched by dry etching to form sidewall insulating layers 312a and 312b. The gate insulating film is etched by using the gate electrode layer 301 and the sidewall insulating layers 312a and 312b as a mask to form a gate insulating film 302. Further, as the etching conditions used when the sidewall insulating layers 312a and 312b and the gate insulating film 302 are formed, the following conditions are employed: etching gas (CHF ₃ : He = 30 sccm: 120 sccm), power supply power of 3 kW, and bias power of 200 W. The pressure is 2.0 Pa and the substrate temperature is -10 ° C).

A tungsten film having a thickness of 30 nm is formed on the oxide semiconductor film 303, the gate electrode layer 301, the sidewall insulating layers 312a and 312b, and the insulating film 313 by a sputtering method (film formation conditions: argon (80 sccm) atmosphere, pressure It is 0.8 Pa, the power supply is 1 kW, and the substrate temperature is 230 ° C).

Next, the tungsten film was etched by dry etching (etching conditions: etching gas (CF ₄ : Cl ₂ : O ₂ = 55 sccm: 45 sccm: 55 sccm), power supply power was 3 kW, bias power was 140 W, and pressure was 0.67 Pa. ) An island-shaped tungsten film is formed.

Next, as the insulating film, an aluminum oxide film having a thickness of 70 nm is formed on the oxide semiconductor film 303, the gate electrode layer 301, the sidewall insulating layers 312a and 312b, the insulating film 313, and the tungsten film by a sputtering method (film formation conditions). : Argon and oxygen (argon: oxygen = 25 sccm: 25 sccm), the pressure was 0.4 Pa, the power supply was 2.5 kW, the distance between the ruthenium substrate and the target was 60 mm, and the substrate temperature was 250 ° C).

Further, a cerium oxynitride film having a thickness of 430 nm was formed on the aluminum oxide film by a CVD method (film formation conditions: SiH ₄ : N ₂ O = 27 sccm: 1000 sccm, pressure 133.3 Pa, RF power supply 60 W, power supply) The frequency is 13.56 MHz and the substrate temperature is 325 ° C).

Next, the yttrium oxynitride film, the aluminum oxide film, and the tungsten film are polished by a chemical mechanical polishing method (polishing conditions: a rigid polyurethane polishing cloth, an alkaline cerium-based slurry, a slurry temperature of room temperature, and a polishing pressure of 0.08 MPa, the number of revolutions (table/spindle) at the time of polishing was 51 rpm/50 rpm), and the yttrium oxynitride film, the aluminum oxide film, and the tungsten film on the gate electrode layer 301 were removed so that the insulating film 313 was exposed.

The yttrium oxynitride film is processed into the insulating film 315 by the polishing treatment, the aluminum oxide film is processed into the insulating film 310, and the tungsten film is separated to form the source electrode layer 305a and the gate electrode layer 305b.

As the insulating film 307, a yttrium oxynitride film having a thickness of 400 nm is formed on the gate electrode layer 301, the insulating film 313, the source electrode layer 305a, the gate electrode layer 305b, the insulating film 310, and the insulating film 315 by a CVD method. (Film formation conditions: SiH ₄ : N ₂ O = 27 sccm: 1000 sccm, pressure 133.3 Pa, RF power supply 60 W, power supply frequency 13.56 MHz, substrate temperature 325 ° C).

An opening reaching the source electrode layer 305a and the drain electrode layer 305b is formed in the insulating film 307, the insulating film 315, and the insulating film 310 (first etching condition: etching gas (CHF ₃ : He = 7.5 sccm: 142.5 sccm), ICP The power supply is 475W, the bias power is 300W, the pressure is 5.5Pa, and the time is 192 seconds. The second etching condition is: etching gas (CHF ₃ : He = 7.5sccm: 142.5sccm), ICP power is 475W, bias The power is 150W, the pressure is 5.5Pa, and the time is 78 seconds).

An aluminum film having a thickness of 50 nm (film formation conditions: a pressure of 0.1 Pa in a argon (20 sccm atmosphere), a power supply of 12 kW) and a thickness of 100 nm was laminated in the opening by a sputtering method (film formation conditions: A titanium film having a thickness of 50 Å under a argon (50 sccm) atmosphere, a pressure of 0.4 kPa, a power supply of 1 kW) (film formation conditions: a pressure of 0.1 Pa in an atmosphere of argon (20 sccm), and a power supply of 12 kW).

The laminate of the titanium film, the aluminum film, and the titanium film is etched (etching conditions: etching gas (BCl ₃ : Cl ₂ = 60 sccm: 20 sccm), ICP power supply is 450 W, bias power is 100 W, pressure is 1.9 Pa), Wiring layers 335a, 335b are formed.

The transistor 340 is fabricated as the embodiment transistor 2 by the above process.

Further, in the embodiment transistor 2, the channel width (W) is set to 10 μm, and the gate electrode layer 301 and the source electrode layer 305a or the gate electrode layer 305b are in contact with the opening of the oxide semiconductor film 303. The distance is set to 0.07 μm.

The electrical characteristics of the embodiment transistor 2 were evaluated.

Fig. 18 is a view showing a gate voltage (Vg) - drain current (Id) characteristic when the gate voltage (Vd) of the transistor 2 of the embodiment 2 is 1 V and a gate voltage when the gate voltage (Vd) is 0.1 V ( Vg) - Deuterium current (Id) characteristics. In addition, the electrical characteristics of FIG. 18 are electrical characteristics when the channel length (L) in the transistor 2 of the embodiment is 0.35 μm, and the gate voltage is -4 V to The range of +4V is measured.

As shown in FIG. 18, the embodiment transistor 2 represents an electrical characteristic as a switching element. In the case where the gate voltage (Vd) is 1 V and the gate voltage is 2.7 V, the on-state current value of the embodiment transistor 2 is 45.1. μA, the threshold voltage (Vth) is -0.27 V, the subthreshold coefficient (S value) is 73.8 mV/dec., and in the case where the drain voltage (Vd) is 0.1 V, the field effect of the embodiment transistor 2 is The mobility was 3.0 cm ² /Vs. Further, the above-described on-current value, threshold voltage (Vth), sub-threshold coefficient (S value), and field-effect mobility are median values in the measurement data.

Further, regarding the electrical characteristics of the transistor 2 of the example, the in-plane variation at the time of performing 100 point measurement was evaluated.

Fig. 21 is a graph showing the normal probability of the on current when the drain voltage is 1 V and the gate voltage is 2.7 V. When the deviation of the on-current is expressed as 3σ, in the case where the channel length is 0.35 μm, 3σ is 16.5 μA, the percentage of 3σ divided by the median is 36.3%, and in the case of channel length 0.55 μm, 3σ is 11.8. The percentage of μA, 3σ divided by the median was 36.0%, and in the case of a channel length of 1 μm, 3σ was 6.4 μA, and the percentage of 3σ divided by the median was 30.0%.

Fig. 22 is a graph showing a normal probability of a threshold voltage when the drain voltage is 1V. When the deviation of the threshold voltage is expressed as 3σ, in the case where the channel length is 0.35 μm, 3σ is 0.22 V, and in the case where the channel length is 0.55 μm, 3σ is 0.26 V, and in the case where the channel length is 1 μm, 3σ is 0.12V.

From the results of Fig. 21 and Fig. 22, it is known that the on current and the threshold are For both voltages, the slope of the graph is large and the deviation is small.

As described above, it was confirmed that the transistor of the present embodiment has a sufficiently small electrical characteristic as a switching element even if it has a micro-channel structure having a channel length of 0.35 μm, and the variation in electrical characteristics is small.

As described above, as shown in the present embodiment, a transistor having high electrical characteristics even with a micro structure can be provided at a high yield. Further, in the semiconductor device including the transistor, high performance, high reliability, and high productivity can be achieved.

10‧‧‧矽 substrate

11‧‧‧Insulation film

12‧‧‧Oxide semiconductor film

13‧‧‧Gate insulation film

14‧‧‧ gate electrode layer

15‧‧‧Insulation film

16a‧‧‧Sidewall insulation

16b‧‧‧Sidewall insulation

17a‧‧‧Source electrode layer

17b‧‧‧汲 electrode layer

18‧‧‧Insulation film

106‧‧‧ Component isolation insulation

108‧‧‧gate insulating film

110‧‧‧gate electrode

116‧‧‧Channel formation area

120‧‧‧ impurity area

124‧‧‧Intermetallic compound zone

128‧‧‧Insulation

130‧‧‧Insulation

135‧‧‧Interlayer insulating film

136a‧‧‧Sidewall insulation

136b‧‧‧ sidewall insulation

137‧‧‧Insulation film

140‧‧‧Optoelectronics

142a‧‧‧electrode layer

142b‧‧‧electrode layer

144‧‧‧Oxide semiconductor film

146‧‧‧gate insulating film

148‧‧‧gate electrode

150‧‧‧Insulation film

152‧‧‧Insulation film

153‧‧‧ Conductive layer

156‧‧‧ wiring

160‧‧‧Optoelectronics

162‧‧‧Optoelectronics

164‧‧‧Capacitive components

172‧‧‧ Conductive layer

173‧‧‧Insulation film

174‧‧‧ Conductive layer

175a‧‧‧Sidewall insulation

175b‧‧‧ sidewall insulation

176‧‧‧Insulation film

180‧‧‧Insulation

185‧‧‧Substrate

191‧‧‧ Conductive layer

192‧‧‧ Conductive layer

193‧‧‧Insulation film

195‧‧‧Insulation film

196‧‧‧Insulation film

197‧‧‧ Conductive layer

250‧‧‧ memory unit

251‧‧‧Memory Cell Array

251a‧‧‧Memory Cell Array

251b‧‧‧Memory Cell Array

253‧‧‧ peripheral circuits

254‧‧‧Capacitive components

256‧‧‧Insulation film

258‧‧‧Insulation film

260‧‧‧ wiring

262‧‧‧ Conductive layer

300‧‧‧矽 substrate

301‧‧ ‧ gate electrode layer

302‧‧‧gate insulating film

303‧‧‧Oxide semiconductor film

305a‧‧‧Source electrode layer

305b‧‧‧汲 electrode layer

307‧‧‧Insulation film

310‧‧‧Insulation film

312a‧‧‧Sidewall insulation

312b‧‧‧Sidewall insulation

313‧‧‧Insulation film

315‧‧‧Insulation film

335a‧‧‧ wiring layer

335b‧‧‧ wiring layer

336‧‧‧Insulation film

340‧‧‧Optoelectronics

400‧‧‧Substrate

401‧‧‧ gate electrode layer

402‧‧‧gate insulating film

403‧‧‧Oxide semiconductor film

404a‧‧‧Low resistance zone

404b‧‧‧low resistance zone

405a‧‧‧Source electrode layer

405b‧‧‧汲 electrode layer

407‧‧‧Insulation film

409‧‧‧Channel formation area

410‧‧‧Insulation film

412a‧‧‧Sidewall insulation

412b‧‧‧ sidewall insulation

413‧‧‧Insulation film

415‧‧‧Interlayer insulating film

421‧‧‧Dopants

435a‧‧‧ wiring layer

435b‧‧‧ wiring layer

436‧‧‧Oxide insulating film

440a‧‧‧Optoelectronics

440b‧‧‧Optoelectronics

440c‧‧‧Optoelectronics

442‧‧‧gate insulating film

445‧‧‧Electrical film

446‧‧‧Insulation film

491‧‧‧Oxide semiconductor film

601‧‧‧Substrate

602‧‧‧Photoelectric diode

606a‧‧‧Semiconductor film

606b‧‧‧Semiconductor film

606c‧‧‧Semiconductor film

608‧‧‧ adhesive layer

613‧‧‧Substrate

631‧‧‧Insulation film

632‧‧‧Interlayer insulating film

633‧‧‧Insulation film

634‧‧‧Interlayer insulating film

640‧‧‧Optoelectronics

641a‧‧‧electrode layer

641b‧‧‧electrode layer

642‧‧‧electrode layer

643‧‧‧ Conductive layer

645‧‧‧ Conductive layer

650‧‧‧Shade film

656‧‧‧Optoelectronics

658‧‧‧Photoelectric pole weight setting signal line

659‧‧‧gate signal line

671‧‧‧Photoelectric detector output signal line

672‧‧‧Photoelectric detector reference signal line

801‧‧‧Optoelectronics

803‧‧‧Optoelectronics

804‧‧‧Optoelectronics

805‧‧‧Optoelectronics

806‧‧‧Optoelectronics

807‧‧‧X decoder

808‧‧‧Y decoder

811‧‧‧Optoelectronics

812‧‧‧Storage capacitor

813‧‧‧X decoder

814‧‧‧Y decoder

901‧‧‧RF circuit

902‧‧‧ analog baseband circuit

903‧‧‧Digital baseband circuit

904‧‧‧Battery

905‧‧‧Power circuit

906‧‧‧Application Processor

907‧‧‧CPU

908‧‧‧DSP

909‧‧ interface

910‧‧‧Flash memory

911‧‧‧ display controller

912‧‧‧Storage circuit

913‧‧‧ display

914‧‧‧Display Department

915‧‧‧Source Driver

916‧‧‧gate driver

917‧‧‧Voice Circuit

918‧‧‧ keyboard

919‧‧‧Touch sensor

950‧‧‧Storage circuit

951‧‧‧ memory controller

952‧‧‧ memory

953‧‧‧ memory

954‧‧‧ switch

955‧‧‧ switch

956‧‧‧Display Controller

957‧‧‧ display

1001‧‧‧Battery

1002‧‧‧Power circuit

1003‧‧‧Microprocessor

1004‧‧‧Flash memory

1005‧‧‧Voice Circuit

1006‧‧‧ keyboard

1007‧‧‧Storage circuit

1008‧‧‧ touch screen

1009‧‧‧ display

1010‧‧‧Display Controller

4001‧‧‧Substrate

4002‧‧‧Pixel Department

4003‧‧‧Signal line driver circuit

4004‧‧‧Scan line driver circuit

4005‧‧‧ Sealing material

4006‧‧‧Substrate

4008‧‧‧Liquid layer

4010‧‧‧Optoelectronics

4011‧‧‧Optoelectronics

4013‧‧‧Liquid crystal components

4015‧‧‧Connecting terminal electrode

4016‧‧‧Terminal electrode

4018‧‧‧FPC

4019‧‧‧ Anisotropic conductive film

4020‧‧‧Interlayer insulating film

4021‧‧‧Insulation film

4023‧‧‧Insulation film

4024‧‧‧Insulation film

4030‧‧‧electrode layer

4031‧‧‧electrode layer

4032‧‧‧Insulation film

4033‧‧‧Insulation film

4035‧‧‧ spacers

4050‧‧‧Shade film

4510‧‧‧ partition wall

4511‧‧‧Electroluminescent layer

4513‧‧‧Lighting elements

4514‧‧‧Filling materials

7100‧‧‧TV

7101‧‧‧Shell

7103‧‧‧Display Department

7105‧‧‧ bracket

7107‧‧‧Display Department

7109‧‧‧ operation keys

7110‧‧‧Remote control

7201‧‧‧ Subject

7202‧‧‧ Shell

7203‧‧‧Display Department

7204‧‧‧ keyboard

7205‧‧‧External connection埠

7206‧‧‧ pointing device

7301‧‧‧Shell

7302‧‧‧Shell

7303‧‧‧Connected section

7304‧‧‧Display Department

7305‧‧‧Display Department

7306‧‧‧Speaker section

7307‧‧‧Storage media insertion section

7308‧‧‧LED lights

7309‧‧‧ operation keys

7310‧‧‧Connecting terminal

7311‧‧‧Sensor

7312‧‧‧Microphone

7400‧‧‧Mobile Phone

7401‧‧‧ Shell

7402‧‧‧Display Department

7403‧‧‧ operation button

7404‧‧‧External connection埠

7405‧‧‧Speakers

7406‧‧‧Microphone

7450‧‧‧ computer

7451L‧‧‧Shell

7451R‧‧‧Shell

7452L‧‧‧Display Department

7452R‧‧‧Display Department

7453‧‧‧ operation buttons

7454‧‧‧Hinges

7455L‧‧‧left speaker

7455R‧‧‧right speaker

7456‧‧‧External connection埠

7500‧‧‧Lighting equipment

7501‧‧‧Shell

7503a‧‧‧Lighting panel

7503d‧‧‧Lighting panel

1A and 1B are plan and cross-sectional views illustrating one mode of a semiconductor device; FIGS. 2A to 2D are cross-sectional views illustrating one mode of a method of fabricating a semiconductor device; and FIGS. 3A to 3D are diagrams illustrating a semiconductor FIG. 4A to FIG. 4C are cross-sectional views illustrating one embodiment of a semiconductor device; and FIGS. 5A to 5C are cross-sectional views, plan views, and circuit diagrams showing one mode of the semiconductor device; FIG. And FIG. 6B is a circuit diagram and a perspective view showing one mode of the semiconductor device; FIGS. 7A and 7B are cross-sectional views showing one mode of the semiconductor device. And FIG. 8A and FIG. 8B are circuit diagrams showing one mode of the semiconductor device; FIG. 9 is a block diagram showing one mode of the semiconductor device; FIG. 10 is a block diagram showing one mode of the semiconductor device; A block diagram showing one mode of a semiconductor device; FIGS. 12A to 12C are plan views illustrating one mode of the semiconductor device; FIGS. 13A and 13B are cross-sectional views illustrating one mode of the semiconductor device; and FIGS. 14A and 14B are diagrams illustrating a semiconductor FIG. 15A to FIG. 15F are diagrams showing an electronic device; FIG. 16 is a view showing a cross-sectional STEM image of the transistor 1 of the embodiment; and FIG. 17 is a view showing the transistor 2 of the embodiment. Figure 18 is a plan view showing an electrical characteristic of the transistor 2 of the embodiment; Figures 19A and 19B are plan and cross-sectional views illustrating one mode of the semiconductor device; and Figures 20A and 20B are diagrams illustrating a semiconductor device. A plan view and a cross-sectional view of the mode; FIG. 21 is a view showing a normal probability diagram of the on current in the transistor 2 of the embodiment; and FIG. 22 is a normal diagram showing the threshold voltage in the transistor 2 of the embodiment. Rate chart.

400‧‧‧Substrate

401‧‧‧ gate electrode layer

402‧‧‧gate insulating film

403‧‧‧Oxide semiconductor film

404a‧‧‧Low resistance zone

404b‧‧‧low resistance zone

405a‧‧‧Source electrode layer

405b‧‧‧汲 electrode layer

407‧‧‧Insulation film

409‧‧‧Channel formation area

412a‧‧‧Sidewall insulation

412b‧‧‧ sidewall insulation

413‧‧‧Insulation film

415‧‧‧Interlayer insulating film

436‧‧‧Oxide insulating film

440a‧‧‧Optoelectronics

Claims (18)

A semiconductor device comprising: an oxide semiconductor film including a channel formation region on an oxide insulating film; a gate insulating film on the oxide semiconductor film; a gate electrode layer on the gate insulating film; the gate electrode a first insulating film on the layer; a sidewall insulating layer covering a side surface of the gate electrode layer and a side surface of the first insulating film; and a side surface of the oxide semiconductor film, the gate insulating film, and a side surface of the sidewall insulating layer a source electrode layer and a drain electrode layer contacting the source electrode layer and an interlayer insulating film on the gate electrode layer; and the first insulating film, the source electrode layer, the drain electrode layer, and the a sidewall insulating layer and a second insulating film contacting the interlayer insulating film thereon, wherein an upper surface of the source electrode layer and an upper surface of the drain electrode layer are lower than an upper surface of the first insulating film, and the sidewall insulating layer Above and above the interlayer insulating film, wherein the upper surface of the source electrode layer and the upper surface of the gate electrode layer are higher than the upper surface of the gate electrode layer, and wherein the oxide semiconductor film comprises doping Agent Domain, the region is not the gate electrode layer and to overlap and include the overlapping region of the gate insulating film. A semiconductor device according to claim 1, wherein the second insulating film comprises an aluminum oxide film. The semiconductor device according to claim 1, further comprising an aluminum oxide film between the source electrode layer and the interlayer insulating film and between the gate electrode layer and the interlayer insulating film. The semiconductor device according to claim 1, wherein the interlayer insulating film does not overlap with the channel formation region. The semiconductor device of claim 1, wherein the upper first region of the interlayer insulating film overlaps the oxide semiconductor film, wherein the upper second region of the interlayer insulating film does not overlap the oxide semiconductor film The overlapping, and the upper surface of the interlayer insulating film of the first region and the second region are flat surfaces. The semiconductor device according to claim 1, wherein the upper surface of the first insulating film, the upper surface of the sidewall insulating layer, and the upper surface of the interlayer insulating film are aligned with each other. A method of fabricating a semiconductor device, comprising the steps of: forming an oxide insulating film; forming an oxide semiconductor film on the oxide insulating film; forming a gate insulating film on the oxide semiconductor film; and forming the gate insulating film on the gate insulating film Forming a gate electrode layer and a first insulating film overlapping the oxide semiconductor film; and selectively introducing a dopant into the oxide semiconductor film by using the gate electrode layer and the first insulating film as a mask Forming a side covering the gate electrode layer on the gate insulating film and a sidewall insulating layer on a side surface of the first insulating film; forming a conductive film on the oxide semiconductor film, the gate insulating film, the gate electrode layer, the first insulating film, and the sidewall insulating layer; on the conductive film Forming an interlayer insulating film; and removing the interlayer insulating film and the conductive film by chemical mechanical polishing to expose the first insulating film on the gate electrode layer to form a source electrode layer and a drain electrode layer. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of forming a contact on the first insulating film, the source electrode layer, the gate electrode layer, the sidewall insulating layer, and the interlayer insulating film Their second insulating film. The method of manufacturing a semiconductor device according to claim 7, wherein an upper surface of the source electrode layer and an upper surface of the gate electrode layer are lower than an upper surface of the first insulating film, an upper surface of the sidewall insulating layer, and the interlayer The top of the insulating film. The method of manufacturing a semiconductor device according to claim 7 or 9, wherein the upper surface of the first insulating film, the upper surface of the sidewall insulating layer, and the upper surface of the interlayer insulating film are aligned with each other. A method of fabricating a semiconductor device, comprising the steps of: forming an oxide insulating film; forming an oxide semiconductor film on the oxide insulating film; forming a gate insulating film on the oxide semiconductor film; and forming the gate insulating film on the gate insulating film Forming a gate overlapping the oxide semiconductor film a pole electrode layer and a first insulating film; using the gate electrode layer and the first insulating film as a mask, selectively introducing a dopant into the oxide semiconductor film; forming a cover on the gate insulating film a sidewall insulating layer on a side surface of the gate electrode layer and a side surface of the first insulating film; on the oxide semiconductor film, the gate insulating film, the gate electrode layer, the first insulating film, and the sidewall insulating layer Forming a conductive film; forming an interlayer insulating film on the conductive film; and removing the interlayer insulating film and the conductive film by chemical mechanical polishing to expose the gate electrode layer to form a source electrode layer and a drain electrode layer . The method of manufacturing a semiconductor device according to claim 11, further comprising the steps of forming a first layer on the gate electrode layer, the source electrode layer, the gate electrode layer, the sidewall insulating layer, and the interlayer insulating film Two insulating film. The method of manufacturing a semiconductor device according to claim 11, wherein an upper surface of the source electrode layer and an upper surface of the gate electrode layer are lower than an upper surface of the sidewall insulating layer and an upper surface of the interlayer insulating film. The method of manufacturing a semiconductor device according to claim 11 or 13, wherein the upper surface of the sidewall insulating layer and the upper surface of the interlayer insulating film are aligned with each other. The method of manufacturing a semiconductor device according to claim 7 or 11, further comprising the steps of: forming an aluminum oxide film, Wherein the aluminum oxide film is disposed between the conductive film and the interlayer insulating film. The method of manufacturing a semiconductor device according to claim 7 or 11, wherein the surface of the oxide insulating film is planarized before the oxide semiconductor film is formed. The method of manufacturing a semiconductor device according to claim 7 or 11, wherein oxygen is introduced into the oxide insulating film before the sidewall insulating layer is formed. The method of manufacturing a semiconductor device according to claim 8 or 12, wherein the second insulating film comprises an aluminum oxide film.