TWI543331B - 半導體積體電路 - Google Patents
半導體積體電路 Download PDFInfo
- Publication number
- TWI543331B TWI543331B TW102124796A TW102124796A TWI543331B TW I543331 B TWI543331 B TW I543331B TW 102124796 A TW102124796 A TW 102124796A TW 102124796 A TW102124796 A TW 102124796A TW I543331 B TWI543331 B TW I543331B
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- Taiwan
- Prior art keywords
- wafer
- metal
- integrated circuit
- substrate
- semiconductor integrated
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 165
- 229910052751 metal Inorganic materials 0.000 claims description 376
- 239000002184 metal Substances 0.000 claims description 376
- 239000000758 substrate Substances 0.000 claims description 158
- 150000001875 compounds Chemical class 0.000 claims description 57
- 239000010949 copper Substances 0.000 claims description 50
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 47
- 229910052802 copper Inorganic materials 0.000 claims description 47
- 239000010931 gold Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 24
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 22
- 229910052737 gold Inorganic materials 0.000 claims description 22
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052732 germanium Inorganic materials 0.000 claims description 16
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 16
- 229920002577 polybenzoxazole Polymers 0.000 claims description 15
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 11
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 claims description 5
- 229910052594 sapphire Inorganic materials 0.000 claims description 5
- 239000010980 sapphire Substances 0.000 claims description 5
- 229910003468 tantalcarbide Inorganic materials 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims 6
- 230000000149 penetrating effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 300
- 235000012431 wafers Nutrition 0.000 description 291
- 230000008569 process Effects 0.000 description 18
- 238000013461 design Methods 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 238000012864 cross contamination Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000010897 surface acoustic wave method Methods 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910007637 SnAg Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
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Description
本發明係關於一種半導體積體電路晶片，其具有一表面金屬層及/或一背面金屬層，用以連接至外部電路；尤指一種具有複數個電子電路晶片相互堆疊之半導體積體電路，且其中至少有一個係為一化合物半導體單晶微波積體電路晶片。
化合物半導體單晶微波積體電路(monolithic microwave integrated circuits,MMIC)已被廣泛使用於射頻(RF)訊號發射器、接收器以及收發器等微波通訊元件，如行動電話及無線區域網路(LAN)模組等。這類射頻模組通常由許多電子電路零件所構成，如功率放大器(PA)、開關元件、濾波器以及控制元件等。其中有些電子電路零件已經被整合於單一晶片上。以化合物半導體之放大器電路而言(如包含異質接面雙極性電晶體(HBT)或高電子遷移率電晶體(HEMT)之放大器)，通常會使用HEMT元件來控制電晶體放大器偏壓條件，而這些元件與電路都可以積體整合於單一化合物半導體晶片上。例如，HBT功率放大器與HEMT控制電路就可以利用BiFET(或BiHEMT)製程將其積體整合於單一化合物半導體晶片上。另一個積體整合的例子則是將增強型HEMT元件與空乏型HEMT元件製作於單一晶片上，其中增強型HEMT元件係作為功率放大器的用途，而空乏型HEMT元件則是作為控制元件。化合物半導體放大器與一開關電路結合，其中該開關可依照功率位準、頻率帶、以及通訊模式用來改變射頻訊號路徑，亦通常被整
合於單一晶片中。化合物半導體放大器與一天線開關電路結合，其中該天線開關可用於切換天線與不同的Tx與Rx電路連接，亦常被整合於單一晶片中。化合物半導體HBT放大器通常操作於不同的偏壓條件，以確保元件在不同輸出功率與頻率範圍的保持最佳特性。由於輸入與輸出阻抗係為偏壓條件的函數，通常會引入一阻抗調節器，使偏壓條件改變時，仍可保持很好的阻抗匹配。阻抗調節器通常由電容器、電感器以及HEMT開關元件所構成，其中HEMT開關元件是被用來切換電容器與電感器的連接，進而改變整體的阻抗大小。然而隨著功能性的增加，高度積體整合的電路與元件也將造成製作成本增加及良率降低，將HBT與HEMT元件積體整合於單一晶片上時尤其如此。
為了降低製程成本，上述射頻模組中的電路元件可以分別製作於不同晶片上，甚至可以進一步結合其他如矽互補式金屬氧化物半導體(Si CMOS)積體電路晶片等。傳統的整合作法通常是將數個不同的晶片置於同一平面上並相互連接；然而此方式會隨晶片數目增加而使模組尺寸變大，同時長距離的相互連接也容易造成訊號損耗及相互干擾。例如，一般射頻模組即包含一HBT功率放大器MMIC晶片、一阻抗匹配及偏壓控制晶片、一天線開關晶片、以及一濾波電路晶片，而這些晶片均置於同一平面之模組基板上。
本發明提供一種化合物半導體積體電路晶片，係具有一表面金屬層及/或背面金屬層，用以連接外部電路。本發明之主要目在於提供一種化合物半導體積體電路晶片，其包含複數個相互堆疊之晶片，且其中至少有一個係為化合物半導體積體電路晶片；藉此，由堆疊晶片構成的半導體積體電路模組其面積將可大幅降低。相較於將模組中所有電路與零件製
作於單一晶片上，晶片模組化的設計亦可簡化晶片的製程步驟。同時，亦可縮短不同晶片之間或電路元件之間相互連接的距離，因而降低訊號損耗及相互干擾。藉由元件上方的金屬層，可以重新分佈或配置晶片之間的連接節點，因此晶片之間的連接節點不一定要位於同一垂直線上，大幅提高連接節點佈局設計的自由度。
為達上述目的，本發明提供一種半導體積體電路，其包含一第一晶片，且該第一晶片包含一化合物半導體積體電路。該第一晶片進一步包含：一基板、一介電層、一電子元件層、以及一第一金屬層。前述之介電層係形成於前述基板之上，且至少包含一介電層通孔貫穿該介電層之第一表面與第二表面。前述之第一金屬層主要係由銅所構成，且包含至少一第一金屬墊形成於該介電層第一表面之上並延伸進入至少一介電層通孔。前述之電子元件層係形成於前述基板與介電層之第二表面之間，包含至少一電子元件以及至少一第二金屬層，其中前述之電子元件包含至少一化合物半導體電子元件，至少一該第二金屬層連接於至少一該電子元件，至少一該第二金屬層係包含至少一第二金屬墊形成於一介電層通孔位於該介電層之第二表面之一端，並與延伸進入該介電層通孔之第一金屬層形成電性接觸，。所有與化合物半導體電子元件所接觸之第二金屬層主要係由金所構成。其中該第一金屬層係以三維方式分佈於電子元件層中至少一個電子元件上方，而至少一個第一金屬墊係透過該第一金屬層延伸進入至少其中一個介電層通孔而電性連接於該介電層通孔另一側之第二金屬墊中之至少一個。
本發明進一步提供一種半導體積體電路，其包含一上述之第一晶片以及一第二晶片，且該第二晶片係包含一電子電路。在此定義第一晶片中之介電層的第一表面為該第一晶片之表面，而該基板相對於該介電
層之表面則定義為第一晶片之背面。前述之第二晶片係堆疊於第一晶片之表面上，並且電性連接至第一晶片上之至少一第一金屬墊。第一金屬層係以三維方式分佈於電子元件層中至少一個電子元件上方，為使兩個晶片上之接點對齊，至少一個第一金屬墊係透過該第一金屬層延伸進入至少其中一個介電層通孔而電性連接於該介電層通孔另一側之第二金屬墊中之至少一個。
本發明亦提供另一種半導體積體電路，其包含一第一晶片以及一第二晶片，其中該第一晶片包含一化合物半導體積體電路，而第二晶片包含一電子電路。該第一晶片進一步包含：一基板、一介電層、一電子元件層、一第一金屬層以及一第三金屬層。前述之基板包含至少一基板通孔，且貫穿該基板之第一表面與第二表面。前述之介電層係形成於該基板之第一表面上，且包含至少一介電層通孔，貫穿該介電層之第一表面與第二表面。前述之第一金屬層主要係由銅所構成，且包含至少一第一金屬墊形成於該介電層之第一表面上並且延伸進入至少一介電層通孔；前述之電子元件層係形成於該基板第一表面與該介電層第二表面之間，包含至少一電子元件以及至少一第二金屬層；其中該電子元件包含至少一化合物半導體電子元件，至少一該第二金屬層連接於至少一該電子元件，至少一該第二金屬層係包含至少一第二金屬墊形成於一介電層通孔位於該介電層之第二表面之一端，並與前述之延伸進入該介電層通孔之第一金屬層形成電性接觸。至少一前述該第二金屬層包含至少一第三金屬墊形成基板通孔位於該基板之第一表面之一端。所有與該化合物半導體電子元件所接觸之第二金屬層主要係由金所構成。前述之第三金屬層包含至少一第四金屬墊形成於該基板之第二表面且延伸進入至少一基板通孔，藉此與位於基板通孔另一側之第三金屬墊形成電性接觸。在此定義前述介電層的第一表面為第一
晶片之表面，而前述基板的第二表面則定義為第一晶片之背面。前述之第二晶片係堆疊於第一晶片之背面，並且電性連接至第一晶片之至少一第四金屬墊。第三金屬層係以三維方式分佈於電子元件層中至少一個電子元件下方，為使兩個晶片上之接點對齊，至少一個第四金屬墊係透過該第三金屬層延伸進入至少其中一個介電層通孔而電性連接於該介電層通孔另一側之第三金屬墊中之至少一個。
本發明亦提供另一種半導體積體電路，其包含一第一晶片以及一第二晶片，其中該第一晶片包含一化合物半導體積體電路，而該第二晶片包含一電子電路。該第一晶片進一步包含：一基板、一電子元件層以及一第三金屬層。前述之基板包含至少一基板通孔，且貫穿該基板之第一表面與第二表面。前述之電子元件層係形成於該基板第一表面，包含至少一電子元件以及至少一第二金屬層，其中前述至少一電子元件中包含至少一化合物半導體電子元件，至少一該第二金屬層連接於至少一該電子元件，至少一該第二金屬層係包含至少一第三金屬墊形成於一基板通孔位於該基板之第一表面之一端。前述之第三金屬層包含至少一第四金屬墊形成於該基板之第二表面且延伸進入至少一基板通孔，藉此與在基板通孔另一側之第三金屬墊形成電性接觸。該第三金屬墊係透過第二金屬層，直接或間接地與至少一電子元件相連接。該第三金屬墊也可以連接到一第五金屬墊；其中第五金屬墊係由該至少一第二金屬層所構成，且位於該電子元件層與基板相對之表面或其鄰近區域。前述之第五金屬墊可連接到其他電路晶片或電子零件模組。在此定義該第一晶片上電子元件層與基板相對之表面為該第一晶片之表面，而該基板的第二表面則定義為第一晶片之背面。前述之第二晶片係堆疊於第一晶片之背面，並且電性連接至第一晶片之至少一第四金屬墊。為使兩個晶片上之接點對齊，前述之至少一第四金屬墊
透過一第三金屬層延伸進入一基板通孔而電性連接於該基板通孔另一側之三金屬墊，並且進一步電性連接至電子元件層中之至少一電子元件。
本發明之另一目的在於提供一種半導體積體電路，其中一晶片之背面金屬層可以用以形成一電感器。前述之位於晶片背面之電感器可以縮小整體電路所佔據的面積，進而所小晶片整體尺寸。且當背面金屬層主要係由銅所構成時，晶片背面將可以製作出具有高品質因子(quality factor)的電感器。
為達上述目的，本發明提供另一種半導體積體電路，其進一步包含一電感器於前述之半導體積體電路中。前述之電感器係由第三金屬層所構成，形成於第一晶片基板之第二表面上，且位於至少一電子元件之上。該電感器係電性連接於第一晶片、第二晶片或同時電性連接於第一及第二晶片。
於實施時，前述之第二金屬層主要係由金(Au)所構成。
於實施時，前述第一晶片之基板係由砷化鎵(GaAs)所構成。
於實施時，前述之介電層係由介電物質聚苯噁唑(Polybenzoxazole,PBO)所構成。
於實施時，前述之介電層厚度係等於或大於10μm。
於實施時，前述之第三金屬層主要係由銅(Cu)所構成。
於實施時，前述之第一晶片係包含一異質接面雙極性電晶體(HBT)單晶微波積體電路(MMIC)或一高電子遷移率電晶體(HEMT)MMIC。
前述之第一晶片係包含一氮化鎵(GaN)場效電晶體(FET)。
於實施時，前述之第一晶片係包含一功率放大器MMIC。
於實施時，前述之第二晶片係包含：一偏壓控制電路，用以
控制第一晶片中至少一電子元件之偏壓條件；一開關電路，用以控制第一晶片訊號路徑；一天線開關電路，用以連接第一晶片中功率放大器輸出端至天線；一阻抗調節電路，用以調節阻抗大小，並使其隨第一晶片中功率放大器之偏壓條件及工作頻率而改變；以及一由被動元件所構成之阻抗匹配電路，用以匹配第一晶片中功率放大器之輸入與/或輸出端之阻抗。
於實施時，前述之第二晶片係包含一化合物半導體MMIC。
於實施時，前述之第二晶片係包含一矽互補式金屬氧化物半導體(Si CMOS)積體電路。
於實施時，前述之第二晶片係包含至少一被動元件積體整合於同一基板，且該基板係由矽、砷化鎵、或玻璃所構成。
於實施時，前述之第二晶片係包含一濾波器。
為對於本發明之特點與作用能有更深入之瞭解，茲藉實施例配合圖式詳述於後。
90‧‧‧模組基板
91‧‧‧模組金屬墊
100‧‧‧第一晶片
101‧‧‧第一晶片背面
102‧‧‧第一晶片表面
103,203‧‧‧MMIC
104,204,404‧‧‧金屬連結線
110,210‧‧‧基板
111‧‧‧基板第一表面
112‧‧‧基板第二表面
113‧‧‧基板通孔
120‧‧‧電子元件層
121,221‧‧‧電子元件
122,222‧‧‧電容器
123,223‧‧‧電阻器
130‧‧‧介電層
131‧‧‧介電層第一表面
132‧‧‧介電層第二表面
133,233‧‧‧介電層通孔
140,240‧‧‧第一金屬層
141‧‧‧第一金屬墊
150‧‧‧第二金屬層
151‧‧‧第二金屬墊
161‧‧‧第三金屬墊
170‧‧‧第三金屬層
171‧‧‧第四金屬墊
172‧‧‧電感器
180,280‧‧‧金屬凸塊
181‧‧‧第五金屬墊
191‧‧‧第四金屬墊
200‧‧‧第二晶片
270‧‧‧背面金屬層
271‧‧‧接觸金屬墊
300‧‧‧第三晶片
400‧‧‧第四晶片
第1圖係為本發明所提供之半導體積體電路之一種實施例之剖面結構示意圖，其中第二晶片係堆疊於第一晶片之表面。
第2圖係為本發明所提供之半導體積體電路之一種實施例之剖面結構示意圖，其中第二晶片係堆疊於第一晶片之背面。
第3圖係為本發明所提供之半導體積體電路之另一實施例之剖面結構示意圖，其中第二晶片係堆疊於第一晶片之背面。
第4圖係為本發明所提供之半導體積體電路之另一實施例之剖面結構示意圖，其中一電感器係形成於第一晶片之背面。
第5圖至第23圖係對應於本發明所提供之第1實施例至第
19實施例之剖面結構示意圖。
第24圖係為本發明所提供之種實施例中，晶片包含一化合物半導體積體電路晶片之剖面結構示意圖。
第24A、24B圖係為本發明所提供之實施例中，金屬層之剖面結構示意圖。
第24圖係為根據本發明之半導體積體電路之一種實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100，且該第一晶片係包含一化合物半導體積體電路。該第一晶片進一步包含：一基板110、一介電層130、一電子元件層120、以及一第一金屬層140。前述之介電層130係形成於基板110之上，且至少包含一介電層通孔133貫穿該介電層130之第一表面131與第二表面132。前述之電子元件層120係形成於基板110與介電層130之第二表面之間。電子元件層120包含至少一化合物半導體電子元件121以及至少一第二金屬層150。第一金屬層140形成至少一第一金屬墊於介電層第一表面131之上，且延伸進入至少一介電層通孔133。在該至少一第二金屬層150當中，其中至少一第二金屬層係電性連接於至少一電子元件121。在該至少一第二金屬層150當中，其中至少一第二金屬層係包含至少一第二金屬墊151形成於一介電層通孔133位於該介電層之第二表面132之一端，並與延伸進入該介電層通孔133之第一金屬層140形成電性接觸。如圖24A與24B所示，第一金屬層140或第二金屬層150下方可以包含一層或複數層底層結構作為附著層(adhesion layer)、擴散位障層(diffusion barrier layer)以及/或電鍍之種子層(seed layer)。該第一金屬層140或第二金屬層150上方亦可以進一步包含一層或複數層之上層結構作為金屬之保護層，可用來防止金屬潮濕或氧化，或提供形成於其上之材料較佳之附著力。
以銅金屬層為例，其底層結構可以由Ti、TiW或Pt等金屬層所構成，而上層結構則可以由金所構成。若以金之金屬層為例，其底層結構可以由Ti或Pd等金屬所構成，而上層結構則可以由Ti等金屬所構成。藉由形成金屬凸塊280於第一金屬墊141之上，該第一晶片100即可透過凸塊接合(bump bonding)方式電性連接至其他電子電路。除了透過金屬凸塊280，亦可利用線接合(wire bonding)方式使第一金屬墊141透過金屬連接線與其他電子電路達到電性連接。例如，該第一晶片100可以直接堆疊於一個模組基板上，並透過凸塊接合或線接合方式，使第一金屬墊141與基板模組上的金屬墊形成電性連接。第一金屬層140係以三維方式分佈於電子元件層120中至少一個電子元件121上方，而至少一個第一金屬墊141係透過第一金屬層140延伸進入至少其中一個介電層通孔133而電性連接於該介電層通孔另一側之第二金屬墊151，因此第一金屬墊141可設置於一較佳的位置已連接於其他電路。
第1圖係為根據本發明之半導體積體電路之一種實施例之剖面結構示意圖。該半導體積體電路包含前述之第一晶片100以及一第二晶片200，且該第二晶片係包含一電子電路。在此定義該第一晶片100上之介電層的第一表面131為該第一晶片表面102，而該基板相對於該介電層之表面則定義為第一晶片背面101。第二晶片200係堆疊於第一晶片表面102上，並且透過金屬凸塊280電性連接於至少一第一金屬墊141。藉此，兩垂直堆疊之第一晶片與第二晶片透過電性連接而整合成為單一電路。第一金屬層140係以三維方式分佈於電子元件層120中至少一個電子元件121上方，為使第一晶片100與第二晶片200上之接點透過金屬凸塊280對齊，至少一個第一金屬墊141係透過第一金屬層140延伸進入至少其中一個介電層通孔133而電性連接於該介電層通孔另一側之第二金屬墊151。
第2圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200，且該第一晶片100包含一化合物半導體積體電路，而第二晶片200包含一電子電路。該第一晶片100進一步包含：一基板110、一電子元件層120、一介電層130、一第一金屬層140以及一第三金屬層170。基板110包含至少一基板通孔113，且貫穿該基板之第一表面111與第二表面112。介電層130係形成於基板之第一表面111，且至少包含一介電層通孔133，並貫穿該介電層之第一表面131與第二表面132。電子元件層120係形成於基板110與介電層130之間，包含至少一電子元件以及至少一第二金屬層150，其中至少一電子元件中包含至少一化合物半導體電子元件121。第一金屬層140主要由銅所構成，且形成至少一第一金屬墊141於介電層之第一表面131上並且延伸進入至少一介電層通孔133。至少一第二金屬層150係電性連接於至少一化合物半導體電子元件121，且所有與化合物半導體電子元件121接觸之第二金屬層150主要由金所構成。所有第二金屬層當中，其中至少一第二金屬層150係包含至少一第二金屬墊151形成於一介電層通孔133位於該介電層之第二表面132之一端，並與延伸進入該介電層通孔133之第一金屬層140形成電性接觸。第三金屬層170係形成於基板之第二表面112，其至少包含一第四金屬墊171，且延伸進入至少一基板通孔113。第二金屬層150中，至少其中之一包含至少一第三金屬墊161形成於該基板通孔113與第四金屬墊171相對之一端，並與延伸進入該基板通孔113之第三金屬層170形成電性接觸。如前所述，第一金屬層140、第二金屬層150、以及第三金屬層170下方可以包含一層或複數層底層結構；而上方亦可以進一步包含一層或複數層之上層結構。在此定義第一晶片100上介電層的第一表面131為該第一晶片表面102，而基板110的第二表面112則定義為第一晶
片背面101。在本實施例中，第一晶片100係表面朝下，第二晶片200則堆疊堆疊於第一晶片100之背面101，並透過金屬凸塊280電性連接到至少一第四金屬墊171。藉此，垂直堆疊之第一晶片與第二晶片可以透過電性連接而整合成為單一電路。每一個第一金屬墊141均進一步連接至一金屬凸塊180，以供與其他電路晶片或模組電性連接。第一金屬層140係以三維方式分佈於電子元件層120中至少一個電子元件121上方，為使第一晶片100與第二晶片200上之接點透過金屬凸塊280對齊，至少一個第一金屬墊141係透過第一金屬層140延伸進入至少其中一個介電層通孔133而電性連接於該介電層通孔另一側之第二金屬墊151。
第3圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200，該第一晶片100包含一化合物半導體積體電路，而第二晶片200包含一電子電路。該第一晶片100進一步包含：一基板110、一電子元件層120、以及一第三金屬層170。基板110包含至少一基板通孔113，且貫穿基板之第一表面111與第二表面112。電子元件層120係形成於基板110之第一表面111，包含至少一電子元件以及至少一第二金屬層150。第三金屬層170係形成於基板之第二表面112，其包含至少一第四金屬墊171，且延伸進入至少一基板通孔113。第二金屬層150中，至少其中之一包含至少一第三金屬墊161形成於基板通孔113上方與第四金屬墊171相對之一端，並與延伸進入該基板通孔113之第三金屬層170形成電性接觸。第三金屬墊161係透過第二金屬層150，直接或間接地與至少一電子元件121相連接；第三金屬墊161也可以連接到一第五金屬墊181，其中第五金屬墊181係由該至少一第二金屬層150所構成，且位於電子元件層120與基板相對之表面或其鄰近區域。如前所述，第二金屬層150以及第三金屬層170下方可以包含一層或
複數層底層結構，而上方亦可以進一步包含一層或複數層之上層結構。在此定義該第一晶片上電子元件層相對於該介電層的表面為該第一晶片表面102，而基板110的第二表面112則定義為第一晶片背面101。在本實施例中，第一晶片100係表面朝下，第二晶片200則堆疊堆疊於第一晶片100之背面101，並透過金屬凸塊280電性連接到至少一第四金屬墊171。藉此，垂直堆疊之第一晶片與第二晶片可以透過電性連接而整合成為單一電路。在第一晶片表面102附近的第五金屬墊181乃進一步連接至一金屬凸塊180，供與其他電路晶片或模組電性連接。第三金屬層170係以三維方式分佈於電子元件層120中至少一個電子元件121下方，為使第一晶片100與第二晶片200上之接點對齊，至少一個第四金屬墊171係透過第三金屬層170延伸進入至少其中一個基板通孔113而電性連接於該基板通孔另一側之第三金屬墊161。
在前述之實施例中，第四金屬層170可以形成一被動元件，如一電感器。第4圖係為本發明之半導體積體電路之另一實施例之剖面結構示意圖，其中第四金屬層170於基板之第二表面112形成一電感器172。該電感器172係以三維的方式配置於至少一電子元件121之上，且電性連接於第一晶片100。電感器172亦可電性連接至第二晶片或同時電性連接於第一及第二晶片。
在前述之實施例中，第一晶片100係為一化合物半導體積體電路晶片，而第二晶片200則可以是一化合物半導體、半導體或其他種類的積體電路晶片。第一晶片之基板材料可以是砷化鎵(GaAs)、矽(Si)、炭化矽(SiC)、藍寶石(sapphire)或氮化鎵(GaN)。當第二晶片為半導體積體電路晶片時，其基板材料亦可為砷化鎵(GaAs)、矽(Si)、炭化矽(SiC)、藍寶石(sapphire)或氮化鎵(GaN)。第一晶片之介電層係由介電物質所構成，以聚苯噁唑
(Polybenzoxazole,PBO)構成尤佳。由於第一金屬層以三維方式分布於介電層上方並延伸進入介電層通孔以連接通孔另一端之第二金屬墊，介電層之較佳厚度係等於或大於10μm，以降低第一金屬層對位於介電層下方的電子元件特性的影響。前述之電子元件層係為一複合層，其包含一化合物半導體元件層以及一頓化層(passivation layer)。該頓化層材料係為介電質材料，且由氮化矽(SiN)構成尤佳，具有絕緣以及保護電子元件的功能。前述之化合物半導體元件可以是異質接面雙極性電晶體(HBT)或高電子遷移率電晶體(HEMT)，該化合物半導體元件亦可為氮化鎵(GaN)場效電晶體(FET)。第一晶片中供電性連接之金屬層可分為直接與電子元件接觸之金屬層以及未直接與電子元件接觸之金屬層。與化合物半導體電子元件直接接觸的第二金屬層主要係由金(Au)所構成，且必須不含或只含有極微量的銅成分，以確保電子元件不被銅所汙染。此外亦可讓所有第二金屬層均主要由金(Au)所構成，且不含或只含有極微量的銅成分，如此一來，電子元件層可就可以利用完全不含銅金屬製程的的前段(front-end)製程來完成，藉此讓表面製程排除銅交叉汙染的問題，以確保元件之特性及製程穩定性。至於未直接與化合物半導體電子元件接觸之金屬層，如第一金屬層以及第三金屬層係間接透過第二金屬層與元件形成電性接觸，其金屬材料可以由銅(Cu)所構成以降低製作成本。銅金屬層的形成可於後段(back-end)製程中完成，藉此避免前段製程受到銅汙染。第一金屬層之銅金屬厚度以等於或大於3μm為較佳。
根據本發明所提供之其他實施例依序說明如下：
第5圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HBT功率放大器
MMIC 203。該HEMT MMIC係形成於一GaAs基板110上。於基板110上具有一電子元件層120，其包含一系列由偽晶型HEMT(pHEMT)元件121所構成的偏壓控制電路、開關電路、以及邏輯電路。該HEMT MMIC係為一控制電路，用以控制HBT功率放大器之偏壓條件，以及/或控制HBT功率放大器中射頻訊號的路徑。該電子元件層120進一步包含一層或複數層的氮化矽(SiN)，可用來絕緣或鈍化半導體電子元件。在該HEMT MMIC上係覆蓋上一層由PBO所構成的介電層130作為絕緣層。該介電層130係透過旋轉塗佈，並控制其厚度在10μm左右。由於介電層130材料PBO係為光敏材料(Photosensitive material)，可利用曝光顯影技術於該介電層130上製作出複數個介電層通孔133，並貫穿該介電層之第一表面131與第二表面132，藉此提供提供下層MMIC之電性連接。在該介電層130之上利用濺鍍之TiW/Cu為銅金屬電鍍之種子層，並在其上電鍍一層約10μm厚、主要為銅的金屬層做為第一金屬層140。該第一金屬層140形成複數個第一金屬墊141，用以提供HBT功率放大器MMIC之電性連接。該第一金屬層140自第一金屬墊141延伸至介電層通孔133，其中該介電質通孔133係以三維的方式分布於HEMT MMIC由pHEMT 121、電容器122以及電阻器123所構成的主動元件區域上，藉此使兩晶片上位於不同位置的連接節點可以達到電性接觸。該第一金屬層140係進一步延伸進入該介電質通孔133，並且與形成於介電質通孔133另一端的第二金屬墊151形成電性接觸。在本實施例中，所有第二金屬層150主要由金所構成，因此第二金屬墊151亦是由金所構成。每一第二金屬墊151係延伸自第二金屬層150並電性連接至HEMT MMIC元件上之pHEMT 121、電容器122、以及電阻器123等。此連接方式可以避免HEMT MMIC上的化合物半導體元件直接與銅金屬層接觸，進而避免銅原子汙染對元件特性所產生的負面影響。再者，由於第二金屬係均
由金所構成，製作電子元件層之前段製程將可以在不含銅的製程條件下進行，而銅製程則是分別於後段製程中進行，藉此排除銅交叉汙染的問題，並確保元件之特性及具有較佳的製程穩定性。第二晶片200係堆疊於第一晶片100之表面102上。為了達成兩晶片之電性接觸，於HEMT MMIC 130之每一第一金屬墊141上形成一第一金屬凸塊180。該第一金屬凸塊180可以由銅柱(Cu pillar)所構成，並於其上形成一錫銀(SnAg)之熔接金屬。第二晶片200之基板係為砷化鎵(GaAs)基板。每一金屬凸塊180係連接於一接觸金屬墊271；該接觸金屬墊271係由一背面金屬層270所構成，且形成於第二晶片200之基板210背面。每一個接觸金屬墊271係進一步延伸至第二晶片GaAs基板210上之一基板通孔233，藉此連接至HBT功率放大器MMIC上之元件，如HBT 221、電容器222、以及電阻器223等。此兩堆疊之晶片係上下翻轉(正面朝下)，而第二晶片200係透過金屬凸塊280以覆晶方式組合至模組基板90上之模組金屬墊91。
第6圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HEMT功率放大器MMIC 203。HEMT MMIC 103係由偏壓控制電路、開關電路、以及邏輯電路所構成；HEMT MMIC 103係為一控制電路，用以控制HEMT功率放大器MMIC 203之偏壓條件，以及/或控制其射頻訊號的路徑。本實施例中，除了將第二晶片200之HBT功率放大器MMIC換成HEMT功率放大器MMIC以外，關於本實施例之其他描述均與第1實施例相同。
第7圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示
意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HBT功率放大器MMIC 203。第二晶片200係堆疊於第一晶片100之表面102，將此堆疊之第一及第二晶片反轉，使第二晶片200裝配於一模組基板90上，並且透過金屬連結線204打線接合(wire bonding)於模組基板90上。本實施例中其他之描述均與第1實施例相同。
第8圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HEMT功率放大器MMIC 203所構成。第二晶片200係透過金屬連結線204打線接合於模組基板90上。本實施例中，除將第二晶片200之HBT功率放大器MMIC換成HEMT功率放大器MMIC以外，其他之描述均與第3實施例相同。
第9圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HBT功率放大器MMIC 203。該HEMT MMIC係形成於一GaAs基板110上，包含開關電路121、電容器122以及電感器124；其功能為一阻抗調節器，使針對不同輸出功率以及頻率而使用不同操作偏壓的HBT功率放大器MMIC 203，其中HBT元件之輸出端能達成阻抗匹配，以維持最佳的元件特性。由於輸出阻抗係為偏壓條件以及操作頻率的函數，使用阻抗調節器可以在操作條件改變時，仍然保持很好的阻抗匹配。在該HEMT MMIC 103上係覆蓋上一層由PBO所構成的介電層130。螺旋狀之電感器124係由以銅金屬製成之第一金
屬層構造形成於該介電層130上。該電感器124係為該阻抗調節電路的一部分。本實施例中，模組基板90上之輸入/輸出金屬墊91與HEMT MMIC 103上的連接節點(亦即其中一個第二金屬墊151)之電性連接，係透過以三維方式分布於HEMT MMIC 103中之電子元件上方之第一金屬層140連接分隔之連接節點。
第10圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HBT功率放大器MMIC 203。該HEMT MMIC之描述係與實施例5相同，而該HBT功率放大器MMIC 203係與實施例3相同。然而，該HBT功率放大器MMIC 203之上另覆蓋一層由PBO所構成的介電層230，並於其上進一步覆蓋一層由銅金屬所構成的金屬層240。該金屬層240可視為第二晶片之第一金屬層。第二晶片200上其他關於金屬層之適用材料的描述，如金或銅，係與第一晶片100上各金屬層適用之金屬材料相同。由於第一晶片100與第二晶片200之表面均有一銅金屬層可供連結兩晶片電路上位於平面上不同位置的連接節點，其電路佈局設計將更具自由度。第二晶片200係透過金屬連結線204打線接合於模組基板90上。
第11圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HBT功率放大器MMIC 103，而第二晶片200包含一非化合物半導體晶片之電子電路晶片。本實施例之第二晶片係為一Si CMOS IC，包含偏壓控制電路、開關電路、以及邏輯電路，並形成一控制電路，用以控
制HBT功率放大器MMIC 103之偏壓條件。於該HBT功率放大器MMIC 103之上依序包含：一層由PBO所構成的介電層130、一層由銅金屬所構成的第一金屬層140、以及複數個由銅金屬與熔接金屬所構成的金屬凸塊180。該第一金屬層140可用以連接一第一金屬墊141以及位於一介電層通孔133另一端之第二金屬墊151，或用以連接一第一金屬墊141以及另一個與一金屬連結線接合之第一金屬墊141，該第一金屬層140係以三維的方式分佈於該HBT功率放大器MMIC 103之主動元件區域之上，並連接兩晶片上位於不同位置的連接節點。與HBT功率放大器MMIC之連接係透過由至少一第二金屬層150所形成之複數個第二金屬墊151。本實施例中，所有與HBT元件121以及其他電子元件122與123連接之第二金屬層，或構成第二金屬墊151以及第三金屬墊161之第二金屬層，主要由金所構成；因此銅金屬層可以遠離HBT功率放大器MMIC之電子元件，以避免因為銅汙染而造成元件性能退化的問題。該HBT功率放大器MMIC 103係透過金屬連結線104以打線接合的方式，以及/或透過第四金屬層170並經由基板110上之基板通孔113，連接至一模組基板90上。
第12圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；該第一晶片100係為一HBT功率放大器MMIC 103，而第二晶片200係為一Si CMOS IC，用以控制HBT功率放大器MMIC 103之偏壓條件。該第一晶片100係上下翻轉(表面朝下)，而第二晶片200得堆疊於第一晶片100之背面101。兩晶片之間的電性連接係透過基板110背面之第三金屬層170所形成的第四金屬墊171。每一個第四金屬墊171係透過基板通孔113電性連接至第三金屬墊161，進而連接至第二金屬墊151以及電子元件層120中的電子元件；
其中第三金屬墊161與第二金屬墊151係皆由第二金屬層150所構成。在本實施例中，如同第7實施例所描述，所有第二金屬層主要由金所構成；因此可以避免化合物半導體元件受到銅汙染。第一金屬層140係由銅金屬所構成，並且形成於一層由PBO所構成的介電層130之上。該第一金屬層140進一步形成一第一金屬墊141，可用以連接至一模組基板90。該介電層130具有複數個貫穿該介電層130之介電質通孔133。該第一金屬層140，係由介電層通孔133延伸至第一金屬墊141，以三維的方式分佈於該HBT功率放大器MMIC 103之主動元件區域之上，並連接至模組基板90上其中一組輸入/輸出金屬墊91；藉此使基板110背面的第四金屬墊171與模組基板90上位於不同平面位置的輸入/輸出金屬墊91形成電性連接。該第一晶片100係以覆晶方式，透過第一金屬墊141上的金屬凸塊180，以及透過介電質通孔133與HBT元件121射極接觸之金屬凸塊180，組合至該模組基板90上。
第13圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；其中該第一晶片100係包含一HBT功率放大器MMIC 103，而第二晶片200係包含積體被動元件(Integrated passive devices)或濾波器。該積體被動元件係形成於一基板上，且該基板可以由玻璃、矽或化合物半導體(如砷化鎵)等材料所構成。該積體被動元件可以做為一濾波器、或阻抗匹配電路等。該第二晶片200可以進一步包含一聲波濾波器(acoustic filter)，如表面聲波(surface acoustic wave)或體聲波(bulk acoustic wave)濾波器，或一薄膜體聲波濾波器等，並且可以將這類聲波濾波器製作在一基板(如矽基板)上。第二晶片200係堆疊於第一晶片100的表面102上。該第一晶片之結構與製作方法之描述係與第7實施例相同。
第14圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。本實施例之設計係與第9實施例相類似，其中除了將第一晶片100之HBT功率放大器MMIC取代為一HEMT功率放大器MMIC 103，其他描述均與第9實施例相同。
第15圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。本實施例之設計係與第9實施例相類似，其中除了該第一晶片係以如第8實施例描述之覆晶方式組合至模組基板90上，其他描述均與第9實施例相同。
第16圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。本實施例之設計係與第11實施例相類似，其中除了將第一晶片100之HBT功率放大器MMIC取代為一HEMT功率放大器MMIC 103，其他描述均與第11實施例相同。
第17圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。本實施例之半導體積體電路係由複數個相互堆疊之晶片所構成，包含一第一晶片100，一第二晶片200，一第三晶片300，以及一第四晶片400；其中該第一晶片100係包含一HBT功率放大器MMIC 103；第二晶片200係包含一阻抗匹配電路(積體被動元件)以及一偏壓控制電路；第三晶片300係包含一天線開關電路；第四晶片400則包含一濾波器。第二晶片200係堆疊於第一晶片100之背面102；第三晶片300係堆疊於第二晶200片上；而第四晶片400則堆疊於第三晶片300上。該HBT功率放大器之MMIC 103之
結構與製作方法之描述係與第8實施例相同。與基板模組90之連接係透過形成於第一晶片100正面102之金屬凸塊180以及利用打線接合的方式，透過金屬連接線104與第四晶片400上之濾波器連接。
第18圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；且該第一晶片100包含一HBT功率放大器MMIC 103，而第二晶片200包含一電子電路晶片。該第一晶片100係上下翻轉(表面朝下)，並透過覆晶方式組合至一模組基板90。第二晶片200係堆疊於該上下翻轉之第一晶片100背面101。第二晶片係包含偏壓控制電路、開關電路、以及邏輯電路；可形成一控制電路，用以控制HBT功率放大器MMIC 103之偏壓條件；及/或形成一開關電路，用以切換第一晶片100中HBT功率放大器MMIC 103之射頻訊號路徑。第二晶片可以是一個化合物半導體MMIC(例如一HEMT MMIC)，或是一個Si CMOS IC。第一晶片100中，第三金屬層170係於晶片背面102形成至少一第四金屬墊171，並沿延伸至基板通孔113。第二金屬層150其中之一係形成一第三金屬墊161，位於該基板通孔113與第四金屬墊171相對之一端；並於該處透過基板通孔113與第三金屬層170形成電性連接。第三金屬墊161係透過第二金屬層150，電性連接至HBT元件121。第三金屬墊161也連接到一形成於該電子元件層120相對於基板之表面之第四金屬墊191；而該第四金屬墊191係進一步連接至模組基板90上的輸入/輸出金屬墊91。第四金屬墊171係透過金屬凸塊280連接至第二晶片200。第三金屬層170係於第一晶片100中以三維的方式分佈於一電阻器123、一電容器122、以及一HBT 121功率放大器MMIC 103之上。透過此方式，將可連接兩晶片上位於不同平面位置的連接節點。該第三金屬層170之材料較佳為
電鍍之銅金屬，並且以Pd為一種子層。
第19圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。該半導體積體電路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HBT功率放大器MMIC 103所構成，而第二晶片200則包含一阻抗匹配電路；該阻抗匹配電路係形成於砷化鎵或玻璃基板，包含電感器以及/或電容器，用以匹配第一晶片100上HBT元件的輸出阻抗。第二晶片200係堆疊於該上下翻轉之第一晶片100背面101。第二晶片亦可包含一阻抗調節器，藉此使其阻抗與第一晶片100的HBT在不同元件操作條件下之輸出阻抗相匹配。第二晶片亦可包含一濾波器電路，用以濾除在第一晶片100中HBT元件所產生基頻訊號以外的不必要雜訊；該濾波器電路可以由形成於矽、砷化鎵、或玻璃基板之積體被動元件所構成，或由一聲波濾波器(acoustic filter)，如表面聲波(surface acoustic wave)濾波器、體聲波(bulk acoustic wave)濾波器，或一薄膜體聲波濾波器等所構成。本實施例中製作第一晶片100之其他描述係與第14實施例相同。
第20圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。本實施例之設計係與第15實施例相類似，其中除了將第一晶片100之HBT功率放大器MMIC取代為一HEMT功率放大器MMIC 103，其他描述均與第15實施例相同。
第21圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。本實施例之設計大部分與第15實施例相類似。在本實施例中，第四金屬層170係於第一晶片100基板之背面101形成一螺旋狀之電感器172。
該電感器172係透過基板通孔113與第一晶片100之MMIC形成電性連接。該電感器172、該第一晶片100上的MMIC、以及該第二晶片200係一起構成阻抗匹配電路以及阻抗調節電路。該第三金屬層170係由銅金屬或含有銅金屬之多層金屬所構成為較佳，此乃因銅具有高電導率，可減低訊號損耗。
第22圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖。本實施例之設計係與第17實施例相類似，其中除了將第一晶片100之HBT功率放大器MMIC取代為一HEMT功率放大器MMIC 103，其他描述均與第17實施例相同。
第23圖係為根據本發明之半導體積體電路之另一實施例之剖面結構示意圖，其係由複數個相互堆疊之晶片所構成。本實施例之設計係與第13實施例相類似，其中除了第一晶片100之設計與第17實施例之第一晶片100相同，其他描述均與第13實施例相同。
綜上所述，本發明確實可達到預期之目的，而提供一種半導體積體電路，其係由相互堆疊之電子電路晶片所構成，其中至少一晶片係為一化合物半導體積體電路晶片。本發明具有以下優點：
1.藉由晶片堆疊的方式構成一模組，其中構成模組之元件可以分別形成於不同晶片上。由於每一晶片可以各自擁有最佳化之元件佈局設計，並且只要透過該晶片所需之製程步驟就可製作完成；因此，相較於將所有模組元件整合於單一晶片，製作成本將大幅降低。此外，相較於將不同晶片以平面方式整合至一模組基板上，以三維垂直堆疊的方式也可以大幅縮小整體模組的面積。
2.不同晶片之間，或不同電路單元之間的相互連接可以透過晶片表面或背面的金屬層來達成。表面或背面的金屬層可以形成於元件主動區域之上，藉此可以連接兩晶片位於不同水平位置之連接節點。因此，對於晶片上連接節點之佈局設計將更具彈性。相較於將晶片以平面方式整合至單一模組基板上，本發明可以縮短元件之間相互連接的距離，因而降低訊號之損耗與相互干擾。
3.雖然不同晶片之間的相互連結是透過銅金屬來達成，與化合物半導體元件接觸之金屬層仍保持使用金；藉此將可避免銅元素擴散進入化合物半導體元件而導致元件特性變差。再者，電子元件層的製程步驟將可於不含銅金屬的前段製程來完成，至於銅金屬層的部分則可於後段製程中完成；藉此讓表面製程排除銅交叉汙染的問題。如此一來，即使整個化合物半導體MMIC之製程步驟中包含銅金屬製程，仍然可以確保元件特性的穩定性。
4.晶片之背面金屬層可以進一步形成一電感器或其他被動元件。將電感器製作於晶片背面可以節省整個電路所佔據的面積，進而縮小晶片的尺寸。當背面金屬層主要由銅所構成時，晶片背面將可以製作出具有高品質因子的電感器。
本發明之化合物半導體積體電路晶片，其具有分佈於元件主動區域上的表面金屬層，也可以延伸應用於非相互堆疊之晶片。化合物半導體積體電路晶片可以透過表面金屬層，連結至其他任何電子電路。例如當一晶片被堆疊於一模組基板上，可以透過凸塊熔接或金屬線打線接合的方式，將位於模組上的金屬墊電性連接至晶片表面之金屬墊；因此，金屬墊之佈局設計也將更具彈性。
本發明確實可達到預期之目的，並具產業利用之價值，爰依
法提出專利申請。又上述說明與圖式僅是用以說明本發明之實施例，凡熟於此業技藝之人士，仍可做等效的局部變化與修飾，其並未脫離本發明之技術與精神。
100‧‧‧第一晶片
101‧‧‧第一晶片背面
102‧‧‧第一晶片表面
110‧‧‧基板
120‧‧‧電子元件層
121‧‧‧電子元件
130‧‧‧介電層
131‧‧‧介電層第一表面
132‧‧‧介電層第二表面
133‧‧‧介電層通孔
140‧‧‧第一金屬層
141‧‧‧第一金屬墊
150‧‧‧第二金屬層
151‧‧‧第二金屬墊
280‧‧‧金屬凸塊
Claims (43)
- 一種半導體積體電路，包括：一第一晶片，係包含一化合物半導體積體電路，包括：一基板，一介電層，形成於該基板之上，且具有至少一介電層通孔貫穿該介電層之第一表面與第二表面，一第一金屬層，主要係由銅所構成，且具有至少一第一金屬墊形成於該介電層第一表面之上，且從該至少一第一金屬墊延伸進入至少一介電層通孔，以及一電子元件層，係形成於該基板與該介電層之第二表面之間，具有至少一電子元件及至少一第二金屬層，其中該電子元件包含至少一化合物半導體電子元件，至少一該第二金屬層係連接於至少一該電子元件，且至少一該第二金屬層係包含至少一第二金屬墊形成於一介電層通孔位於該介電層之第二表面之一端，並與延伸進入該介電層通孔之第一金屬層形成電性接觸，其中所有與該至少一化合物半導體電子元件接觸之第二金屬層主要係由金所構成；以及一第二晶片，係包含一電子電路，且堆疊於該第一晶片之介電層之第一表面上，並透過連接到至少其中一個該第一金屬墊與第一晶片形成電性連接，其中該第一金屬層係以三維方式分佈於該電子元件層中至少一個電子元件上方，而至少一個該第一金屬墊係透過該第一金屬層延伸進 入至少其中一個該介電層通孔而電性連接於該介電層通孔另一側之第二金屬墊中之至少一個；以及該第一晶片包含一功率放大器MMIC，而該第二晶片包含下列電路中的一種：一偏壓控制電路，用以控制第一晶片中該至少一電子元件之偏壓條件；一開關電路，用以控制第一晶片訊號路徑；一天線開關電路，用以連接第一晶片中功率放大器輸出端至天線；一阻抗調節電路，用以調節阻抗大小，並使其隨第一晶片中功率放大器之偏壓條件及工作頻率而改變；以及一由被動元件所構成之阻抗匹配電路，用以匹配第一晶片中功率放大器之輸入與/或輸出端之阻抗。
- 如申請專利範圍第1項所述之半導體積體電路，其中所有該第二金屬層主要係由金所構成。
- 如申請專利範圍第1項所述之半導體積體電路，其中該第一晶片之基板係由砷化鎵(GaAs)、矽(Si)、炭化矽(SiC)、藍寶石(sapphire)或氮化鎵(GaN)所構成。
- 如申請專利範圍第1項所述之半導體積體電路，其中該介電層係由介電物質聚苯噁唑(Polybenzoxazole,PBO)所構成。
- 如申請專利範圍第1項所述之半導體積體電路，其中該介電層之厚度等於或大於10μm。
- 如申請專利範圍第1項所述之半導體積體電路，其中該第一晶片包含一異質接面雙極性電晶體(heterojunction bipolar transistor,HBT)單晶微波積體電路(monolithic microwave integrated circuit,MMIC)或一高電子遷移率電晶體(high-electron-mobility transistor,HEMT)MMIC。
- 如申請專利範圍第1項所述之半導體積體電路，其中該第一晶片包含一氮化鎵(GaN)場效電晶體(field effect transistor,FET)MMIC。
- 如申請專利範圍第1項所述之半導體積體電路，其中該第二晶片係包含一化合物半導體MMIC。
- 如申請專利範圍第8項所述之半導體積體電路，其中該第二晶片之基板係由砷化鎵(GaAs)所構成。
- 如申請專利範圍第1項所述之半導體積體電路，其中該第二晶片係包含一矽互補式金屬氧化物半導體(Si CMOS)積體電路。
- 如申請專利範圍第1項所述之半導體積體電路，其中該第二晶片係包含至少一被動元件積體整合於同一基板，且該基板之材料可為矽、砷化鎵、或玻璃。
- 如申請專利範圍第1項所述之半導體積體電路，其中該第二晶片係包含一濾波器。
- 一種半導體積體電路，包括：一第一晶片，係包含一化合物半導體積體電路，包括：一基板，具有至少一基板通孔貫穿該基板之第一表面與第二表面，一介電層，形成於該基板之上，且具有至少一介電層通孔貫穿該介電層之第一表面與第二表面，一第一金屬層，主要係由銅所構成，該第一金屬層形成至少一第一金屬墊於該介電層第一表面之上，且從該至少一第一金屬墊延伸進入至少一介電層通孔，一電子元件層，形成於該基板之第一表面與該介電層之第二表面之間，具有至少一電子元件及至少一第二金屬層；其中該電子元件包含至少一化合物半導體電子元件，至少一該第二金屬層係連接於至少一該電子元件，至少一該第二金屬層係包含至少一第二金 屬墊形成於一介電層通孔位於該介電層之第二表面之一端，並與延伸進入該介電層通孔之第一金屬層形成電性接觸，且至少一該第二金屬層形成至少一第三金屬墊於一基板通孔位於該基板之第一表面之一端，其中所有與該至少一化合物半導體電子元件所接觸之第二金屬層主要係由金所構成，以及一第三金屬層，具有至少一第四金屬墊形成於該基板之第二表面，且從每一個該至少一第四金屬墊延伸進入至少一基板通孔，藉此與配置於基板通孔另一側之第三金屬墊形成電性接觸；以及一第二晶片，係包含一電子電路，且堆疊於該第一晶片基板之第二表面上，並透過連接到至少其中一個該第四金屬墊，與第一晶片形成電性連接；其中該第一金屬層係以三維方式分佈於該電子元件層中至少一個電子元件上方，而至少一個該第一金屬墊係透過該第一金屬層延伸進入至少其中一個該介電層通孔而電性連接於該介電層通孔另一側之第二金屬墊中之至少一個。
- 如申請專利範圍第13項所述之半導體積體電路，其中所有該第二金屬層主要係由金所構成。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第三金屬層主要係由銅所構成。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第一晶片之基板係由砷化鎵(GaAs)、矽(Si)、炭化矽(SiC)、藍寶石(sapphire)或氮化鎵(GaN)所構成。
- 如申請專利範圍第13項所述之半導體積體電路，其中該介電層係由介電物質聚苯噁唑(Polybenzoxazole,PBO)所構成。
- 如申請專利範圍第13項所述之半導體積體電路，其中該介電層之厚度等於或大於10μm。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第一晶片包含一HBT MMIC或一HEMT MMIC。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第一晶片包含一氮化鎵(GaN)場效電晶體(FET)MMIC。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第一晶片包含一功率放大器MMIC。
- 如申請專利範圍第21項所述之半導體積體電路，其中該第二晶片包含下列電路中的一種：一偏壓控制電路，用以控制第一晶片中該至少一電子元件之偏壓條件；一開關電路，用以控制第一晶片訊號路徑；一天線開關電路，用以連接第一晶片中功率放大器輸出端至天線；一阻抗調節電路，用以調節阻抗大小，並使其隨第一晶片中功率放大器之偏壓條件及工作頻率而改變；以及一由被動元件所構成之阻抗匹配電路，用以匹配第一晶片中功率放大器之輸入與/或輸出端之阻抗。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第二晶片係包含一化合物半導體MMIC。
- 如申請專利範圍第23項所述之半導體積體電路，其中該第二晶片之基板係由砷化鎵(GaAs)所構成。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第二晶片係包含一矽互補式金屬氧化物半導體(Si CMOS)積體電路。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第二晶片係包含至少一被動元件積體整合於同一基板，且該基板之材料可為矽、砷化鎵、 或玻璃。
- 如申請專利範圍第13項所述之半導體積體電路，其中該第二晶片係包含一濾波器。
- 一種半導體積體電路，包括：一第一晶片，係包含一化合物半導體積體電路，包括：一基板，具有至少一基板通孔貫穿該基板之第一表面與第二表面，一電子元件層，形成於該基板之第一表面，具有至少一電子元件及至少一第二金屬層，其中該電子元件包含至少一化合物半導體電子元件，至少一該第二金屬層係連接於至少一該電子元件，至少一該第二金屬層係形成至少一第三金屬墊於一基板通孔位於該基板第一表面之一端，以及一第三金屬層，具有至少一第四金屬墊形成於該基板之第二表面，且從每一個該至少一第四金屬墊延伸進入至少一基板通孔，藉此與配置於基板通孔另一側之第三金屬墊形成電性接觸；以及一第二晶片，係包含一電子電路，且堆疊於該第一晶片基板之第二表面上，並透過連接到至少其中一個該第四金屬墊，與第一晶片形成電性連接，其中該第三金屬層係以三維方式分佈於該電子元件層中至少一個電子元件下方，而至少一個該第四金屬墊係透過該第三金屬層延伸進入至少其中一個該基板通孔而電性連接於該基板通孔另一側之第三金屬墊中之至少一個。
- 如申請專利範圍第28項所述之半導體積體電路，其中至少一個該第二金屬層進一步形成一第五金屬墊，且位於該電子元件層之表面(未與該基板 接觸之表面)或其鄰近區域；其中至少一個該第三金屬墊係電性連接到至少其中一個該第五金屬墊層。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第三金屬層主要係由銅所構成。
- 如申請專利範圍第30項所述之半導體積體電路，其中所有與化合物半導體元件接觸之該第二金屬層主要係由金所構成。
- 如申請專利範圍第30項所述之半導體積體電路，其中所有該第二金屬層主要係由金所構成。
- 如申請專利範圍第28項所述之半導體積體電路，其中至少一個該第三金屬層進一步形成一電感器，其位於第一晶片基板之第二表面，且分佈涵蓋至少一個該電子元件，並且該電感器係電性連接至該第一晶片、第二晶片、或同時連接至該第一晶片以及第二晶片。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第一晶片之基板係由砷化鎵(GaAs)、矽(Si)、炭化矽(SiC)、藍寶石(sapphire)或氮化鎵(GaN)所構成。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第一晶片包含一HBT MMIC或一HEMT MMIC。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第一晶片包含一氮化鎵(GaN)場效電晶體(FET)MMIC。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第一晶片包含一功率放大器MMIC。
- 如申請專利範圍第37項所述之半導體積體電路，其中該第二晶片包含下列電路中的一種：一偏壓控制電路，用以控制第一晶片中該至少一電子 元件之偏壓條件；一開關電路，用以控制第一晶片訊號路徑；一天線開關電路，用以連接第一晶片中功率放大器輸出端至天線；一阻抗調節電路，用以調節阻抗大小，並使其隨第一晶片中功率放大器之偏壓條件及工作頻率而改變；以及一由被動元件所構成之阻抗匹配電路，用以匹配第一晶片中功率放大器之輸入與/或輸出端之阻抗。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第二晶片係包含一化合物半導體MMIC。
- 如申請專利範圍第39項所述之半導體積體電路，其中該第二晶片之基板係由砷化鎵(GaAs)所構成。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第二晶片係包含一矽互補式金屬氧化物半導體(Si CMOS)積體電路。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第二晶片係包含至少一被動元件積體整合於同一基板，且該基板之材料可為矽、砷化鎵、或玻璃。
- 如申請專利範圍第28項所述之半導體積體電路，其中該第二晶片係包含一濾波器。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/751,855 US20140209926A1 (en) | 2013-01-28 | 2013-01-28 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201431037A TW201431037A (zh) | 2014-08-01 |
| TWI543331B true TWI543331B (zh) | 2016-07-21 |
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| TW102124796A TWI543331B (zh) | 2013-01-28 | 2013-07-10 | 半導體積體電路 |
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| US (1) | US20140209926A1 (zh) |
| JP (1) | JP5763704B2 (zh) |
| CN (1) | CN103972226B (zh) |
| TW (1) | TWI543331B (zh) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9093506B2 (en) * | 2012-05-08 | 2015-07-28 | Skyworks Solutions, Inc. | Process for fabricating gallium arsenide devices with copper contact layer |
| GB2533767B (en) * | 2014-12-16 | 2019-06-19 | Leonardo Mw Ltd | Integrated circuits and methods of manufacturing. |
| US10075132B2 (en) | 2015-03-24 | 2018-09-11 | Nxp Usa, Inc. | RF amplifier with conductor-less region underlying filter circuit inductor, and methods of manufacture thereof |
| US9871107B2 (en) * | 2015-05-22 | 2018-01-16 | Nxp Usa, Inc. | Device with a conductive feature formed over a cavity and method therefor |
| US10276541B2 (en) * | 2015-06-30 | 2019-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D package structure and methods of forming same |
| US9787254B2 (en) | 2015-09-23 | 2017-10-10 | Nxp Usa, Inc. | Encapsulated semiconductor device package with heatsink opening, and methods of manufacture thereof |
| KR102492527B1 (ko) * | 2015-10-12 | 2023-01-31 | 삼성전자주식회사 | 데이터 스토리지 소자 및 그를 포함하는 전자 장치 |
| TWI559449B (zh) * | 2015-10-19 | 2016-11-21 | 穩懋半導體股份有限公司 | 化合物半導體積體電路之電路佈局方法 |
| CN106672888B (zh) * | 2015-11-11 | 2022-03-11 | 恩智浦美国有限公司 | 封装集成电路管芯的方法和器件 |
| WO2017111769A1 (en) * | 2015-12-22 | 2017-06-29 | Intel Corporation | Microelectronic devices designed with compound semiconductor devices and integrated on an inter die fabric |
| CN108292648B (zh) * | 2015-12-22 | 2022-08-30 | 英特尔公司 | 设计有包括集成在封装上的管芯结构上的化合物半导体器件的高频通信器件的微电子器件 |
| TWI765944B (zh) * | 2016-12-14 | 2022-06-01 | 成真股份有限公司 | 標準大宗商品化現場可編程邏輯閘陣列（ｆｐｇａ）積體電路晶片組成之邏輯驅動器 |
| US10069464B1 (en) * | 2017-02-21 | 2018-09-04 | The Boeing Company | 3D low flux, high-powered MMIC amplifiers |
| US10062683B1 (en) | 2017-02-27 | 2018-08-28 | Qualcomm Incorporated | Compound semiconductor transistor and high-Q passive device single chip integration |
| WO2019065668A1 (ja) * | 2017-09-29 | 2019-04-04 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
| CN109494218B (zh) * | 2018-09-30 | 2021-07-30 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | 双面超导量子芯片 |
| US11310904B2 (en) | 2018-10-30 | 2022-04-19 | Xintec Inc. | Chip package and power module |
| CN109534278B (zh) * | 2018-11-01 | 2020-12-15 | 中国科学院半导体研究所 | 声学滤波器与hemt异构集成的结构及其制备方法 |
| KR102083742B1 (ko) * | 2018-11-13 | 2020-03-02 | 광운대학교 산학협력단 | 안정된 성능을 가지는 반도체 장치 |
| DE102019211465A1 (de) * | 2019-07-31 | 2021-02-04 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Halbleiter-bauelementstruktur mit verbindungshalbleiter und verfahren zum herstellen derselbigen |
| DE102019211468A1 (de) | 2019-07-31 | 2021-02-04 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Vertikale verbindungshalbleiter-struktur und verfahren zum herstellen derselbigen |
| CN111477612B (zh) * | 2020-03-23 | 2022-06-10 | 中国电子科技集团公司第十三研究所 | 可调芯片 |
| WO2022124035A1 (ja) * | 2020-12-11 | 2022-06-16 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
| US11749746B2 (en) | 2021-04-29 | 2023-09-05 | Qualcomm Incorporated | Radio frequency front end (RFFE) hetero-integration |
| TWI839620B (zh) | 2021-06-30 | 2024-04-21 | 立積電子股份有限公司 | 半導體裝置及形成半導體裝置之方法 |
| CN115579299B (zh) * | 2022-11-21 | 2023-04-14 | 常州承芯半导体有限公司 | 半导体结构及其形成方法 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| MY115336A (en) * | 1994-02-18 | 2003-05-31 | Ericsson Telefon Ab L M | Electromigration resistant metallization structures and process for microcircuit interconnections with rf-reactively sputtered titanium tungsten and gold |
| US6037044A (en) * | 1998-01-08 | 2000-03-14 | International Business Machines Corporation | Direct deposit thin film single/multi chip module |
| JP4209178B2 (ja) * | 2002-11-26 | 2009-01-14 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
| US6825559B2 (en) * | 2003-01-02 | 2004-11-30 | Cree, Inc. | Group III nitride based flip-chip intergrated circuit and method for fabricating |
| US7088003B2 (en) * | 2004-02-19 | 2006-08-08 | International Business Machines Corporation | Structures and methods for integration of ultralow-k dielectrics with improved reliability |
| JP2008085362A (ja) * | 2004-12-20 | 2008-04-10 | Sanyo Electric Co Ltd | 半導体装置及び半導体モジュール |
| JP2007317857A (ja) * | 2006-05-25 | 2007-12-06 | Fujikura Ltd | 半導体装置及びその製造方法 |
| US7615863B2 (en) * | 2006-06-19 | 2009-11-10 | Northrop Grumman Space & Missions Systems Corp. | Multi-dimensional wafer-level integrated antenna sensor micro packaging |
| JP2008103387A (ja) * | 2006-10-17 | 2008-05-01 | Murata Mfg Co Ltd | 半導体装置 |
| JP5192163B2 (ja) * | 2007-03-23 | 2013-05-08 | 住友電工デバイス・イノベーション株式会社 | 半導体装置 |
| US7508267B1 (en) * | 2007-09-28 | 2009-03-24 | Rockwell Collins, Inc. | GaN based digital controlled broadband MMIC power amplifier |
| SG156550A1 (en) * | 2008-05-06 | 2009-11-26 | Gautham Viswanadam | Wafer level integration module with interconnects |
| KR101202020B1 (ko) * | 2008-11-14 | 2012-11-16 | 한국전자통신연구원 | 웨이퍼 수준의 집적회로 칩 조정 시스템 및 집적회로 칩 조정 방법 |
| JP2010171386A (ja) * | 2008-12-26 | 2010-08-05 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
| US8426961B2 (en) * | 2010-06-25 | 2013-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded 3D interposer structure |
| WO2012011207A1 (ja) * | 2010-07-21 | 2012-01-26 | パナソニック株式会社 | 検査用パッド電極を除去する工程を備える半導体装置の製造方法 |
| US20120193785A1 (en) * | 2011-02-01 | 2012-08-02 | Megica Corporation | Multichip Packages |
| KR20130013820A (ko) * | 2011-07-29 | 2013-02-06 | 한국전자통신연구원 | 반도체 장치 및 그 제조 방법 |
| JP2012109614A (ja) * | 2012-02-24 | 2012-06-07 | Seiko Epson Corp | 半導体装置、回路基板及び電子機器 |
-
2013
- 2013-01-28 US US13/751,855 patent/US20140209926A1/en not_active Abandoned
- 2013-04-26 JP JP2013093771A patent/JP5763704B2/ja not_active Expired - Fee Related
- 2013-07-10 TW TW102124796A patent/TWI543331B/zh active
- 2013-08-01 CN CN201310331225.0A patent/CN103972226B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| TW201431037A (zh) | 2014-08-01 |
| US20140209926A1 (en) | 2014-07-31 |
| JP2014146780A (ja) | 2014-08-14 |
| CN103972226A (zh) | 2014-08-06 |
| CN103972226B (zh) | 2017-04-12 |
| JP5763704B2 (ja) | 2015-08-12 |
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