CN103972226B - 半导体集成电路 - Google Patents

半导体集成电路 Download PDF

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Publication number
CN103972226B
CN103972226B CN201310331225.0A CN201310331225A CN103972226B CN 103972226 B CN103972226 B CN 103972226B CN 201310331225 A CN201310331225 A CN 201310331225A CN 103972226 B CN103972226 B CN 103972226B
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chip
metal
integrated circuit
substrate
semiconductor integrated
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CN103972226A (zh
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高谷信郎
高谷信一郎
萧献赋
林正国
花长煌
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WIN Semiconductors Corp
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WIN Semiconductors Corp
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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Bipolar Transistors (AREA)

Abstract

一种化合物半导体集成电路，其具有表面以及/或背面金属层，可用于连接至外部电路。该化合物半导体集成电路晶片(第一晶片)包含一基板、一电子元件层以及一介电层。一第一金属层形成于该介电层的表面，一第三金属层则形成于基板背面。该第一金属层与第三金属层主要由铜所构成，且用于连接至其他外部的电子电路。第一晶片上的第一或第三金属层以三维的方式分布于第一晶片的电子元件上方或下方，一第二晶片可以设置堆叠于第一晶片的表面或背面，并通过第一或第三金属层电连接两个晶片上分隔的连接节点。

Description

半导体集成电路
技术领域
本发明是关于一种半导体集成电路晶片，其具有一表面金属层及/或一背面金属层，用以连接至外部电路；尤指一种具有数个电子电路晶片相互堆叠的半导体集成电路，且其中至少有一个为一化合物半导体单晶微波集成电路晶片。
背景技术
化合物半导体单晶微波集成电路(monolithic microwave integratedcircuits,MMIC)已被广泛应用于射频(RF)信号发射器、接收器以及收发器等微波通讯元件，如行动电话及无线区域网路(LAN)模组等。这类射频模组通常由许多电子电路零件所构成，如功率放大器(PA)、开关元件、滤波器以及控制元件等。其中有些电子电路零件已经被整合于单一晶片上。以化合物半导体的放大器电路而言(如包含异质接面双极性电晶体(HBT)或高电子迁移率电晶体(HEMT)的放大器)，通常会使用HEMT元件来控制电晶体放大器偏压条件，而这些元件与电路都可以集成整合于单一化合物半导体晶片上。例如，HBT功率放大器与HEMT控制电路就可以利用BiFET(或BiHEMT)工艺将其集成整合于单一化合物半导体晶片上。另一个集成整合的例子则是将增强型HEMT元件与空乏型HEMT元件制作于单一晶片上，其中增强型HEMT元件作为功率放大器的用途，而空乏型HEMT元件则是作为控制元件。化合物半导体放大器与一开关电路结合，其中该开关可依照功率位准、频率带以及通讯模式用来改变射频信号路径，也通常被整合于单一晶片中。化合物半导体放大器与一天线开关电路结合，其中该天线开关可用于切换天线与不同的Tx与Rx电路连接，也常被整合于单一晶片中。化合物半导体HBT放大器通常操作于不同的偏压条件，以确保元件在不同输出功率与频率范围的保持最佳特性。由于输入与输出阻抗为偏压条件的函数，通常会引入一阻抗调节器，使偏压条件改变时，仍可保持很好的阻抗匹配。阻抗调节器通常由电容器、电感器以及HEMT开关元件所构成，其中HEMT开关元件是被用来切换电容器与电感器的连接，进而改变整体的阻抗大小。然而随着功能性的增加，高度集成整合的电路与元件也将造成制作成本增加及良率降低，将HBT与HEMT元件集成整合于单一晶片上时尤其如此。
为了降低工艺成本，上述射频模组中的电路元件可以分别制作于不同晶片上，甚至可以进一步结合其他如硅互补式金属氧化物半导体(Si CMOS)集成电路晶片等。传统的整合作法通常是将数个不同的晶片置于同一平面上并相互连接；然而此方式会随晶片数目增加而使模组尺寸变大，同时长距离的相互连接也容易造成信号损耗及相互干扰。例如，一般射频模组即包含一HBT功率放大器MMIC晶片、一阻抗匹配及偏压控制晶片、一天线开关晶片以及一滤波电路晶片，而这些晶片均置于同一平面的模组基板上。
发明内容
本发明提供一种化合物半导体集成电路晶片，具有一表面金属层及/或背面金属层，用以连接外部电路。本发明的主要目在于提供一种化合物半导体集成电路晶片，其包含数个相互堆叠的晶片，且其中至少有一个为化合物半导体集成电路晶片；借此，由堆叠晶片构成的半导体集成电路模组其面积将可大幅降低。相较于将模组中所有电路与零件制作于单一晶片上，晶片模组化的设计也可简化晶片的工艺步骤。同时，也可缩短不同晶片之间或电路元件之间相互连接的距离，因而降低信号损耗及相互干扰。借助元件上方的金属层，可以重新分布或配置晶片之间的连接节点，因此晶片之间的连接节点不一定要位于同一垂直线上，大幅提高连接节点布局设计的自由度。
为达上述目的，本发明提供一种半导体集成电路，其包含一第一晶片，且该第一晶片包含一化合物半导体集成电路。该第一晶片进一步包含：一基板、一介电层、一电子元件层以及一第一金属层。前述的电子元件层形成于该基板之上，具有一钝化层和位于该钝化层内的至少一电子元件及至少一第二金属层，该电子元件包括至少一化合物半导体电子元件。前述的介电层形成于前述电子元件层之上，且至少包含一介电层通孔贯穿该介电层的第一表面与第二表面。前述的第一金属层主要由铜所构成，且包含至少一第一金属垫形成于该介电层第一表面的上并延伸进入至少一介电层通孔。前述的至少一该第二金属层连接于至少一该电子元件，至少一该第二金属层包含至少一第二金属垫形成于一介电层通孔位于该介电层的第二表面的一端，并与延伸进入该介电层通孔的第一金属层形成电接触。所有与化合物半导体电子元件所接触的第二金属层主要由金所构成。其中该第一金属层以三维方式分布于电子元件层中至少一个电子元件上方，而至少一个第一金属垫通过该第一金属层延伸进入至少其中一个介电层通孔而电连接于该介电层通孔另一侧的第二金属垫中的至少一个。
本发明进一步提供一种半导体集成电路，其包含一上述的第一晶片以及一第二晶片，且该第二晶片包含一电子电路。在此定义第一晶片中的介电层的第一表面为该第一晶片的表面，而该基板相对于该介电层的表面则定义为第一晶片的背面。前述的第二晶片堆叠于第一晶片的表面上，并且电连接至第一晶片上的至少一第一金属垫。第一金属层以三维方式分布于电子元件层中至少一个电子元件上方，为使两个晶片上的接点对齐，至少一个第一金属垫通过该第一金属层延伸进入至少其中一个介电层通孔而电连接于该介电层通孔另一侧的第二金属垫中的至少一个。
本发明也提供另一种半导体集成电路，其包含一第一晶片以及一第二晶片，其中该第一晶片包含一化合物半导体集成电路，而第二晶片包含一电子电路。该第一晶片进一步包含：一基板、一介电层、一电子元件层、一第一金属层以及一第三金属层。前述的基板包含至少一基板通孔，且贯穿该基板的第一表面与第二表面。前述的电子元件层形成于该基板之上，具有一钝化层和位于该钝化层内的至少一电子元件及至少一第二金属层，该电子元件包括至少一化合物半导体电子元件。前述的介电层形成于该电子元件层的第一表面上，且包含至少一介电层通孔，贯穿该介电层的第一表面与第二表面。前述的第一金属层主要由铜所构成，且包含至少一第一金属垫形成于该介电层的第一表面上并且延伸进入至少一介电层通孔；前述的至少一该第二金属层连接于至少一该电子元件，至少一该第二金属层包含至少一第二金属垫形成于一介电层通孔位于该介电层的第二表面的一端，并与前述的延伸进入该介电层通孔的第一金属层形成电接触。至少一前述该第二金属层包含至少一第三金属垫形成基板通孔位于该基板的第一表面的一端。所有与该化合物半导体电子元件所接触的第二金属层主要由金所构成。前述的第三金属层包含至少一第四金属垫形成于该基板的第二表面且延伸进入至少一基板通孔，借此与位于基板通孔另一侧的第三金属垫形成电接触。在此定义前述介电层的第一表面为第一晶片的表面，而前述基板的第二表面则定义为第一晶片的背面。前述的第二晶片堆叠于第一晶片的背面，并且电连接至第一晶片的至少一第四金属垫。第三金属层以三维方式分布于电子元件层中至少一个电子元件下方，为使两个晶片上的接点对齐，至少一个第四金属垫通过该第三金属层延伸进入至少其中一个介电层通孔而电连接于该介电层通孔另一侧的第三金属垫中的至少一个。
本发明也提供另一种半导体集成电路，其包含一第一晶片以及一第二晶片，其中该第一晶片包含一化合物半导体集成电路，而该第二晶片包含一电子电路。该第一晶片进一步包含：一基板、一电子元件层以及一第三金属层。前述的基板包含至少一基板通孔，且贯穿该基板的第一表面与第二表面。前述的电子元件层形成于该基板第一表面，包含一钝化层和位于该钝化层内的至少一电子元件以及至少一第二金属层，其中前述至少一电子元件中包含至少一化合物半导体电子元件，至少一该第二金属层连接于至少一该电子元件，至少一该第二金属层包含至少一第三金属垫形成于一基板通孔位于该基板的第一表面的一端。前述的第三金属层包含至少一第四金属垫形成于该基板的第二表面且延伸进入至少一基板通孔，借此与在基板通孔另一侧的第三金属垫形成电接触。该第三金属垫通过第二金属层，直接或间接地与至少一电子元件相连接。该第三金属垫也可以连接到一第五金属垫；其中第五金属垫由该至少一第二金属层所构成，且位于该电子元件层与基板相对的表面或其邻近区域。前述的第五金属垫可连接到其他电路晶片或电子零件模组。在此定义该第一晶片上电子元件层与基板相对的表面为该第一晶片的表面，而该基板的第二表面则定义为第一晶片的背面。前述的第二晶片堆叠于第一晶片的背面，并且电连接至第一晶片的至少一第四金属垫。为使两个晶片上的接点对齐，前述的至少一第四金属垫通过一第三金属层延伸进入一基板通孔而电连接于该基板通孔另一侧的三金属垫，并且进一步电连接至电子元件层中的至少一电子元件。
本发明的另一目的在于提供一种半导体集成电路，其中一晶片的背面金属层可以用以形成一电感器。前述的位于晶片背面的电感器可以缩小整体电路所占据的面积，进而所小晶片整体尺寸。且当背面金属层主要由铜所构成时，晶片背面将可以制作出具有高品质因子(quality factor)的电感器。
为达上述目的，本发明提供另一种半导体集成电路，其进一步包含一电感器于前述的半导体集成电路中。前述的电感器由第三金属层所构成，形成于第一晶片基板的第二表面上，且位于至少一电子元件上。该电感器电连接于第一晶片、第二晶片或同时电连接于第一及第二晶片。
于实施时，前述的第二金属层主要由金(Au)所构成。
于实施时，前述第一晶片的基板由砷化镓(GaAs)所构成。
于实施时，前述的介电层由介电物质聚苯恶唑(Polybenzoxazole,PBO)所构成。
于实施时，前述的介电层厚度等于或大于10μm。
于实施时，前述的第三金属层主要由铜(Cu)所构成。
于实施时，前述的第一晶片包含一异质接面双极性电晶体(HBT)单晶微波集成电路(MMIC)或一高电子迁移率电晶体(HEMT)MMIC。
前述的第一晶片包含一氮化镓(GaN)场效电晶体(FET)。
于实施时，前述的第一晶片包含一功率放大器MMIC。
于实施时，前述的第二晶片包含：一偏压控制电路，用以控制第一晶片中至少一电子元件的偏压条件；一开关电路，用以控制第一晶片信号路径；一天线开关电路，用以连接第一晶片中功率放大器输出端至天线；一阻抗调节电路，用以调节阻抗大小，并使其随第一晶片中功率放大器的偏压条件及工作频率而改变；以及一由被动元件所构成的阻抗匹配电路，用以匹配第一晶片中功率放大器的输入与/或输出端的阻抗。
于实施时，前述的第二晶片包含一化合物半导体MMIC。
于实施时，前述的第二晶片包含一硅互补式金属氧化物半导体(Si CMOS)集成电路。
于实施时，前述的第二晶片包含至少一被动元件集成整合于同一基板，且该基板由硅、砷化镓或玻璃所构成。
于实施时，前述的第二晶片包含一滤波器。
为对于本发明的特点与作用能有更深入的了解，兹借实施例配合附图详述于后。
附图说明
图1为本发明所提供的半导体集成电路的一种实施例的剖面结构示意图，其中第二晶片堆叠于第一晶片的表面。
图2为本发明所提供的半导体集成电路的一种实施例的剖面结构示意图，其中第二晶片堆叠于第一晶片的背面。
图3为本发明所提供的半导体集成电路的另一实施例的剖面结构示意图，其中第二晶片堆叠于第一晶片的背面。
图4为本发明所提供的半导体集成电路的另一实施例的剖面结构示意图，其中一电感器形成于第一晶片的背面。
图5至图23为分别对应于本发明所提供的第1实施例至第19实施例的剖面结构示意图。
图24为本发明所提供的种实施例中，晶片包含一化合物半导体集成电路晶片的剖面结构示意图。
图24A、图24B为本发明所提供的实施例中，金属层的剖面结构示意图。附图标记说明
模组基板 90 模组金属垫 91
第一晶片 100 第一晶片背面 101
第一晶片表面 102 MMIC 103,203
金属连结线 104,204,404 基板 110,210
基板第一表面 111 基板第二表面 112
基板通孔 113 电子元件层 120
电子元件 121,221 电容器 122,222
电阻器 123,223 钝化层 128
介电层 130
介电层第一表面 131 介电层第二表面 132
介电层通孔 133,233 第一金属层 140,240
第一金属垫 141 第二金属层 150
第二金属垫 151 第三金属垫 161
第三金属层 170 第四金属垫 171
电感器 172 金属凸块 180,280
第五金属垫 181 第四金属垫 191
第二晶片 200 背面金属层 270
接触金属垫 271 第三晶片 300
第四晶片 400。
具体实施方式
图24为根据本发明的半导体集成电路的一种实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100，且该第一晶片包含一化合物半导体集成电路。该第一晶片进一步包含：一基板110、一介电层130、一电子元件层120以及一第一金属层140。前述的介电层130形成于基板110上，且至少包含一介电层通孔133贯穿该介电层130的第一表面131与第二表面132。前述的电子元件层120形成于基板110与介电层130的第二表面之间。电子元件层120包含至少一化合物半导体电子元件121以及至少一第二金属层150。第一金属层140形成至少一第一金属垫于介电层第一表面131上，且延伸进入至少一介电层通孔133。在该至少一第二金属层150当中，其中至少一第二金属层电连接于至少一电子元件121。在该至少一第二金属层150当中，其中至少一第二金属层包含至少一第二金属垫151形成于一介电层通孔133位于该介电层的第二表面132的一端，并与延伸进入该介电层通孔133的第一金属层140形成电接触。如图24A与24B所示，第一金属层140或第二金属层150下方可以包含一层或数层底层结构作为附着层(adhesion layer)、扩散位障层(diffusion barrierlayer)以及/或电镀的种子层(seed layer)。该第一金属层140或第二金属层150上方也可以进一步包含一层或数层的上层结构作为金属的保护层，可用来防止金属潮湿或氧化，或提供形成于其上的材料较佳的附着力。以铜金属层为例，其底层结构可以由Ti、TiW或Pt等金属层所构成，而上层结构则可以由金所构成。若以金的金属层为例，其底层结构可以由Ti或Pd等金属所构成，而上层结构则可以由Ti等金属所构成。借助形成金属凸块280于第一金属垫141上，该第一晶片100即可通过凸块接合(bump bonding)方式电连接至其他电子电路。除了通过金属凸块280，也可利用线接合(wire bonding)方式使第一金属垫141通过金属连接线与其他电子电路达到电连接。例如，该第一晶片100可以直接堆叠于一个模组基板上，并通过凸块接合或线接合方式，使第一金属垫141与基板模组上的金属垫形成电连接。第一金属层140以三维方式分布于电子元件层120中至少一个电子元件121上方，而至少一个第一金属垫141通过第一金属层140延伸进入至少其中一个介电层通孔133而电连接于该介电层通孔另一侧的第二金属垫151，因此第一金属垫141可设置于一较佳的位置已连接于其他电路。
图1为根据本发明的半导体集成电路的一种实施例的剖面结构示意图。该半导体集成电路包含前述的第一晶片100以及一第二晶片200，且该第二晶片包含一电子电路。在此定义该第一晶片100上的介电层的第一表面131为该第一晶片表面102，而该基板相对于该介电层的表面则定义为第一晶片背面101。第二晶片200堆叠于第一晶片表面102上，并且通过金属凸块280电连接于至少一第一金属垫141。借此，两垂直堆叠的第一晶片与第二晶片通过电连接而整合成为单一电路。第一金属层140以三维方式分布于电子元件层120中至少一个电子元件121上方，为使第一晶片100与第二晶片200上的接点通过金属凸块280对齐，至少一个第一金属垫141通过第一金属层140延伸进入至少其中一个介电层通孔133而电连接于该介电层通孔另一侧的第二金属垫151。
图2为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200，且该第一晶片100包含一化合物半导体集成电路，而第二晶片200包含一电子电路。该第一晶片100进一步包含：一基板110、一电子元件层120、一介电层130、一第一金属层140以及一第三金属层170。基板110包含至少一基板通孔113，且贯穿该基板的第一表面111与第二表面112。介电层130形成于基板的第一表面111，且至少包含一介电层通孔133，并贯穿该介电层的第一表面131与第二表面132。电子元件层120形成于基板110与介电层130之间，包含至少一电子元件以及至少一第二金属层150，其中至少一电子元件中包含至少一化合物半导体电子元件121。第一金属层140主要由铜所构成，且形成至少一第一金属垫141于介电层的第一表面131上并且延伸进入至少一介电层通孔133。至少一第二金属层150电连接于至少一化合物半导体电子元件121，且所有与化合物半导体电子元件121接触的第二金属层150主要由金所构成。所有第二金属层当中，其中至少一第二金属层150包含至少一第二金属垫151形成于一介电层通孔133位于该介电层的第二表面132的一端，并与延伸进入该介电层通孔133的第一金属层140形成电接触。第三金属层170形成于基板的第二表面112，其至少包含一第四金属垫171，且延伸进入至少一基板通孔113。第二金属层150中，至少其中的一包含至少一第三金属垫161形成于该基板通孔113与第四金属垫171相对的一端，并与延伸进入该基板通孔113的第三金属层170形成电接触。如前所述，第一金属层140、第二金属层150以及第三金属层170下方可以包含一层或数层底层结构；而上方也可以进一步包含一层或数层的上层结构。在此定义第一晶片100上介电层的第一表面131为该第一晶片表面102，而基板110的第二表面112则定义为第一晶片背面101。在本实施例中，第一晶片100表面朝下，第二晶片200则堆叠于第一晶片100的背面101，并通过金属凸块280电连接到至少一第四金属垫171。借此，垂直堆叠的第一晶片与第二晶片可以通过电连接而整合成为单一电路。每一个第一金属垫141均进一步连接至一金属凸块180，以供与其他电路晶片或模组电连接。第一金属层140以三维方式分布于电子元件层120中至少一个电子元件121上方，为使第一晶片100与第二晶片200上的接点通过金属凸块280对齐，至少一个第一金属垫141通过第一金属层140延伸进入至少其中一个介电层通孔133而电连接于该介电层通孔另一侧的第二金属垫151。
图3为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200，该第一晶片100包含一化合物半导体集成电路，而第二晶片200包含一电子电路。该第一晶片100进一步包含：一基板110、一电子元件层120以及一第三金属层170。基板110包含至少一基板通孔113，且贯穿基板的第一表面111与第二表面112。电子元件层120形成于基板110的第一表面111，包含至少一电子元件以及至少一第二金属层150。第三金属层170形成于基板的第二表面112，其包含至少一第四金属垫171，且延伸进入至少一基板通孔113。第二金属层150中，至少其中的一包含至少一第三金属垫161形成于基板通孔113上方与第四金属垫171相对的一端，并与延伸进入该基板通孔113的第三金属层170形成电接触。第三金属垫161通过第二金属层150，直接或间接地与至少一电子元件121相连接；第三金属垫161也可以连接到一第五金属垫181，其中第五金属垫181由该至少一第二金属层150所构成，且位于电子元件层120与基板相对的表面或其邻近区域。如前所述，第二金属层150以及第三金属层170下方可以包含一层或数层底层结构，而上方也可以进一步包含一层或数层的上层结构。在此定义该第一晶片上电子元件层相对于该介电层的表面为该第一晶片表面102，而基板110的第二表面112则定义为第一晶片背面101。在本实施例中，第一晶片100表面朝下，第二晶片200则堆叠于第一晶片100的背面101，并通过金属凸块280电连接到至少一第四金属垫171。借此，垂直堆叠的第一晶片与第二晶片可以通过电连接而整合成为单一电路。在第一晶片表面102附近的第五金属垫181乃进一步连接至一金属凸块180，供与其他电路晶片或模组电连接。第三金属层170以三维方式分布于电子元件层120中至少一个电子元件121下方，为使第一晶片100与第二晶片200上的接点对齐，至少一个第四金属垫171通过第三金属层170延伸进入至少其中一个基板通孔113而电连接于该基板通孔另一侧的第三金属垫161。
在前述的实施例中，第四金属层170可以形成一被动元件，如一电感器。图4为本发明的半导体集成电路的另一实施例的剖面结构示意图，其中第四金属层170于基板的第二表面112形成一电感器172。该电感器172以三维的方式配置于至少一电子元件121上，且电连接于第一晶片100。电感器172也可电连接至第二晶片或同时电连接于第一及第二晶片。
在前述的实施例中，第一晶片100为一化合物半导体集成电路晶片，而第二晶片200则可以是一化合物半导体、半导体或其他种类的集成电路晶片。第一晶片的基板材料可以是砷化镓(GaAs)、硅(Si)、碳化硅(SiC)、蓝宝石(sapphire)或氮化镓(GaN)。当第二晶片为半导体集成电路晶片时，其基板材料也可为砷化镓(GaAs)、硅(Si)、碳化硅(SiC)、蓝宝石(sapphire)或氮化镓(GaN)。第一晶片的介电层由介电物质所构成，以聚苯并恶唑(Polybenzoxazole,PBO)构成尤佳。由于第一金属层以三维方式分布于介电层上方并延伸进入介电层通孔以连接通孔另一端的第二金属垫，介电层的较佳厚度等于或大于10μm，以降低第一金属层对位于介电层下方的电子元件特性的影响。前述的电子元件层为一复合层，其包含一化合物半导体元件层以及一钝化层(passivation layer)128。该钝化层材料为介电质材料，且由氮化硅(SiN)构成尤佳，具有绝缘以及保护电子元件的功能。前述的化合物半导体元件可以是异质接面双极性电晶体(HBT)或高电子迁移率电晶体(HEMT)，该化合物半导体元件也可为氮化镓(GaN)场效电晶体(FET)。第一晶片中供电连接的金属层可分为直接与电子元件接触的金属层以及未直接与电子元件接触的金属层。与化合物半导体电子元件直接接触的第二金属层主要由金(Au)所构成，且必须不含或只含有极微量的铜成分，以确保电子元件不被铜所污染。此外也可让所有第二金属层均主要由金(Au)所构成，且不含或只含有极微量的铜成分，如此一来，电子元件层可就可以利用完全不含铜金属工艺的的前段(front-end)工艺来完成，借此让表面工艺排除铜交叉污染的问题，以确保元件的特性及工艺稳定性。至于未直接与化合物半导体电子元件接触的金属层，如第一金属层以及第三金属层间接通过第二金属层与元件形成电接触，其金属材料可以由铜(Cu)所构成以降低制作成本。铜金属层的形成可于后段(back-end)工艺中完成，借此避免前段工艺受到铜污染。第一金属层的铜金属厚度以等于或大于3μm为较佳。
根据本发明所提供的其他实施例依序说明如下:
第1实施例：
图5为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HBT功率放大器MMIC 203。该HEMT MMIC形成于一GaAs基板110上。于基板110上具有一电子元件层120，其包含一系列由伪晶型HEMT(pHEMT)元件121所构成的偏压控制电路、开关电路以及逻辑电路。该HEMT MMIC为一控制电路，用以控制HBT功率放大器的偏压条件，以及/或控制HBT功率放大器中射频信号的路径。该电子元件层120进一步包含一层或数层的氮化硅(SiN)，可用来绝缘或钝化半导体电子元件。在该HEMT MMIC上覆盖上一层由PBO所构成的介电层130作为绝缘层。该介电层130通过旋转涂布，并控制其厚度在10μm左右。由于介电层130材料PBO为光敏材料(Photosensitive material)，可利用曝光显影技术于该介电层130上制作出数个介电层通孔133，并贯穿该介电层的第一表面131与第二表面132，借此提供提供下层MMIC的电连接。在该介电层130的上利用溅镀的TiW/Cu为铜金属电镀的种子层，并在其上电镀一层约10μm厚、主要为铜的金属层做为第一金属层140。该第一金属层140形成数个第一金属垫141，用以提供HBT功率放大器MMIC的电连接。该第一金属层140自第一金属垫141延伸至介电层通孔133，其中该介电质通孔133以三维的方式分布于HEMT MMIC由pHEMT 121、电容器122以及电阻器123所构成的主动元件区域上，借此使两晶片上位于不同位置的连接节点可以达到电接触。该第一金属层140进一步延伸进入该介电质通孔133，并且与形成于介电质通孔133另一端的第二金属垫151形成电接触。在本实施例中，所有第二金属层150主要由金所构成，因此第二金属垫151也是由金所构成。每一第二金属垫151延伸自第二金属层150并电连接至HEMT MMIC元件上的pHEMT 121、电容器122以及电阻器123等。此连接方式可以避免HEMT MMIC上的化合物半导体元件直接与铜金属层接触，进而避免铜原子污染对元件特性所产生的负面影响。再者，由于第二金属均由金所构成，制作电子元件层的前段工艺将可以在不含铜的工艺条件下进行，而铜工艺则是分别于后段工艺中进行，借此排除铜交叉污染的问题，并确保元件的特性及具有较佳的工艺稳定性。第二晶片200堆叠于第一晶片100的表面102上。为了达成两晶片的电接触，于HEMT MMIC130的每一第一金属垫141上形成一第一金属凸块180。该第一金属凸块180可以由铜柱(Cupillar)所构成，并于其上形成一锡银(SnAg)的熔接金属。第二晶片200的基板为砷化镓(GaAs)基板。每一金属凸块180连接于一接触金属垫271；该接触金属垫271由一背面金属层270所构成，且形成于第二晶片200的基板210背面。每一个接触金属垫271进一步延伸至第二晶片GaAs基板210上的一基板通孔233，借此连接至HBT功率放大器MMIC上的元件，如HBT221、电容器222以及电阻器223等。此两堆叠的晶片上下翻转(正面朝下)，而第二晶片200通过金属凸块280以覆晶方式组合至模组基板90上的模组金属垫91。
第2实施例：
图6为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HEMT功率放大器MMIC 203。HEMT MMIC 103由偏压控制电路、开关电路、以及逻辑电路所构成；HEMT MMIC 103为一控制电路，用以控制HEMT功率放大器MMIC 203的偏压条件，以及/或控制其射频信号的路径。本实施例中，除了将第二晶片200的HBT功率放大器MMIC换成HEMT功率放大器MMIC以外，关于本实施例的其他描述均与第1实施例相同。
第3实施例：
图7为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HBT功率放大器MMIC 203。第二晶片200堆叠于第一晶片100的表面102，将此堆叠的第一及第二晶片反转，使第二晶片200装配于一模组基板90上，并且通过金属连结线204打线接合(wire bonding)于模组基板90上。本实施例中其他的描述均与第1实施例相同。
第4实施例：
图8为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HEMT功率放大器MMIC203所构成。第二晶片200通过金属连结线204打线接合于模组基板90上。本实施例中，除将第二晶片200的HBT功率放大器MMIC换成HEMT功率放大器MMIC以外，其他的描述均与第3实施例相同。
第5实施例：
图9为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HBT功率放大器MMIC 203。该HEMT MMIC形成于一GaAs基板110上，包含开关电路121、电容器122以及电感器124；其功能为一阻抗调节器，使针对不同输出功率以及频率而使用不同操作偏压的HBT功率放大器MMIC 203，其中HBT元件的输出端能达成阻抗匹配，以维持最佳的元件特性。由于输出阻抗为偏压条件以及操作频率的函数，使用阻抗调节器可以在操作条件改变时，仍然保持很好的阻抗匹配。在该HEMT MMIC 103上覆盖上一层由PBO所构成的介电层130。螺旋状的电感器124由以铜金属制成的第一金属层构造形成于该介电层130上。该电感器124为该阻抗调节电路的一部分。本实施例中，模组基板90上的输入/输出金属垫91与HEMT MMIC 103上的连接节点(也即其中一个第二金属垫151)的电连接，通过以三维方式分布于HEMT MMIC 103中的电子元件上方的第一金属层140连接分隔的连接节点。
第6实施例：
图10为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HEMT MMIC 103，而第二晶片200包含一HBT功率放大器MMIC 203。该HEMT MMIC的描述与实施例5相同，而该HBT功率放大器MMIC 203与实施例3相同。然而，该HBT功率放大器MMIC 203的上另覆盖一层由PBO所构成的介电层230，并于其上进一步覆盖一层由铜金属所构成的金属层240。该金属层240可视为第二晶片的第一金属层。第二晶片200上其他关于金属层的适用材料的描述，如金或铜，与第一晶片100上各金属层适用的金属材料相同。由于第一晶片100与第二晶片200的表面均有一铜金属层可供连结两晶片电路上位于平面上不同位置的连接节点，其电路布局设计将更具自由度。第二晶片200通过金属连结线204打线接合于模组基板90上。
第7实施例：
图11为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HBT功率放大器MMIC103，而第二晶片200包含一非化合物半导体晶片的电子电路晶片。本实施例的第二晶片为一Si CMOS IC，包含偏压控制电路、开关电路以及逻辑电路，并形成一控制电路，用以控制HBT功率放大器MMIC 103的偏压条件。于该HBT功率放大器MMIC 103的上依序包含：一层由PBO所构成的介电层130、一层由铜金属所构成的第一金属层140以及数个由铜金属与熔接金属所构成的金属凸块180。该第一金属层140可用以连接一第一金属垫141以及位于一介电层通孔133另一端的第二金属垫151，或用以连接一第一金属垫141以及另一个与一金属连结线接合的第一金属垫141，该第一金属层140以三维的方式分布于该HBT功率放大器MMIC 103的主动元件区域上，并连接两晶片上位于不同位置的连接节点。与HBT功率放大器MMIC的连接通过由至少一第二金属层150所形成的数个第二金属垫151。本实施例中，所有与HBT元件121以及其他电子元件122与123连接的第二金属层，或构成第二金属垫151以及第三金属垫161的第二金属层，主要由金所构成；因此铜金属层可以远离HBT功率放大器MMIC的电子元件，以避免因为铜污染而造成元件性能退化的问题。该HBT功率放大器MMIC103通过金属连结线104以打线接合的方式，以及/或通过第四金属层170并经由基板110上的基板通孔113，连接至一模组基板90上。
第8实施例：
图12为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；该第一晶片100为一HBT功率放大器MMIC103，而第二晶片200为一Si CMOS IC，用以控制HBT功率放大器MMIC 103的偏压条件。该第一晶片100上下翻转(表面朝下)，而第二晶片200得堆叠于第一晶片100的背面101。两晶片之间的电连接通过基板110背面的第三金属层170所形成的第四金属垫171。每一个第四金属垫171通过基板通孔113电连接至第三金属垫161，进而连接至第二金属垫151以及电子元件层120中的电子元件；其中第三金属垫161与第二金属垫151皆由第二金属层150所构成。在本实施例中，如同第7实施例所描述，所有第二金属层主要由金所构成；因此可以避免化合物半导体元件受到铜污染。第一金属层140由铜金属所构成，并且形成于一层由PBO所构成的介电层130上。该第一金属层140进一步形成一第一金属垫141，可用以连接至一模组基板90。该介电层130具有数个贯穿该介电层130的介电质通孔133。该第一金属层140，由介电层通孔133延伸至第一金属垫141，以三维的方式分布于该HBT功率放大器MMIC 103的主动元件区域的上，并连接至模组基板90上其中一组输入/输出金属垫91；借此使基板110背面的第四金属垫171与模组基板90上位于不同平面位置的输入/输出金属垫91形成电连接。该第一晶片100以覆晶方式，通过第一金属垫141上的金属凸块180，以及通过介电质通孔133与HBT元件121射极接触的金属凸块180，组合至该模组基板90上。
第9实施例：
图13为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；其中该第一晶片100包含一HBT功率放大器MMIC 103，而第二晶片200包含集成被动元件(Integrated passive devices)或滤波器。该集成被动元件形成于一基板上，且该基板可以由玻璃、硅或化合物半导体(如砷化镓)等材料所构成。该集成被动元件可以做为一滤波器或阻抗匹配电路等。该第二晶片200可以进一步包含一声波滤波器(acoustic filter)，如表面声波(surface acoustic wave)或体声波(bulk acoustic wave)滤波器或一薄膜体声波滤波器等，并且可以将这类声波滤波器制作在一基板(如硅基板)上。第二晶片200堆叠于第一晶片100的表面102上。该第一晶片的结构与制作方法的描述与第7实施例相同。
第10实施例：
图14为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。本实施例的设计与第9实施例相类似，其中除了将第一晶片100的HBT功率放大器MMIC取代为一HEMT功率放大器MMIC 103，其他描述均与第9实施例相同。
第11实施例：
图15为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。本实施例的设计与第9实施例相类似，其中除了该第一晶片以如第8实施例描述的覆晶方式组合至模组基板90上，其他描述均与第9实施例相同。
第12实施例：
图16为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。本实施例的设计与第11实施例相类似，其中除了将第一晶片100的HBT功率放大器MMIC取代为一HEMT功率放大器MMIC 103，其他描述均与第11实施例相同。
第13实施例：
图17为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。本实施例的半导体集成电路由数个相互堆叠的晶片所构成，包含一第一晶片100，一第二晶片200，一第三晶片300，以及一第四晶片400；其中该第一晶片100包含一HBT功率放大器MMIC 103；第二晶片200包含一阻抗匹配电路(集成被动元件)以及一偏压控制电路；第三晶片300包含一天线开关电路；第四晶片400则包含一滤波器。第二晶片200堆叠于第一晶片100的背面102；第三晶片300堆叠于第二晶200片上；而第四晶片400则堆叠于第三晶片300上。该HBT功率放大器的MMIC 103的结构与制作方法的描述与第8实施例相同。与基板模组90的连接通过形成于第一晶片100正面102的金属凸块180以及利用打线接合的方式，通过金属连接线104与第四晶片400上的滤波器连接。
第14实施例：
图18为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；且该第一晶片100包含一HBT功率放大器MMIC 103，而第二晶片200包含一电子电路晶片。该第一晶片100上下翻转(表面朝下)，并通过覆晶方式组合至一模组基板90。第二晶片200堆叠于该上下翻转的第一晶片100背面101。第二晶片包含偏压控制电路、开关电路以及逻辑电路；可形成一控制电路，用以控制HBT功率放大器MMIC 103的偏压条件；及/或形成一开关电路，用以切换第一晶片100中HBT功率放大器MMIC 103的射频信号路径。第二晶片可以是一个化合物半导体MMIC(例如一HEMTMMIC)，或是一个Si CMOS IC。第一晶片100中，第三金属层170于晶片背面102形成至少一第四金属垫171，并沿延伸至基板通孔113。第二金属层150其中的一形成一第三金属垫161，位于该基板通孔113与第四金属垫171相对的一端；并于该处通过基板通孔113与第三金属层170形成电连接。第三金属垫161通过第二金属层150，电连接至HBT元件121。第三金属垫161也连接到一形成于该电子元件层120相对于基板的表面的第四金属垫191；而该第四金属垫191进一步连接至模组基板90上的输入/输出金属垫91。第四金属垫171通过金属凸块280连接至第二晶片200。第三金属层170于第一晶片100中以三维的方式分布于一电阻器123、一电容器122以及一HBT 121功率放大器MMIC103上。通过此方式，将可连接两晶片上位于不同平面位置的连接节点。该第三金属层170的材料较佳为电镀的铜金属，并且以Pd为一种子层。
第15实施例：
图19为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。该半导体集成电路包含一第一晶片100以及一第二晶片200；第一晶片100包含一HBT功率放大器MMIC103所构成，而第二晶片200则包含一阻抗匹配电路；该阻抗匹配电路形成于砷化镓或玻璃基板，包含电感器以及/或电容器，用以匹配第一晶片100上HBT元件的输出阻抗。第二晶片200堆叠于该上下翻转的第一晶片100背面101。第二晶片也可包含一阻抗调节器，借此使其阻抗与第一晶片100的HBT在不同元件操作条件下的输出阻抗相匹配。第二晶片也可包含一滤波器电路，用以滤除在第一晶片100中HBT元件所产生基频信号以外的不必要杂讯；该滤波器电路可以由形成于硅、砷化镓或玻璃基板的集成被动元件所构成，或由一声波滤波器(acoustic filter)，如表面声波(surface acoustic wave)滤波器、体声波(bulkacoustic wave)滤波器或一薄膜体声波滤波器等所构成。本实施例中制作第一晶片100的其他描述与第14实施例相同。
第16实施例：
图20为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。本实施例的设计与第15实施例相类似，其中除了将第一晶片100的HBT功率放大器MMIC取代为一HEMT功率放大器MMIC 103，其他描述均与第15实施例相同。
第17实施例：
图21为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。本实施例的设计大部分与第15实施例相类似。在本实施例中，第四金属层170于第一晶片100基板的背面101形成一螺旋状的电感器172。该电感器172通过基板通孔113与第一晶片100的MMIC形成电连接。该电感器172、该第一晶片100上的MMIC以及该第二晶片200一起构成阻抗匹配电路以及阻抗调节电路。该第三金属层170由铜金属或含有铜金属的多层金属所构成为较佳，此乃因铜具有高电导率，可减低信号损耗。
第18实施例：
图22为根据本发明的半导体集成电路的另一实施例的剖面结构示意图。本实施例的设计与第17实施例相类似，其中除了将第一晶片100的HBT功率放大器MMIC取代为一HEMT功率放大器MMIC 103，其他描述均与第17实施例相同。
第19实施例：
图23为根据本发明的半导体集成电路的另一实施例的剖面结构示意图，其由数个相互堆叠的晶片所构成。本实施例的设计与第13实施例相类似，其中除了第一晶片100的设计与第17实施例的第一晶片100相同，其他描述均与第13实施例相同。
综上所述，本发明确实可达到预期的目的，而提供一种半导体集成电路，其由相互堆叠的电子电路晶片所构成，其中至少一晶片为一化合物半导体集成电路晶片。本发明具有以下优点：
1.借助晶片堆叠的方式构成一模组，其中构成模组的元件可以分别形成于不同晶片上。由于每一晶片可以各自拥有最佳化的元件布局设计，并且只要通过该晶片所需的工艺步骤就可制作完成；因此，相较于将所有模组元件整合于单一晶片，制作成本将大幅降低。此外，相较于将不同晶片以平面方式整合至一模组基板上，以三维垂直堆叠的方式也可以大幅缩小整体模组的面积。
2.不同晶片之间，或不同电路单元之间的相互连接可以通过晶片表面或背面的金属层来达成。表面或背面的金属层可以形成于元件主动区域上，借此可以连接两晶片位于不同水平位置的连接节点。因此，对于晶片上连接节点的布局设计将更具弹性。相较于将晶片以平面方式整合至单一模组基板上，本发明可以缩短元件之间相互连接的距离，因而降低信号的损耗与相互干扰。
3.虽然不同晶片之间的相互连结是通过铜金属来达成，与化合物半导体元件接触的金属层仍保持使用金；借此将可避免铜元素扩散进入化合物半导体元件而导致元件特性变差。再者，电子元件层的工艺步骤将可于不含铜金属的前段工艺来完成，至于铜金属层的部分则可于后段工艺中完成；借此让表面工艺排除铜交叉污染的问题。如此一来，即使整个化合物半导体MMIC的工艺步骤中包含铜金属工艺，仍然可以确保元件特性的稳定性。
4.晶片的背面金属层可以进一步形成一电感器或其他被动元件。将电感器制作于晶片背面可以节省整个电路所占据的面积，进而缩小晶片的尺寸。当背面金属层主要由铜所构成时，晶片背面将可以制作出具有高品质因子的电感器。
本发明的化合物半导体集成电路晶片，其具有分布于元件主动区域上的表面金属层，也可以延伸应用于非相互堆叠的晶片。化合物半导体集成电路晶片可以通过表面金属层，连结至其他任何电子电路。例如当一晶片被堆叠于一模组基板上，可以通过凸块熔接或金属线打线接合的方式，将位于模组上的金属垫电连接至晶片表面的金属垫；因此，金属垫的布局设计也将更具弹性。
本发明确实可达到预期的目的，并具产业利用的价值，爰依法提出专利申请。又上述说明与附图仅是用以说明本发明的实施例，凡熟于此业技艺的人士，仍可做等效的局部变化与修饰，其并未脱离本发明的技术与精神。

Claims (31)

1.一种半导体集成电路，其特征在于，包括：
一第一晶片，该第一晶片包含一化合物半导体集成电路，还包括：
一基板，具有至少一基板通孔贯穿该基板的第一表面与第二表面；
一电子元件层，形成于该基板之上，具有一钝化层和位于该钝化层内的至少一电子元件及至少一第二金属层，该电子元件包括至少一化合物半导体电子元件；
一介电层，形成于该电子元件层上，且具有至少一介电层通孔贯穿该介电层的第一表面与第二表面；
一第一金属层，主要由铜所构成，该第一金属层形成至少一第一金属垫于该介电层第一表面的上，且从该至少一第一金属垫延伸进入至少一介电层通孔；
其中，至少一该第二金属层连接于至少一该电子元件，至少一该第二金属层包含至少一第二金属垫形成于一介电层通孔位于该介电层的第二表面的一端，并与延伸进入该介电层通孔的第一金属层形成电接触，且至少一该第二金属层形成至少一第三金属垫于一基板通孔位于该基板的第一表面的一端，其中所有与该至少一化合物半导体电子元件所接触的第二金属层主要由金所构成；以及
一第三金属层，具有至少一第四金属垫形成于该基板的第二表面，且从每一个该至少一第四金属垫延伸进入至少一基板通孔，借此与配置于基板通孔另一侧的第三金属垫形成电接触；以及
一第二晶片，包含一电子电路，且堆叠于该第一晶片基板的第二表面上，并通过连接到至少其中一个该第四金属垫，与第一晶片形成电连接；
其中该第一金属层以三维方式分布于该电子元件层中至少一个电子元件上方，而至少一个该第一金属垫通过该第一金属层延伸进入至少其中一个该介电层通孔而电连接于该介电层通孔另一侧的第二金属垫中的至少一个。
2.如权利要求1所述的半导体集成电路，其特征在于，所有该第二金属层主要由金所构成。
3.如权利要求1所述的半导体集成电路，其特征在于，该第三金属层主要由铜所构成。
4.如权利要求1所述的半导体集成电路，其特征在于，该第一晶片的基板由砷化镓(GaAs)、硅(Si)、碳化硅(SiC)、蓝宝石(sapphire)或氮化镓(GaN)所构成。
5.如权利要求1所述的半导体集成电路，其特征在于，该介电层由介电物质聚苯恶唑(Polybenzoxazole,PBO)所构成。
6.如权利要求1所述的半导体集成电路，其特征在于，该介电层的厚度等于或大于10μm。
7.如权利要求1所述的半导体集成电路，其特征在于，该第一晶片包含一HBT MMIC或一HEMT MMIC。
8.如权利要求1所述的半导体集成电路，其特征在于，该第一晶片包含一氮化镓(GaN)场效电晶体(FET)MMIC。
9.如权利要求1所述的半导体集成电路，其特征在于，该第一晶片包含一功率放大器MMIC。
10.如权利要求9所述的半导体集成电路，其特征在于，该第二晶片包含下列电路中的一种：一偏压控制电路，用以控制第一晶片中该至少一电子元件的偏压条件；一开关电路，用以控制第一晶片信号路径；一天线开关电路，用以连接第一晶片中功率放大器输出端至天线；一阻抗调节电路，用以调节阻抗大小，并使其随第一晶片中功率放大器的偏压条件及工作频率而改变；以及一由被动元件所构成的阻抗匹配电路，用以匹配第一晶片中功率放大器的输入与/或输出端的阻抗。
11.如权利要求1所述的半导体集成电路，其特征在于，该第二晶片包含一化合物半导体MMIC。
12.如权利要求11所述的半导体集成电路，其特征在于，该第二晶片的基板由砷化镓(GaAs)所构成。
13.如权利要求1所述的半导体集成电路，其特征在于，该第二晶片包含一硅互补式金属氧化物半导体(Si CMOS)集成电路。
14.如权利要求1所述的半导体集成电路，其特征在于，该第二晶片包含至少一被动元件集成整合于同一基板，且该基板的材料可为硅、砷化镓或玻璃。
15.如权利要求1所述的半导体集成电路，其特征在于，该第二晶片包含一滤波器。
16.一种半导体集成电路，其特征在于，包括：
一第一晶片，该第一晶片包含一化合物半导体集成电路，还包括：
一基板，具有至少一基板通孔贯穿该基板的第一表面与第二表面；
一电子元件层，形成于该基板的第一表面，具有一钝化层和位于该钝化层内的至少一电子元件及至少一第二金属层，其中该电子元件包含至少一化合物半导体电子元件，至少一该第二金属层连接于至少一该电子元件，至少一该第二金属层形成至少一第三金属垫于一基板通孔位于该基板第一表面的一端；以及
一第三金属层，具有至少一第四金属垫形成于该基板的第二表面，且从每一个该至少一第四金属垫延伸进入至少一基板通孔，借此与配置于基板通孔另一侧的第三金属垫形成电接触；以及
一第二晶片，包含一电子电路，且堆叠于该第一晶片基板的第二表面上，并通过连接到至少其中一个该第四金属垫，与第一晶片形成电连接；
其中该第三金属层以三维方式分布于该电子元件层中至少一个电子元件下方，而至少一个该第四金属垫通过该第三金属层延伸进入至少其中一个该基板通孔而电连接于该基板通孔另一侧的第三金属垫中的至少一个。
17.如权利要求16所述的半导体集成电路，其特征在于，至少一个该第二金属层进一步形成一第五金属垫，且位于该电子元件层的表面(未与该基板接触的表面)或其邻近区域；其中至少一个该第三金属垫电连接到至少其中一个该第五金属垫层。
18.如权利要求16所述的半导体集成电路，其特征在于，该第三金属层主要由铜所构成。
19.如权利要求18所述的半导体集成电路，其特征在于，所有与化合物半导体元件接触的该第二金属层主要由金所构成。
20.如权利要求18所述的半导体集成电路，其特征在于，所有该第二金属层主要由金所构成。
21.如权利要求16所述的半导体集成电路，其特征在于，至少一个该第三金属层进一步形成一电感器，其位于第一晶片基板的第二表面，且分布涵盖至少一个该电子元件，并且该电感器电连接至该第一晶片、第二晶片或同时连接至该第一晶片以及第二晶片。
22.如权利要求16所述的半导体集成电路，其特征在于，该第一晶片的基板由砷化镓(GaAs)、硅(Si)、碳化硅(SiC)、蓝宝石(sapphire)或氮化镓(GaN)所构成。
23.如权利要求16所述的半导体集成电路，其特征在于，该第一晶片包含一HBT MMIC或一HEMT MMIC。
24.如权利要求16所述的半导体集成电路，其特征在于，该第一晶片包含一氮化镓(GaN)场效电晶体(FET)MMIC。
25.如权利要求16所述的半导体集成电路，其特征在于，该第一晶片包含一功率放大器MMIC。
26.如权利要求25所述的半导体集成电路，其特征在于，该第二晶片包含下列电路中的一种：一偏压控制电路，用以控制第一晶片中该至少一电子元件的偏压条件；一开关电路，用以控制第一晶片信号路径；一天线开关电路，用以连接第一晶片中功率放大器输出端至天线；一阻抗调节电路，用以调节阻抗大小，并使其随第一晶片中功率放大器的偏压条件及工作频率而改变；以及一由被动元件所构成的阻抗匹配电路，用以匹配第一晶片中功率放大器的输入与/或输出端的阻抗。
27.如权利要求16所述的半导体集成电路，其特征在于，该第二晶片包含一化合物半导体MMIC。
28.如权利要求27所述的半导体集成电路，其特征在于，该第二晶片的基板由砷化镓(GaAs)所构成。
29.如权利要求16所述的半导体集成电路，其特征在于，该第二晶片包含一硅互补式金属氧化物半导体(Si CMOS)集成电路。
30.如权利要求16所述的半导体集成电路，其特征在于，该第二晶片包含至少一被动元件集成整合于同一基板，且该基板的材料可为硅、砷化镓或玻璃。
31.如权利要求16所述的半导体集成电路，其特征在于，该第二晶片包含一滤波器。
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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9093506B2 (en) * 2012-05-08 2015-07-28 Skyworks Solutions, Inc. Process for fabricating gallium arsenide devices with copper contact layer
GB2533767B (en) * 2014-12-16 2019-06-19 Leonardo Mw Ltd Integrated circuits and methods of manufacturing.
US10075132B2 (en) 2015-03-24 2018-09-11 Nxp Usa, Inc. RF amplifier with conductor-less region underlying filter circuit inductor, and methods of manufacture thereof
US9871107B2 (en) * 2015-05-22 2018-01-16 Nxp Usa, Inc. Device with a conductive feature formed over a cavity and method therefor
US10276541B2 (en) * 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
US9787254B2 (en) 2015-09-23 2017-10-10 Nxp Usa, Inc. Encapsulated semiconductor device package with heatsink opening, and methods of manufacture thereof
KR102492527B1 (ko) * 2015-10-12 2023-01-31 삼성전자주식회사 데이터 스토리지 소자 및 그를 포함하는 전자 장치
TWI559449B (zh) * 2015-10-19 2016-11-21 穩懋半導體股份有限公司 化合物半導體積體電路之電路佈局方法
CN106672888B (zh) * 2015-11-11 2022-03-11 恩智浦美国有限公司 封装集成电路管芯的方法和器件
WO2017111769A1 (en) * 2015-12-22 2017-06-29 Intel Corporation Microelectronic devices designed with compound semiconductor devices and integrated on an inter die fabric
US10573608B2 (en) * 2015-12-22 2020-02-25 Intel Corporation Microelectronic devices designed with high frequency communication devices including compound semiconductor devices integrated on a die fabric on package
CN108288616B (zh) * 2016-12-14 2023-04-07 成真股份有限公司 芯片封装
US10069464B1 (en) * 2017-02-21 2018-09-04 The Boeing Company 3D low flux, high-powered MMIC amplifiers
US10062683B1 (en) 2017-02-27 2018-08-28 Qualcomm Incorporated Compound semiconductor transistor and high-Q passive device single chip integration
WO2019065668A1 (ja) 2017-09-29 2019-04-04 株式会社村田製作所 高周波モジュールおよび通信装置
CN109494218B (zh) * 2018-09-30 2021-07-30 华东计算技术研究所（中国电子科技集团公司第三十二研究所） 双面超导量子芯片
TWI726463B (zh) * 2018-10-30 2021-05-01 精材科技股份有限公司 晶片封裝體與電源模組
CN109534278B (zh) * 2018-11-01 2020-12-15 中国科学院半导体研究所 声学滤波器与hemt异构集成的结构及其制备方法
KR102083742B1 (ko) * 2018-11-13 2020-03-02 광운대학교 산학협력단 안정된 성능을 가지는 반도체 장치
DE102019211468A1 (de) 2019-07-31 2021-02-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Vertikale verbindungshalbleiter-struktur und verfahren zum herstellen derselbigen
DE102019211465A1 (de) * 2019-07-31 2021-02-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Halbleiter-bauelementstruktur mit verbindungshalbleiter und verfahren zum herstellen derselbigen
CN111477612B (zh) * 2020-03-23 2022-06-10 中国电子科技集团公司第十三研究所 可调芯片
WO2022124035A1 (ja) * 2020-12-11 2022-06-16 株式会社村田製作所 高周波モジュールおよび通信装置
US11749746B2 (en) 2021-04-29 2023-09-05 Qualcomm Incorporated Radio frequency front end (RFFE) hetero-integration
CN115579299B (zh) * 2022-11-21 2023-04-14 常州承芯半导体有限公司 半导体结构及其形成方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1125999A (zh) * 1994-02-18 1996-07-03 艾利森电话股份有限公司 用于与射频反应溅射的钛-钨和金微电路互连的抗电迁移的金属化结构
CN1503359A (zh) * 2002-11-26 2004-06-09 新光电气工业株式会社 电子元件封装结构及制造该电子元件封装结构的方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037044A (en) * 1998-01-08 2000-03-14 International Business Machines Corporation Direct deposit thin film single/multi chip module
US6825559B2 (en) * 2003-01-02 2004-11-30 Cree, Inc. Group III nitride based flip-chip intergrated circuit and method for fabricating
US7088003B2 (en) * 2004-02-19 2006-08-08 International Business Machines Corporation Structures and methods for integration of ultralow-k dielectrics with improved reliability
JP2008085362A (ja) * 2004-12-20 2008-04-10 Sanyo Electric Co Ltd 半導体装置及び半導体モジュール
JP2007317857A (ja) * 2006-05-25 2007-12-06 Fujikura Ltd 半導体装置及びその製造方法
US7615863B2 (en) * 2006-06-19 2009-11-10 Northrop Grumman Space & Missions Systems Corp. Multi-dimensional wafer-level integrated antenna sensor micro packaging
JP2008103387A (ja) * 2006-10-17 2008-05-01 Murata Mfg Co Ltd 半導体装置
JP5192163B2 (ja) * 2007-03-23 2013-05-08 住友電工デバイス・イノベーション株式会社 半導体装置
US7508267B1 (en) * 2007-09-28 2009-03-24 Rockwell Collins, Inc. GaN based digital controlled broadband MMIC power amplifier
SG156550A1 (en) * 2008-05-06 2009-11-26 Gautham Viswanadam Wafer level integration module with interconnects
KR101202020B1 (ko) * 2008-11-14 2012-11-16 한국전자통신연구원 웨이퍼 수준의 집적회로 칩 조정 시스템 및 집적회로 칩 조정 방법
JP2010171386A (ja) * 2008-12-26 2010-08-05 Sanyo Electric Co Ltd 半導体装置及びその製造方法
US8426961B2 (en) * 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
WO2012011207A1 (ja) * 2010-07-21 2012-01-26 パナソニック株式会社 検査用パッド電極を除去する工程を備える半導体装置の製造方法
US20120193785A1 (en) * 2011-02-01 2012-08-02 Megica Corporation Multichip Packages
KR20130013820A (ko) * 2011-07-29 2013-02-06 한국전자통신연구원 반도체 장치 및 그 제조 방법
JP2012109614A (ja) * 2012-02-24 2012-06-07 Seiko Epson Corp 半導体装置、回路基板及び電子機器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1125999A (zh) * 1994-02-18 1996-07-03 艾利森电话股份有限公司 用于与射频反应溅射的钛-钨和金微电路互连的抗电迁移的金属化结构
CN1503359A (zh) * 2002-11-26 2004-06-09 新光电气工业株式会社 电子元件封装结构及制造该电子元件封装结构的方法

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