TWI726463B - 晶片封裝體與電源模組 - Google Patents

晶片封裝體與電源模組 Download PDF

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TWI726463B
TWI726463B TW108138708A TW108138708A TWI726463B TW I726463 B TWI726463 B TW I726463B TW 108138708 A TW108138708 A TW 108138708A TW 108138708 A TW108138708 A TW 108138708A TW I726463 B TWI726463 B TW I726463B
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ground
layer
top surface
functional layer
chip package
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TW202017130A (zh
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劉滄宇
李柏漢
簡瑋銘
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精材科技股份有限公司
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Abstract

一種晶片封裝體包含耐高壓基板與裝置晶片。耐高壓基板具有本體、功能層與接地層。本體具有相對的頂面與底面、貫穿頂面與底面的穿孔及圍繞穿孔的側壁。功能層位於頂面上。接地層覆蓋底面與側壁。裝置晶片位於功能層上，且具有朝向本體的接地墊。接地墊電性連接穿孔中的接地層。

Description

晶片封裝體與電源模組
本案是有關於一種晶片封裝體與一種具有此晶片封裝體的電源模組。
一般而言，晶片封裝體的頂面具有複數個導電墊。當晶片封裝體接合於電路板後，可採用打線製程將這些導電墊與電路板電性連接。這些導電墊的一部分與晶片封裝體的接地功能有關，另一部分則與晶片封裝體本身的功能有關(例如功率處理、指紋辨識、影像處理等等)。
然而，為了降低阻值，通常會在晶片封裝體的每一接地墊接合兩條以上的導線來電性連接電路板的接地區。如此一來，不僅導線易產生干涉，且無法降低導線的材料與製造成本。此外，由於晶片封裝體的面積有限，將接地墊設置於晶片封裝體的頂面並不利於微小化設計。
本發明之一技術態樣為一種晶片封裝體。
根據本發明一實施方式，一種晶片封裝體包含耐 高壓基板與裝置晶片。耐高壓基板具有本體、功能層與接地層。本體具有相對的頂面與底面、貫穿頂面與底面的穿孔及圍繞穿孔的側壁。功能層位於頂面上。接地層覆蓋底面與側壁。裝置晶片位於功能層上，且具有朝向本體的接地墊。接地墊電性連接穿孔中的接地層。
在本發明一實施方式中，上述功能層的材質包含氮化鎵(GaN)。
在本發明一實施方式中，上述功能層的厚度介於3μm至4μm的範圍。
在本發明一實施方式中，上述接地層大致覆蓋本體的整個底面。
在本發明一實施方式中，上述接地層的面積大於接地墊的面積。
在本發明一實施方式中，上述接地層的材質包含銅。
在本發明一實施方式中，上述裝置晶片具有朝向功能層的底面，接地墊位於裝置晶片的底面上。
在本發明一實施方式中，上述接地墊更位於功能層中。
在本發明一實施方式中，上述裝置晶片具有朝向功能層的底面，接地墊位於裝置晶片的底面中。
在本發明一實施方式中，上述穿孔與接地層更延伸至功能層中。
在本發明一實施方式中，上述穿孔與接地層更延 伸至裝置晶片中。
在本發明一實施方式中，上述裝置晶片具有背對功能層的頂面，裝置晶片的頂面具有導電墊。
本發明之一技術態樣為一種電源模組。
根據本發明一實施方式，一種電源模組包含電路板與晶片封裝體。電路板具有接地區。晶片封裝體位於電路板的接地區上。晶片封裝體包含耐高壓基板與裝置晶片。耐高壓基板具有本體、功能層與接地層。本體具有相對的頂面與底面、貫穿頂面與底面的穿孔及圍繞穿孔的側壁。功能層位於頂面上。接地層覆蓋底面與側壁，且接地層位於電路板的接地區上且電性連接接地區。裝置晶片位於功能層上，且具有朝向本體的接地墊。接地墊電性連接穿孔中的接地層。
在本發明一實施方式中，上述電路板具有打線區。裝置晶片具有背對功能層的頂面。裝置晶片的頂面具有導電墊。電源模組更包含導線。導線的兩端分別位於打線區與導電墊上。
在本發明一實施方式中，上述電源模組更包含接合導電層。接合導電層位於耐高壓基板的接地層與電路板的接地區之間。
在本發明一實施方式中，上述接合導電層為銀膠或焊料。
在本發明上述實施方式中，由於耐高壓基板的接地層覆蓋本體的底面與圍繞穿孔的側壁，且穿孔中的接地層電性連接位在功能層上的裝置晶片的接地墊，因此當晶片封裝體 設置於電路板的接地區上時，接地層可與電路板的接地區接觸而彼此電性連接。如此一來，晶片封裝體的裝置晶片的接地墊便可透過耐高壓基板的接地層與電路板的接地區達到接地的效果，不僅可降低阻值減少雜訊，且因接地墊不需打線，接地墊不用被限制在裝置晶片的頂面，可降低導線的材料與製造成本。此外，與裝置晶片功能相關的導電墊可設於裝置晶片的頂面，連接導電墊的導線不會受到裝置晶片的接地墊與耐高壓基板的接地層的干涉。由於晶片封裝體的面積有限，因此本揭露之裝置晶片的接地墊與耐高壓基板的接地層的有利於微小化設計。
100、100a、100b‧‧‧晶片封裝體
110、110a、110b‧‧‧耐高壓基板
111‧‧‧頂面
112‧‧‧本體
113‧‧‧底面
114、114a、114b‧‧‧穿孔
115‧‧‧側壁
116‧‧‧功能層
118‧‧‧接地層
120、120a、120b‧‧‧裝置晶片
121‧‧‧底面
122‧‧‧接地墊
123‧‧‧頂面
124‧‧‧導電墊
130‧‧‧導線
200、200a、200b‧‧‧電源模組
210‧‧‧電路板
212‧‧‧接地區
214‧‧‧打線區
220‧‧‧接合導電層
2-2‧‧‧線段
D1、D2‧‧‧厚度
W、Wa、Wb‧‧‧寬度
第1圖繪示根據本發明一實施方式之電源模組的俯視圖。
第2圖繪示第1圖之電源模組沿線段2-2的剖面圖。
第3圖繪示第2圖之晶片封裝體的底視圖。
第4圖繪示根據本發明一實施方式之電源模組的剖面圖，其剖面位置與第2圖相同。
第5圖繪示根據本發明一實施方式之電源模組的剖面圖，其剖面位置與第2圖相同。
第6圖繪示第5圖之穿孔之深寬比的相關數據。
以下將以圖式揭露本發明之複數個實施方式，為 明確說明，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
第1圖繪示根據本發明一實施方式之電源模組200的俯視圖。第2圖繪示第1圖之電源模組200沿線段2-2的剖面圖。同時參閱第1圖與第2圖，電源模組200包含電路板210與晶片封裝體100。電路板210具有接地區212，接地區212可以為接地用的導電墊。晶片封裝體100位於電路板210的接地區212上。電路板210的接地區212可以為單一大面積的導電結構，也可以為多個小面積的導電結構，並不用以限制本發明。晶片封裝體100包含耐高壓基板110與裝置晶片120。耐高壓基板110具有本體112、功能層116與接地層118。耐高壓基板110的本體112具有相對的頂面111與底面113、貫穿頂面111與底面113的穿孔114、及圍繞穿孔114的側壁115。功能層116位於頂面111上。接地層118覆蓋底面113與覆蓋圍繞穿孔114的側壁115，且接地層118位於電路板210的接地區212上且電性連接接地區212。裝置晶片120位於功能層116上，且裝置晶片120具有朝向耐高壓基板110之本體112的接地墊122。接地墊122電性連接穿孔114中的接地層118，舉例來說，接地墊122與接地層118接觸。
在本實施方式中，耐高壓基板110可以為功率元件，但並不用以限制本發明。耐高壓基板110的本體112的材 質包含矽，功能層116的材質包含氮化鎵(GaN)。如此一來，功能層116可讓耐高壓基板110具有耐高壓、漏電流低、高頻表現佳等特性。功能層116可採蒸鍍的方式形成於本體112的頂面111上，其中功能層116的厚度D1可介於3μm至4μm的範圍，本體112的厚度D2可小於4mil。此外，接地層118的材質可以包含銅，可採濺鍍的方式形成於本體112的底面113上與圍繞穿孔114的側壁115上。
由於耐高壓基板110的接地層118覆蓋本體112的底面113與圍繞穿孔114的側壁115，且穿孔114中的接地層118電性連接位在功能層116上的裝置晶片120的接地墊122，因此當晶片封裝體100設置於電路板210的接地區212上時，接地層118可與電路板210的接地區212接觸而彼此電性連接。如此一來，晶片封裝體100的裝置晶片120的接地墊122便可透過耐高壓基板110的接地層118與電路板210的接地區212達到接地的效果，不僅可降低阻值減少雜訊，且因接地墊122不需打線，接地墊122不用被限制在裝置晶片120的頂面123，可降低導線的材料與製造成本。
在本實施方式中，裝置晶片120具有朝向功能層116的底面121，接地墊122位於裝置晶片120的底面121上，因此接地墊122可位於耐高壓基板110的功能層116中。
此外，裝置晶片120具有背對功能層116的頂面123，裝置晶片120的頂面123具有導電墊124。導電墊124與裝置晶片120的功能相關，例如功率處理、指紋辨識、影像處理等等，非用於接地。電路板210具有打線區214。電源模組 200更包含導線130。導線130的兩端分別位於打線區214與導電墊124上，以電性連接打線區214與導電墊124。導線130可採打線製程固定於電路板210的打線區214與裝置晶片120的導電墊124。連接導電墊124的導線130不會受到裝置晶片120的接地墊122與耐高壓基板110的接地層118的干涉。由於晶片封裝體100的面積有限，因此本揭露之裝置晶片120的接地墊122與耐高壓基板110的接地層118的有利於微小化設計。
在本實施方式中，電源模組200更包含接合導電層220。接合導電層220位於耐高壓基板110的接地層118與電路板210的接地區212之間。接合導電層220可以為銀膠或焊料，使得接地層118與接地區212接合且彼此電性連接。
第3圖繪示第2圖之晶片封裝體100的底視圖。同時參閱第2圖與第3圖，接地層118的材質為金屬(例如銅)，可視為大面積的散熱結構，提升晶片封裝體100的熱傳導性(Thermal conductivity)。在本實施方式中，接地層118大致覆蓋本體112的整個底面113。此外，耐高壓基板110的接地層118的面積大於裝置晶片120的接地墊122的面積。
應瞭解到，已敘述過的元件連接關係、材料與功效將不再重複贅述，合先敘明。在以下敘述中，將說明其他形式的晶片封裝體。
第4圖繪示根據本發明一實施方式之電源模組200a的剖面圖，其剖面位置與第2圖相同。電源模組200a包含電路板210與晶片封裝體100a。晶片封裝體100a位於電路板210的接地區212上。晶片封裝體100a包含耐高壓基板110a與 裝置晶片120a。裝置晶片120a除了具有接地墊122外，還具有與底面121共面的接地墊122a。與第2圖實施方式不同的地方在於，裝置晶片120a的接地墊122a位於裝置晶片120a的底面121中。為了讓耐高壓基板110a的接地層118a可電性連接裝置晶片120a的接地墊122a，耐高壓基板110a的穿孔114a與接地層118a進一步延伸至功能層116中，以讓接地層118a可延伸至接地墊122a。在本實施方式中，接地墊122a的下表面高於接地墊122的下表面。
第5圖繪示根據本發明一實施方式之電源模組200b的剖面圖，其剖面位置與第2圖相同。電源模組200b包含電路板210與晶片封裝體100b。晶片封裝體100b位於電路板210的接地區212上。晶片封裝體100b包含耐高壓基板110b與裝置晶片120b。裝置晶片120b除了具有接地墊122、122a外，還具接地墊122b。接地墊122a、122b位於裝置晶片120b的底面121中。與第4圖實施方式不同的地方在於，裝置晶片120b的接地墊122b的位置高於接地墊122a的位置。也就是說，接地墊122b較接地墊122a靠近裝置晶片120b的頂面123。為了讓耐高壓基板110b的接地層118b可電性連接裝置晶片120b的接地墊122b，耐高壓基板110b的穿孔114b與接地層118b進一步延伸至裝置晶片120b中，以讓接地層118b可延伸至接地墊122b。在本實施方式中，接地墊122b的下表面高於接地墊122a的下表面，且接地墊122a的下表面高於接地墊122的下表面。
第6圖繪示第5圖之穿孔114、114a、114b之深寬 比的相關數據。同時參閱第5圖與第6圖，在一實施方式中，耐高壓基板110b的本體112的厚度D2約為85μm，本體112中之穿孔114底部的寬度W約為70μm，本體112中之穿孔114a底部的寬度Wa約為55μm，本體112中之穿孔114b底部的寬度Wb約為45μm，其中寬度W、Wa、Wb為底部關鍵尺寸(Bottom critical dimension；BCD)。經過計算，可得到本體112中之穿孔114的深寬比(Aspect ratio)約為1.21，本體112中之穿孔114a的深寬比約為1.55，本體112中之穿孔114b的深寬比約為1.89。也就是說，電源模組200b可利用穿孔延伸至功能層116及/或裝置晶片120b中來調整穿孔深寬比，而不需更換不同厚度的本體112，對於設計上來說有所助益。
此外，耐高壓基板110b還可進一步具有另外的兩穿孔(未繪示)，本體112中之此兩穿孔底部的寬度分別約為90μm與80μm。經過計算，如第6圖所示，可得到本體112中之此兩穿孔的深寬比分別約為0.94與1.06。
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧晶片封裝體
110‧‧‧耐高壓基板
111‧‧‧頂面
112‧‧‧本體
113‧‧‧底面
114‧‧‧穿孔
115‧‧‧側壁
116‧‧‧功能層
118‧‧‧接地層
120‧‧‧裝置晶片
121‧‧‧底面
122‧‧‧接地墊
123‧‧‧頂面
124‧‧‧導電墊
130‧‧‧導線
200‧‧‧電源模組
210‧‧‧電路板
212‧‧‧接地區
214‧‧‧打線區
220‧‧‧接合導電層
D1、D2‧‧‧厚度

Claims (15)

  1. 一種晶片封裝體，包含：一耐高壓基板，具有一本體、一功能層與一接地層，該本體具有相對的一頂面與一底面、貫穿該頂面與該底面的一穿孔及圍繞該穿孔的一側壁，其中該功能層位於該頂面上，該接地層覆蓋該底面與該側壁；以及一裝置晶片，位於該功能層上，且具有朝向該本體的一接地墊與背對該功能層的一頂面，該裝置晶片的該頂面的邊緣部分具有一導電墊，且該裝置晶片的該頂面的中央部分不具有導體，其中該接地墊電性連接該穿孔中的該接地層。
  2. 如請求項1所述的晶片封裝體，其中該功能層的材質包含氮化鎵(GaN)。
  3. 如請求項1所述的晶片封裝體，其中該功能層的厚度介於3μm至4μm的範圍。
  4. 如請求項1所述的晶片封裝體，其中該接地層大致覆蓋該本體的整個該底面。
  5. 如請求項1所述的晶片封裝體，其中該接地層的面積大於該接地墊的面積。
  6. 如請求項1所述的晶片封裝體，其中該接地層的材質包含銅。
  7. 如請求項1所述的晶片封裝體，其中該裝置晶片具有朝向該功能層的一底面，該接地墊位於該裝置晶片的該底面上。
  8. 如請求項7所述的晶片封裝體，其中該接地墊更位於該功能層中。
  9. 如請求項1所述的晶片封裝體，其中該裝置晶片具有朝向該功能層的一底面，該接地墊位於該裝置晶片的該底面中。
  10. 如請求項9所述的晶片封裝體，其中該穿孔與該接地層更延伸至該功能層中。
  11. 如請求項10所述的晶片封裝體，其中該穿孔與該接地層更延伸至該裝置晶片中。
  12. 一種電源模組，包含：一電路板，具有一接地區；以及一晶片封裝體，位於該電路板的該接地區上，包含：一耐高壓基板，具有一本體、一功能層與一接地層，該本體具有相對的一頂面與一底面、貫穿該頂面與該底面的一穿孔及圍繞該穿孔的一側壁，其中該功能層位於該頂面上，該接地層覆蓋該底面與該側壁，且該接 地層位於該電路板的該接地區上且電性連接該接地區；以及一裝置晶片，位於該功能層上，且具有朝向該本體的一接地墊與背對該功能層的一頂面，該裝置晶片的該頂面的邊緣部分具有一導電墊，且該裝置晶片的該頂面的中央部分不具有導體，其中該接地墊電性連接該穿孔中的該接地層。
  13. 如請求項12所述的電源模組，其中該電路板具有一打線區，該電源模組更包含：一導線，其兩端分別位於該打線區與該導電墊上。
  14. 如請求項12所述的電源模組，更包含：一接合導電層，位於該耐高壓基板的該接地層與該電路板的該接地區之間。
  15. 如請求項14所述的電源模組，其中該接合導電層為銀膠或焊料。
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