TWI533426B - 導線架及半導體裝置 - Google Patents

導線架及半導體裝置 Download PDF

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Publication number
TWI533426B
TWI533426B TW101110141A TW101110141A TWI533426B TW I533426 B TWI533426 B TW I533426B TW 101110141 A TW101110141 A TW 101110141A TW 101110141 A TW101110141 A TW 101110141A TW I533426 B TWI533426 B TW I533426B
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Taiwan
Prior art keywords
plating layer
layer
lead frame
plating
wire
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TW101110141A
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English (en)
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TW201246492A (en
Inventor
吳宗昭
吉江崇
大串正幸
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新光電氣工業股份有限公司
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Publication of TW201246492A publication Critical patent/TW201246492A/zh
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Publication of TWI533426B publication Critical patent/TWI533426B/zh

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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L23/495—Lead-frames or other flat leads
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Description

導線架及半導體裝置
此申請案係基於且主張在2011年3月29日提出申請之日本專利申請號2011-073264之前案整合如下做參考的全部內容之優先權權益。
本發明係關於一種導線架及一種半導體裝置。
供半導體裝置使用之導線架係用於鑲嵌半導體元件。當半導體元件鑲嵌在導線架後，半導體元件被以封裝樹脂封裝且結合半導體元件與導線架。半導體元件被鑲嵌在例如印刷線路版等的基材上。傳統的導線架通常包含半導體元件鑲嵌於上的晶粒銲墊、經由線接合耦接於半導體元件之電極的內導線、以及當鑲嵌半導體元件於基材上時作為外部連接端的外導線。此類導線架相對於半導體元件需要具備良好的接合性。進一步而言，接合線必須具備良好的線接合性以連接半導體元件至內導線，且外導線必須具有良好的線接合性以連接半導體裝置至例如基材的鑲嵌物件。將半導體裝置鑲嵌到基材時通常使用銲接。現今，廣用的導線架包含預先形成在外導線上以增進外導線接合性的銲料層。
相對的，容許半導體元件鑲嵌在基材上而不用銲料層的導線架亦被使用著。例如，如圖15所示，導線架50包含銅或銅 合金基礎材料51、作為最底層或基礎層的鎳鍍層11A、鈀鍍層12A、以及黃金鍍層14A。鍍層11A、12A、以及14A依序層疊在銅或或銅合金基礎材料51上(參照，例如，日本專利公開號4-115558及國際公開號WO2005/117112)。此類結構的導線架50被稱為預鍍鈀導線架(palladium pre-plated lead frame,Pd-PPF)。在導線架50，黃金鍍層14A，形成在最上層，防止導線架的氧化並且提供連接半導體元件至內導線之接合線(例如黃金線)好的線接合性。
黃金線時常用作連接線。然而，近年來金價高漲。因此，銅線(其相較於黃金線的材料成本便宜許多)的使用快速增加。盡管如此，與黃金線比較，銅線較易氧化、較硬、且延展性較低。是故，銅線的線連接性不佳。圖15所示的導線架50包含具有相對硬表面的連接部分。本發明之發明人著手研究並作出結論認為當連接銅線至導線架50時銅線時常造成滑動。因此，當用在導線架之線接合時銅線比黃金線更難接合。基此，銅線用於導線架50之線接合可能導致失敗等問題。
本發明之目的之一在於提供一種導線架以及一種半導體裝置，可增加線連接的可靠度。
本發明的一方面係一種供樹脂封裝型半導體裝置用之導線架，其中半導體裝置包含半導體元件具有電極、接合線連接到半導體元件之電極、以及封裝樹脂覆蓋並封裝半導體元件與 接合線。導線架包含基材架，其係包含複數個導線；四層鍍層施作於基材架被連接至接合線且被封裝樹脂封裝的一部分，其中四層鍍層包含生成自鎳或鎳合金的第一鍍層、生成自鈀或鈀合金的第二鍍層、生成自銀或銀合金的的第三鍍層、以及生成自黃金或黃金合金的第四鍍層，其係依此順序層疊在基材架之部分；以及三層鍍層施作於基材架自封裝樹脂暴露出的暴露區域，其中三層鍍層包含第一鍍層、第二鍍層、以及第四鍍層，其係依此順序層疊在基材架之暴露區域。
根據實施例之一的導線架，包含第一至第四鍍層之四層鍍層係形成在基材架上被連接至接合線且由封裝樹脂封裝的部分。基材架表面層的硬度被由銀形成的第三鍍層以及由黃金形成的第四鍍層減少。此抑制了進行接合時接合線的滑移。因此，接合線的連接可靠度被增進。
本發明的其他目的及優點將由以下內容說明，在敘述中明顯可見，或可經由本發明的實施例習得。本發明的目的及優點將藉由特別指出申請中的申請專利範圍的元件及組合的手段被了解及獲得。
要了解的是前述一般性描述以及以下的詳細描述係示範及解釋用，而非作為本發明的限縮。
實施例將參考對應之圖式描述如下。對應的圖式概要地繪示出結構而未示出真實比例。此外，鍍層在剖面圖中並未示出影線以助於理解每一部的斷面結構。
實施例之一將參考圖1至10描述如下。
導線架結構
圖1示出一導線架1，其基本上形成自被用作奎德平封裝(Quad Flat Package,QFP)的基材架2。基材架2(基礎材料)係形成自，例如，銅、銅合金、鎳-鐵雙合金、或鎳-鐵基質多組成合金。基材架2係得自，例如，壓出或蝕刻一金屬板。
基材架2包含半導體元件21(參圖2)鑲嵌於上的晶粒銲墊3。由上觀之時晶粒銲墊3形成為四角形。晶粒銲墊3由連接至軌件4的支撐條5所支撐，其中軌件4形成於基材架2之邊角並沿基材架2長軸方向延伸。複數個連接至屏障條6的內導線7被安排在晶粒銲墊3的周圍。屏障條6被連接至複數個外導線8的基部端，且外導線8的末端被連接至軌件4或內框9。每一內框9呈直角地延伸至並連接至軌件4。晶粒銲墊3、支撐條5、屏障條6、內導線7、以及外導線8被形成於基材架2的開口10所定義。在圖1中，以虛線標示的部分係由封裝樹脂23(參圖2)封裝的樹脂封裝區域。晶粒銲墊3及內導線7被封裝樹脂23封裝，外導線8被封裝樹脂23暴露。
如圖2所示，晶粒銲墊3位於比內導線7低的位置。與內導線7形成為一體的外導線8位於比晶粒銲墊3低的位置。第一彎折部8a以及第二彎折部8b可形成於每一外導線8，其中第一彎折部8a接近內導線7。外導線8由第二彎折部8b至末端的底部係作為銲接及鑲嵌至例如印刷線路板的鑲嵌基材的 鑲嵌表面。
施作於晶粒銲墊3、內導線7、以及外導線8的層狀結構現敘述如下。
如圖2所示，被封裝樹脂23封裝的四層鍍層15A被施作於晶粒銲墊3以及內導線7。四層鍍層15A包含用作基礎的第一鍍層11、第二鍍層12、第三鍍層13、以及第四鍍層14，其係依此順序層疊。在此實施例中，第一鍍層11係鎳鍍層，第二鍍層係鈀鍍層，第三鍍層係銀鍍層，第四鍍層係黃金鍍層。四層鍍層15A覆蓋晶粒銲墊3以及內導線7的上、下以及側表面。三層鍍層15B被施作於由封裝樹脂23暴露的外導線8。三層鍍層15B包含作為基礎的第一鍍層11、第二鍍層12以及第四鍍層14，其係依此順序層疊。三層鍍層15B覆蓋外導線8之上、下、以及側表面。
依此，包含第三鍍層13(銀鍍層)的四層鍍層15A被施作於基材架2覆蓋有封裝樹脂23的部分而不含第三鍍層13的三層鍍層15B則被施作於基材架2由封裝樹脂23暴露的部分。第一鍍層11至第四鍍層14可經由例如電鍍的方式形成。
位於最底用作基礎的第一鍍層11較佳係由一材料生成，其且/或具有將抵擋基材架2的腐蝕、與由鈀形成的第二鍍層12的黏著性、以及受彎折的被鍍部位對於裂開的阻力等納入考慮的厚度。例如供第一鍍層11的材料，鎳、鎳合金或類似者可以被使用。由特性及製造成本的角度觀之，第一鍍層11的厚度較佳介於0.1μm至3μm間(亦即大於或等於0.1μm且小於或等於3μm)，更佳介於0.2μm至2μm間。
由基礎材料起的第二層之第二鍍層12較佳係由一材料生成，其且/或具有阻止第一鍍層11因為組裝時產生的熱導致的擴散及氧化的厚度。作為體現這些功能的第二鍍層12的材料，鈀或鈀合金可以被使用。當由製造成本的觀點減小厚度時第二鍍層12的厚度較佳介於0.005μm至0.2μm間以阻止第一鍍層11的擴散及氧化。
由基礎材料起的第三層之第三鍍層13較佳係由一材料生成，其且/或具有增加對接合線22連接可靠性的厚度。第三鍍層13的材料較佳係為相對抗氧化且具低硬度的金屬。作為第三鍍層13的材料，例如，銀或銀合金可以被使用。為了穩定增加對接合線22連接可靠性，第三鍍層13的厚度較佳介於0.01μm至3.5μm間，更佳介於0.05μm至3.5μm間。
由基礎材料起的第四層或者為最高層之第四鍍層14較佳係由一材料生成，其且/或具有增進對接合線22連接可靠性的厚度。第四鍍層14的材料較佳係為相對抗氧化且具低硬度的金屬。作為第四鍍層14的材料，例如，黃金或黃金合金可以被使用。當由製造成本的觀點減小厚度時，為了增加對接合線22連接可靠性，第四鍍層14的厚度較佳介於0.001μm至0.1μm間，更佳介於0.003μm至0.01μm間。
半導體裝置結構
如圖2所示，樹脂封裝型半導體裝置20具有導線架1產出之QFP結構。在半導體裝置20中，半導體元件21藉由黏膠21A(例如銀膠)黏附於導線架1的晶粒銲墊3上，特別是形成 於晶粒銲墊3表面的四層鍍層15A。半導體元件21包含由接合線22連接至內導線7的電極21B。具體而言，半導體元件21的電極21B經由接合線22以及第一鍍層11至第四鍍層14(鍍層15A)耦接至內導線7。半導體元件21、接合線22、晶粒銲墊3、以及內導線7被封裝樹脂23覆蓋及封裝。在半道體裝置20，外導線8被封裝樹脂23暴露作為外部連接端。
半導體元件21係為，例如，積體電路晶片、大尺寸積分(large scale integration,LSI)晶片或相類似者。在說明範例中，僅示出一個半導體元件。然而，必要時，二個或更多的半導體元件可以被使用。此外，任何主動或被動元件可被用於替代或組合半導體元件。接合線22可能為，例如，銅線、黃金線、鋁線、或相類似者。封裝樹脂23的材料可能為，例如，環氧樹脂、聚亞醯胺樹脂、酚樹脂、或壓克力樹脂。
連接可靠性評估
銅線相較於內部導線7之於四層鍍層15A被施作者的連接可靠性(線接合性質)的評估結果今敘述如下。
首先，線連接至內部導線7的銅線的張力被量測，其中第一鍍層11的厚度為1.0μm、第二鍍層12的厚度為0.03μm、第三鍍層13的厚度為0.1μm、以及第四鍍層14的厚度為為0.008μm(範例1)。在相同條件下施作有三層鍍層16(參圖15)的習知導線架50的銅線的張力亦被量測。在導線架50，鎳鍍層11A、鈀鍍層12A、以及黃金鍍層14A之厚度分別為1.0μm、0.03μm、以及0.08μm(比較例1)。進一步，在相同條件下直 接施作5μm的銀鍍層於由銅或銅合金形成的基材架的導線架之銅線的張力亦被量測(比較例2)。結果如圖3所示。
張力係為在對於內部導線已進行針腳接合的導線架之銅線針腳接合部進行張力測試期間當銅線分層或斷裂時表示負載的值。較大的負載結果在較高的張力，其表示對於銅線較高的連接可靠性。
如圖3的結果明顯所示，有四層鍍層15A的範例1得到的張力近乎三至四倍大於有三層鍍層16的比較例1。其被理解為原因在於第三鍍層13(銀鍍層)的添加減少了內導線7之線接合表面層(第四鍍層14)的硬度。細部而言，首先，其被理解到，因為銅線比黃進線硬且滑移發生於銅線接合時的事實，當使用銅線取代黃金線，線接合性質惡化。就此而言，在有四層鍍層15A的範例1，其可被理解到第三鍍層13(銀鍍層)的存在減少了表面層的硬度，從而導致在導線架邊可塑的變形。此抑制了銅線的滑移並容許了好的連接。此顯著地增加張力相較於比較例1。在範例1，第三鍍層13(銀鍍層)的厚度小於比較例2中銀鍍層的厚度。然而，範例1獲得了約與比較例2相同的張力且從而具有實質上足夠的張力。
當形成自低硬度的金屬的第四鍍層14或第三鍍層13的厚度增加，內導線7之表面層(第四鍍層14)的硬度減少。如此，線接合性質可以藉由增加第四鍍層14與第三鍍層13的厚度被增進。圖4及圖5顯示支持此觀察的評估結果的例子。
圖4顯示形成於內導線7上的四層鍍層15A中的第三鍍層13的厚度與維克氏硬度(Vickers hardness)的關係。更具體 而言，維克氏硬度被獲得在當第三鍍層(銀鍍層)在內導線7的厚度變化為0μm、0.05μm、0.1μm、0.5μm、以及1.0μm，而第一鍍層11的厚度設為0.8μm、第二鍍層12的厚度設為0.02μm、以及第四鍍層14的厚度設為0.006μm。對於維克氏硬度的量測，50gf被使用。較低的維克氏硬度值表示較低的硬度。如圖4的結果明顯所示，維克氏硬度減小，亦即，內導線7的硬度減小當第三鍍層13的厚度增加。
圖5顯示了形成在內導線上的四層鍍層15A中的第三鍍層13的厚度與表示張力測試後的針腳分離的缺陷率之間的關係。如圖5的結果明顯所示，第三鍍層13厚度的增加減小了表示針腳分離的缺陷率。具體而言，當第三鍍層13的厚度大於或等於0.05μm，表示針腳分離的缺陷率為零。由這些結果明顯可知，第三鍍層13厚度的增加減少了內導線7的表面層的硬度且增進了線接合性質。
然而，第三鍍層13厚度的增加提高了製造成本。就此而言，進行了研究以找出第三鍍層13的厚度的上限值。研究結果如圖6所示。圖6顯示當直接施作於形成自銅或銅合金的基材架的銀鍍層的厚度變化為2.0μm、3.5μm、6.0μm、以及1.2μm的張力。如圖6的結果明顯所示，當銀鍍層的厚度大於或等於2.0μm，每一例可獲得實質上足夠的的張力。然而，當銀鍍層的厚度超過3.5μm，張力的變異隨著銀鍍層厚度哦增加而增大。據此，由圖6的結果，其係明顯的高張力可以穩定地被獲得當銀鍍層的厚度被設為3.5μm。圖6的結果係被獲得在當銀鍍層直接被施作在基材架。然而，在四層鍍層中的 第三鍍層13(銀鍍層)大幅助益於增加張力。因此，其可被理解為當變異在四層鍍層中的第三鍍層13的厚度時，具有如同圖6的結果所示相同的趨勢的張力可以被獲得。換言之，對於施作有四層鍍層15A的導線架7，藉由設定第三鍍層13的厚度為3.5μm，高張力可能被穩定地獲得。此得到高連接可靠性。
由前述描述中明顯可知，第三鍍層13的厚度較佳設於0.05μm至3.5μm間。
可靠性評估
可靠性測試(濕氣吸附回流測試)被進行於具有包含銀鍍層且被施作於封裝樹脂內的基材架的四層鍍層(參見圖2)的半導體裝置以評估半導體裝置的可靠性。作為比較例，相同的評估被進行於具有不包含銀鍍層且被施作於封裝樹脂內的基材架的三層鍍層的半導體裝置(參見圖15)。除了銀鍍層是否存在外，進行於此二半導體裝置的可靠性測試係在相同條件下進行。圖7及圖8顯示了從超音波測試儀器，例如掃描聲學顯像儀(scanning acoustic tomography,SAT)獲得的結果，其檢查了在可靠性測試前後半導體裝置中的封裝樹脂以及導線架間的去層疊(delamination)。
可靠性測試係以下列條件進行。
濕氣吸附條件：JEDEC MSL 2a(60℃/60% RH x 120小時)
回流條件：260℃ x 3次
如圖7(a)及圖8(a)所示，在此進行了可靠性測試的二半 導體裝置中，被確認在可靠性測試前封裝樹脂以及導線架間未發生去層疊。如圖8(b)所示，然而，在具有不包含銀鍍層的三層鍍層的半導體裝置中，在封裝樹脂(指白線圈出部分)，每一晶粒銲墊的封裝樹脂以及導線架間在可靠性測試後被檢出去層疊。相對的，如圖7(b)所示，在具有包含銀鍍層的四層鍍層的半導體裝置中，在封裝樹脂，每一晶粒銲墊的封裝樹脂以及導線架間在可靠性測試被執行後未被檢出去層疊。由這些結果，明顯可知圖2所示半導體裝置20的可靠性可藉由包含第三鍍層13(銀鍍層)的四層鍍層15A被施作於基材架2被封裝樹脂23封裝的區域而被提升。
銀鍍層不被形成於外導線的原因
如圖16所示，在四層鍍層15A被施作於基材架2的結構中，四層鍍層15A亦可以如同於內導線7的方式被施作於外導線8。然而，在此實施例中，不包含第三鍍層13(銀鍍層)的三層鍍層15B被有意地施作在由封裝樹脂23暴露的外導線8。此結構的原因將被描述。即，在第三鍍層13形成於由封裝樹脂23暴露外導線8時會發生下列所述問題。
第一問題
導線架被形成為套裝並焊接到基材，當基材側邊銲料係無鉛之錫-銀-銅銲料或相似者時可能發生下列問題。細部而言，Ag3Sn金屬化物係相對穩定的合金且已知為具有絕佳機械強度的無鉛銲料。然而，當銀在錫中的濃度超過4%時其脆裂強度變得異常大，從而導致例如基材的地去疊層(land delamination)現象的傾向於發生。進一步，當銀在錫中的濃度超過5%，會生成可能造成碎裂的收縮凹處。當包含第三鍍層13(銀鍍層)的四層鍍層15A形成在如圖16所示之導線架1D之外導線8(鑲嵌表面)時，大量的銀存在於被焊接部分。此將增加銀的濃度，且地去疊層及碎裂易發生。
第二問題
銀一般已知為易硫化的金屬。當包含銀鍍層的四層鍍層15A形成在外導線8上時，例如，銀在組裝期間在導線架1D的表面層被熱擴散，且銀及黃金彼此共存或以合金形式存在於表面層。於是，導線架1D(特別是每一外導線)係容易被硫化。當外導線8被硫化，外導線8的可濕性與銲料惡化。此可由如圖7及圖10所是的實驗結果確認。實驗條件及結果描述如下。
首先，具有施作於外導線8(參見圖2)的三層鍍層15B的導線架1以及具有施作於外導線8(參見圖16)的四層鍍層15A的導線架1D被準備。導線架1及1D在適於組裝的條件下被加熱，且進行氣體測試。
加熱條件：溫度由室溫被持續調升30分鐘至175℃。而後，在大氣中於175℃加熱60分鐘，且進一步在熱盤上於200℃加熱2分鐘。
氣體測試：100ml的6%硫酸溶液被置入乾燥器，且導線架隨後被留置在由此溶液生成的SO2氣體中60分鐘。其後，100ml的2%硫氫化胺溶液被置入乾燥器，且導線架隨後被留置在由此溶液生成的H2S氣體中15分鐘。
以歐傑電子能譜儀(Auger electron spectroscopy,AES)表面分析對存在於經過氣體測試的導線架的外導線之表面的單元進行定量及定性分析。結果顯示在圖9。如這些結果明顯所示，在具有銀鍍層在外導線上之導線架1D，在外導線8表面的硫的量近乎3倍高於在不具有銀鍍層在外導線上之導線架1。據此，其係明顯的銀鍍層的存在導致外導線傾向於被硫化。
進一步，以變面試驗(meniscograph test)量測經過氣體測試的導線架的零跨時間(zero cross time)。此量測零跨時間的測試(銲料可濕性的評估)係以下列條件進行。
銲料浴的種類：64%錫-鉛共熔銲料
助熔劑種類：非主動式松香基底助熔劑
浸潤速度：2mm/秒
浸潤深度：0.5mm
浸潤時間：10秒
圖10顯示了變面試驗的結果。較短的零跨時間表示銲料可濕性被增進。
由圖10所示的結果，其係明顯的，包含銀鍍層在外導線上的導線架1D(硫化的導線架)相較於不包含銀鍍層在外導線上的導線架1具有較長的零跨時間。進一步而言，相較於導線架1，導線架1D的銲料可濕性較差。
由上述實驗結果可明顯得知，當銀鍍層存在於外導線，外導線傾向被硫化，且銲料可濕性惡化。
因此，在此實施例中的導線架1，如圖2所示，第三鍍層 13(銀鍍層)不被形成於外導線8。相反的，三層鍍層15B被形成在外導線8上。此可避免第一及第二問題發生。
此實施例具有的優點敘述如下。
(1)包含第一鍍層11至第四鍍層14的四層鍍層15A生成在基材架2(內導線7)於線接合部分。內導線7的表面層的硬度被生成自銀的第三鍍層13以及生成自黃金的第四鍍層14減少。此抑制了接合線(銅線)的在進行接合時的滑移。於是，接合線連接可靠性被增進。據此，即使銅線被用於線接合，銅線具有良好的線接合性質。
(2)包含第一鍍層11至第四鍍層14的四層鍍層15A全部生成在基材架2被封裝樹脂23封裝的區域(晶粒銲墊3及內導線7的上、下、以及側表面)。此抑制了導線架1及封裝樹脂23的去層疊且增進了半導體裝置20的可靠性。
(3)不包含第三鍍層13的三層鍍層15B生成在基材架2由封裝樹脂23暴露的區域(即外導線8)。此避免了當銀鍍層存在於外導線8上時可能發生的問題，例如地去層疊及脆裂的發生以及因硫化導致的銲料可濕性惡化。
相較於習知技術應當明顯的，本發明可實現於其他特定的形式而不跳脫本發明的領域。特別應該理解到此發明可以下列形式體現。
如圖11所示之半導體裝置20A的導線架1A，晶粒銲墊3可藉由每一接合線22(係銅線)耦接至半導體元件21的電極21B。具體而言，接合線22可連接半導體元件21的電極21B 至形成在晶粒銲墊3上的四層鍍層15A。
在上述實施例中，四層鍍層15A全部形成在被封裝樹脂23封裝的晶粒銲墊3及內導線7上。然而，本發明不限於以此設置。例如，如圖12所示之導線架1B以及半導體裝置20B，包含第三鍍層13(銀鍍層)的四層鍍層15A，可被施作於被封裝樹脂23封裝且被連接至接合線22的唯一部份(接合部分)。在此例中，三層鍍層15B被施作在被封裝樹脂23封裝之基材架2(晶粒銲墊3及內導線7)在接合部分以外的區域。
在上述實施例中，半導體裝置20包含供QFP的導線架1且形成QFP結構。然而，本發明不限於以此設置。例如，如圖13所示，本發明可實施於包含供覆晶(Led On Chip,LOC)的導線架1C的半導體裝置20C並且形成LOC封裝結構。在半導體裝置20C，黏接層25A被黏著於內導線7的下表面，半導體元件25被黏附在黏接層25A以使半導體元件25由導線架1C(基材架2A)支撐。進一步而言，半導體元件25的電極25B經由接合線22被耦接至內導線7。內導線7、被內導線7支撐的半導體元件25、以及接合線22被封裝樹脂23封裝。導線架1C的基材架2A包含內導線7以及外導線8但不包含晶粒銲墊。
在用於具有如此結構的半導體裝置20C的導線架1C，四層鍍層15A至少被形成在被封裝樹脂23封裝之基材架2A之接合部分，且三層鍍層15B被形成在基材架2A由封裝樹脂23暴露的部分(即外導線8)。此結構亦獲得前述實施例的優點(1)。四層鍍層15A亦可被形成在基材架2A被封裝材料23封裝的全 部區域(即內導線7)上。
如圖14所示，例如，本發明可實施在半導體裝置40包含供用於奎德平無鉛封裝(Quad Flat Non-leaded Package,QFN)之奎德平無鉛的導線架30並形成QFN封裝結構。在導線架30，開口30X被安排在預定的位置(兩個位置在示例中)。導線架30的基材架31包含晶粒銲墊32以及複數個線33被安排在晶粒銲墊32周圍。開口30X定義出晶粒銲墊32以及線33。半導體裝置40包含導線架30、鑲嵌於晶粒銲墊32上的半導體元件41、耦接半導體元件41的電極41B至線33的接合線42、以及覆蓋半導體元件41、接合線42、以及部分基材架31的封裝樹脂43。預定量的封裝樹脂43由導線架30之一側(在此示例中，由上側)被填充入開口30X以具有小於導線架30厚度的厚度。由封裝樹脂43暴露的線33係作為銲接至例如印刷線路板的鑲嵌基材的鑲嵌表面。
在用於具有如此結構的半導體裝置40的導線架30，四層鍍層15A被形成在被封裝樹脂43封裝之晶粒銲墊32及線33的區域，且三層鍍層15B被形成在晶粒銲墊32及線33由封裝樹脂43暴露的區域。此結構亦獲得與前述實施例相同的優點。在被封裝樹脂43封裝的區域，當四層鍍層15A至少被形成在接合線42被線接合之部分，此實施例的優點(1)被獲得。
本發明亦可被實施於包含不同封裝結構的樹脂封裝型半導體裝置，例如球柵陣列(Ball Grid Array,BGA)、地柵陣列(Land Grid Array,LGA)、及相類似者，或者導線架用於此類半導體裝置者。
雖然前述的描述及圖式已揭示本發明之較佳實施例，必須瞭解到各種增添、許多修改和取代可能使用於本發明較佳實施例，而不會脫離如所附申請專利範圍所界定的本發明原理之精神及範圍。熟悉本發明所屬技術領域之一般技藝者將可體會，本發明可使用於許多形式、結構、佈置、比例、材料、元件和組件的修改。因此，本文於此所揭示的實施例應被視為用以說明本發明，而非用以限制本發明。本發明的範圍應由後附申請專利範圍所界定，並涵蓋其合法均等物，並不限於先前的描述。
1‧‧‧導線架
1A‧‧‧導線架
1B‧‧‧導線架
1C‧‧‧導線架
1D‧‧‧導線架
2‧‧‧基材架
2A‧‧‧基材架
3‧‧‧晶粒銲墊
4‧‧‧軌件
5‧‧‧支撐條
6‧‧‧屏障條
7‧‧‧內導線
8‧‧‧外導線
8a‧‧‧第一彎折部
8b‧‧‧第二彎折部
9‧‧‧內框
10‧‧‧開口
11‧‧‧第一鍍層
11A‧‧‧鎳鍍層
12‧‧‧第二鍍層
12A‧‧‧鈀鍍層
13‧‧‧第三鍍層
14‧‧‧第四鍍層
14A‧‧‧黃金鍍層
15A‧‧‧四層鍍層
15B‧‧‧三層鍍層
16‧‧‧三層鍍層
20‧‧‧半導體裝置
20A‧‧‧半導體裝置
20B‧‧‧半導體裝置
20C‧‧‧半導體裝置
21‧‧‧半導體元件
21A‧‧‧黏膠
21B‧‧‧電極
22‧‧‧接合線
23‧‧‧封裝樹脂
25‧‧‧半導體元件
25A‧‧‧黏接層
25B‧‧‧電極
30‧‧‧導線架
30X‧‧‧開口
31‧‧‧基材架
32‧‧‧晶粒銲墊
33‧‧‧線
40‧‧‧半導體裝置
41‧‧‧半導體元件
41B‧‧‧電極
42‧‧‧接合線
43‧‧‧封裝樹脂
50‧‧‧導線架
51‧‧‧基礎材料
本發明，連同其目的及優點，可能藉由參考下列目前的較佳實施例的描述併同其對應的圖式被較佳地了解，其中：圖1為導線架實施例平面示意圖；圖2為半導體裝置之實施例剖面示意圖；圖3為連接可靠性評估結果的曲線示意圖；圖4為銀鍍層厚度與維克氏硬度的關係的曲線示意圖；圖5為連接可靠性評估結果的曲線示意圖；圖6為連接可靠性評估結果的曲線示意圖；圖7(a)為半導體裝置在可靠性測試前的示意圖；圖7(b)為半導體裝置在可靠性測試後的示意圖；圖8(a)為半導體裝置在可靠性測試前的示意圖；圖8(b)為半導體裝置在可靠性測試後的示意圖；圖9為AES定性及定量分析表；圖10為銲料可濕性評估結果的曲線示意圖； 圖11為修改過的半導體裝置之剖面示意圖；圖12為修改過的半導體裝置之剖面示意圖；圖13為修改過的半導體裝置之剖面示意圖；圖14為修改過的半導體裝置之剖面示意圖；圖15為統的半導體裝置之剖面示意圖；以及圖16為比較例之導線架之剖面示意圖。
1‧‧‧導線架
2‧‧‧基材架
3‧‧‧晶粒銲墊
7‧‧‧內導線
8‧‧‧外導線
8a‧‧‧第一彎折部
8b‧‧‧第二彎折部
10‧‧‧開口
11‧‧‧第一鍍層
12‧‧‧第二鍍層
13‧‧‧第三鍍層
14‧‧‧第四鍍層
15A‧‧‧四層鍍層
15B‧‧‧三層鍍層
20‧‧‧半導體裝置
21‧‧‧半導體元件
21A‧‧‧黏膠
21B‧‧‧電極
22‧‧‧接合線
23‧‧‧封裝樹脂

Claims (9)

  1. 一種供一樹脂封裝型半導體裝置用之導線架，其中該半導體裝置包含一半導體元件具有一電極、一接合線連接到該半導體元件之該電極、以及一封裝樹脂覆蓋並封裝該半導體元件與該接合線，該導線架包含：一包含複數個導線之基材架；一四層鍍層施作於該基材架被連接至該接合線且被該封裝樹脂封裝的一部分，其中該四層鍍層包含一生成自鎳或鎳合金的第一鍍層、一生成自鈀或鈀合金的第二鍍層、一生成自銀或銀合金的的第三鍍層、以及一生成自黃金或黃金合金的第四鍍層，其係依此順序層疊在該基材架之該部分；以及一三層鍍層施作於該基材架自該封裝樹脂暴露出的一暴露區域，其中該三層鍍層包含該第一鍍層、該第二鍍層、以及該第四鍍層，其係依此順序層疊在該基材架之該暴露區域。
  2. 如請求項1所述之導線架，其中該基材架包含一該半導體元件鑲嵌於上的晶粒銲墊。
  3. 如請求項1所述之導線架，其中該四層鍍層係全部施作於該基材架被該封裝樹脂封裝的一封裝區域。
  4. 如請求項1所述之導線架，其中該第三鍍層之厚度係介於0.05μm至3.5μm間。
  5. 如請求項1所述之導線架，其中：該複數個導線每一均包含一外端以及一內端；該三層鍍層施作於該導線之該外端；以及 該四層鍍層施作於該導線之該內端。
  6. 一種半導體裝置，包含：如請求項1所述之導線架；該半導體元件；該接合線，耦接該半導體元件之該電極以及該四層鍍層；以及該封裝樹脂，覆蓋並封裝該半導體元件、該接合線、以及部分之該導線。
  7. 如請求項1所述之導線架，其中該四層鍍層的該第三鍍層及該第四鍍層減少該複數個導線至少其中之一的該四層鍍層的一表面層的一硬度從而導致在該複數個導線至少其中之一的該表面層的一可塑的變形。
  8. 如請求項7所述之導線架，其中該可塑的變形抑制了一銅線被接合到該複數個導線的該表面層時的滑移。
  9. 如請求項8所述之導線架，其中該四層鍍層增加該銅線連接到該複數個導線的該表面層的可靠度。
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