TWI500085B - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
TWI500085B
TWI500085B TW102121548A TW102121548A TWI500085B TW I500085 B TWI500085 B TW I500085B TW 102121548 A TW102121548 A TW 102121548A TW 102121548 A TW102121548 A TW 102121548A TW I500085 B TWI500085 B TW I500085B
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TW
Taiwan
Prior art keywords
control gate
length
semiconductor device
buckling
height
Prior art date
Application number
TW102121548A
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English (en)
Chinese (zh)
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TW201426871A (zh
Inventor
小藤直行
根岸伸幸
石村裕昭
Original Assignee
日立全球先端科技股份有限公司
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Application filed by 日立全球先端科技股份有限公司 filed Critical 日立全球先端科技股份有限公司
Publication of TW201426871A publication Critical patent/TW201426871A/zh
Application granted granted Critical
Publication of TWI500085B publication Critical patent/TWI500085B/zh

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/69IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693Vertical IGFETs having charge trapping gate insulators
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/73Etching of wafers, substrates or parts of devices using masks for insulating materials

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
TW102121548A 2012-12-25 2013-06-18 Manufacturing method of semiconductor device TWI500085B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012280480A JP6173684B2 (ja) 2012-12-25 2012-12-25 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201426871A TW201426871A (zh) 2014-07-01
TWI500085B true TWI500085B (zh) 2015-09-11

Family

ID=50973676

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102121548A TWI500085B (zh) 2012-12-25 2013-06-18 Manufacturing method of semiconductor device

Country Status (5)

Country Link
US (1) US9099349B2 (2)
JP (1) JP6173684B2 (2)
KR (1) KR101513596B1 (2)
CN (1) CN103904033B (2)
TW (1) TWI500085B (2)

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Also Published As

Publication number Publication date
KR101513596B1 (ko) 2015-04-20
US9099349B2 (en) 2015-08-04
CN103904033B (zh) 2017-03-01
TW201426871A (zh) 2014-07-01
JP6173684B2 (ja) 2017-08-02
CN103904033A (zh) 2014-07-02
JP2014127475A (ja) 2014-07-07
US20140175534A1 (en) 2014-06-26
KR20140082914A (ko) 2014-07-03

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