TWI490957B - 用於形成由直通矽晶穿孔連接至背面互聯結構的被動電路元件之半導體元件與方法 - Google Patents

用於形成由直通矽晶穿孔連接至背面互聯結構的被動電路元件之半導體元件與方法 Download PDF

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TWI490957B
TWI490957B TW097137851A TW97137851A TWI490957B TW I490957 B TWI490957 B TW I490957B TW 097137851 A TW097137851 A TW 097137851A TW 97137851 A TW97137851 A TW 97137851A TW I490957 B TWI490957 B TW I490957B
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substrate
layer
forming
conductor
passive component
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TW200924092A (en
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Yaojian Lin
Haijing Cao
Qing Zhang
Kang Chen
Jianmin Fang
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Stats Chippac Ltd
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Description

用於形成由直通矽晶穿孔連接至背面互聯結構的被動電路元件之半導體元件與方法
本發明概略有關於半導體元件，並且特別是關於一種具經互聯至背面焊燒球點之整合式被動電路構件的半導體元件。
可在娛樂、通訊、網路、電腦及家用市場領域中的眾多產品裡尋獲半導體元件的影蹤。半導體裝置亦出現在軍用、航空、汽車、工業控制器及辦公室設備裡。半導體裝置可執行對於這些應用項目所必要的各式電氣功能。
半導體元件的製造過程牽涉到構成具有複數個晶粒的晶圓。各個半導體晶粒含有數百或數千個電晶體以及其他執行各種電氣功能的主動和被動元件。對於一給定晶圓而言，來自該晶圓的各個晶粒通常會執行相同的電氣功能。前端製造一般是指在該晶圓上構成半導體元件。所完成的晶圓具有一主動側面，而其中含有該等電晶體及其他主動和被動器件。而後端製造則是指將該所完成晶圓切割或單化成個別晶粒，然後再將晶粒加以封裝俾提供結構支撐與環境隔離。
半導體製造的其一目標即為按較低成本以生產出適合於更快速、可靠、更微小及更高密度之積體電路(IC)的封裝。覆晶封裝或晶圓層級晶片比例封裝(WLCSP)為理想地適用於要求高速、高密度及更多腳針數目的IC。覆晶式封裝 處理牽涉到將該晶粒的主動側面向下架置而朝於一晶片載體基板或印刷電路板(PCB)。於該晶粒上之主動元件與該載體基板上之導體跡線間的電氣及機械互聯是經由一焊燒球點結構所達成，此結構含有大量的導體焊燒球點或焊球。該等焊燒球點是藉由一重流製程所構成，此製程係施用在經沉積於設置在該半導體基板上之接觸點板上的焊燒材料。然後將該等焊燒球點焊燒至該載體基板。該覆晶半導體封裝提供一自該晶粒上的主動元件至該載體基板的微短導電路徑，藉此縮短信號傳播，降低電容性並且達到整體較佳的電路效能。
在許多應用項目裡，會希望在該半導體晶圓上構成包含電感器、電阻器及電容器在內的被動電路構件。電成器及電容器可讓該IC能夠執行反應性電路功能而無須利用外部的電路器件。該等被動電路構件，尤其是電感器，會在該晶粒上佔據顯著面積。電容器通常是在該基板的表面上按如線圈或捲繞金屬層所構成，然如此會耗佔龐大面積。該晶粒亦必須容納像是焊燒球點的互聯結構，而這也會佔用顯著的空間。當考量到互聯要求時。對於較小晶粒而具備高特性密度的需要亦不易達成。
故存在一種需要以將被動電路構件及互聯結構整合於更小及更密集半導體晶粒的需求。
在一具體實施例裡，本發明係一種製作一半導體元件 的方法，其中包含如下步驟，即提供一基板，此者具有複數個經構成於其上的主動元件；在該基板上構成一類比電路；在該基板內構成一直通基板穿孔(TSV)；在該TSV內沉積導體材料而電氣接觸於該類比電路；在該基板背面上構成一底層球點金屬化(UBM)層而電氣接觸於該TSV內的導體材料；在該UBM層上沉積焊燒材料；以及重流該焊燒材料以構成一焊燒球點。該類比電路係經由該TSV而電氣連接至位於該基板背面上的焊燒球點。
在另一具體實施例裡，本發明係一種製作一半導體元件的方法，其中包含如下步驟，即提供一基板；在該基板上構成一被動元件；以及構成一通透該基板的穿孔。含有該導體材料的穿孔係電氣接觸於該被動元件。該方法進一步包含如下步驟，即在該基板之背面上構成一互聯結構而電氣接觸於該穿孔內的導體材料。該被動元件經由穿孔而電氣連接至位於該基板背面上的互聯結構。
在另一具體實施例裡，本發明係一種製作一半導體元件的方法，其中包含如下步驟，即提供一基板；在該基板上構成一被動元件；構成一通透該基板的穿孔；在該穿孔中沉積導體材料；以及在該基板之背面上構成一互聯結構而電氣接觸於該穿孔內的導體材料。
在另一具體實施例裡，本發明係一種半導體元件，其中包含一基板；一被動元件，此者係經構成於該基板上；以及一穿孔，此者係通透該基板所構成。該穿孔含有導體材料而電氣接觸於該被動元件。一互聯結構係經構成於該 基板的背面上而電氣接觸於該穿孔。該被動元件經由該穿孔而電氣連接至位於該基板背面上的互聯結構。
後文中將參照圖式而按一或更多具體實施例以說明本發明，其中類似參考編號代表相同或相仿構件。本發明雖係按照為達本發明之目標的最佳模式所敘述，然熟請本項技藝之人士將能瞭解所欲者係為涵蓋能夠納入在依後載申請專利範圍及其等可獲後述揭示與圖示所支持之等同項目而定義的本發明精神與範圍以內之替代、修改和等同項目。
半導體元件的製造過程牽涉到構成一具有複數個晶粒的晶圓。各晶粒含有數百或數千個電晶體以及其他執行各種電氣功能的主動和被動元件。對於一給定晶圓而言，來自該晶圓的各個晶粒通常會執行相同的電氣功能。前端製造一般是指在該晶圓上構成半導體元件。所完成的晶圓具有一主動側面，而其中含有該等電晶體及其他主動和被動器件。而後端製造則是指將該所完成晶圓切割或單化成個別晶粒，然後再將晶粒加以封裝俾提供結構支撐及/或環境隔離。
一半導體晶圓通常含有一主動表面，其上設置有多個半導體元件；以及一背面表面，而經構成有即如矽晶的體型半導體材料。該主動側面表面含有複數個半導體晶粒。該主動表面是由各種半導體製程所構成，包含疊層化、圖案化、掺質及熱處理。在疊層化製程中，藉由涉及到熱氧 化、氮化、化學氣相沉積、汽化及濺鍍處理的技術，令半導體材料在該基板上成長或沉積。微影術牽涉到將該表面的多個區域加以遮蔽並蝕刻掉不欲材料，藉此構成特定結構。掺質處理可藉由熱擴散或離子佈植作業以注入掺質材料的濃縮物。
覆晶半導體封裝及晶圓層級封裝(WLP)常用於要求高速、高密度及眾多腳針數目的積體電路(IC)。覆晶式半導體元件10牽涉到將該晶粒14的主動區域12向下架置而朝於一晶片載體基板或印刷電路板(PCB)16，即如圖1所示者。根據該晶粒之電氣設計而定，該主動區域12可含有主動及被動元件、導體層和介電層。可藉由經構成於該主動區域12內並經電氣互聯之一或更多被動元件的組合以產生類比電路。例如，一類比電路可含有一或更多經構成於該主動區域12內的電感器、電容器及電阻器。該電氣及機械互聯是透過一焊燒球點結構20所達成，此結構含有大量的個別導體焊燒球點或焊球22。該等焊燒球點係經構成於經設置在該主動區域12上的球點點板或互聯處所24之上。該等球點點板24藉由該主動區域12內的導體跡線而連接至該等主動電路。該等焊燒球點22係藉由一焊燒重流製程以按電氣且機械方式連接於該載體基板16上的接觸點板或互聯處所26。覆晶半導體元件可提供一自該晶粒14上之主動元件至該載體基板16之導體跡線的微短導電路徑，藉此縮短信號傳播，降低電容性並達到整體較佳的電路效能。
圖2a說明一半導體晶圓28，此者具有一由矽晶或其他 體型半導體材料所製成的基板30。可利用一深層反應離子蝕刻(DRIE)製程，或是以氫氧化鉀(KOH)之矽晶濕性蝕刻製程，將溝槽或穿孔34及36切入該基板30內。該等溝槽34及36在稍後的階段中將會成為直通基板穿孔(TSV)。藉由化學汽相沉積(CVD)以在該基板30之上設置一絕緣層38。該絕緣層38依循該基板的廓形，並且提供對於該等溝槽34及36的穿孔襯墊。該絕緣層38可為由二氧化矽(SiO2)、氮氧化矽(SiON)、氮化矽(SixNy)、五氧化二鉭(Ta2O5)、氧化鋯(Zr)或是其他具有介電性質的材料所製成。該絕緣層38的厚度範圍為從500埃()至30微米(μm)，而典型數值則約為1000。
在圖2b裡，該絕緣層38上沉積有一導電層40且經圖案化。該導電層40可為由鋁(Al)、鋁合金、銅(Cu)、鎳(Ni)、金(Cu)、銀(Ag)或是其他導電材料所製成。Cu一般用於合併附著層及阻障層。該導電層40可有多個疊層，像是鈦(Ti)/氮化鈦(TiN)/Al/TiN。該導電層40的沉積作業是利用一物理汽相沉積(PVD)、CVD、汽化、電鍍鍍置或無電鍍置製程。該等導電層40可為根據經構成於該基板30上之個別元件的連接性所電氣共用或電氣隔離。該導電層40在穿孔34及36內的圖案可為選擇性。
一電阻層42係經標註為電阻層42a及42b，並經沉積於該絕緣層38且經圖案化，同時連接至該導電層40以構成一電阻器。或者，該電阻層42可經由該鍍置層50及Cu層54而連接以構成一電阻器，參見圖2c。該電阻層42b係 於該導電層40與該絕緣層46間所圖案化以壓制Hillock成長。該電阻層42是由矽化物而經掺入具有一達約100歐姆/平方之薄片電阻的聚矽、氮化鉭(TaN)、鉻化鎳(NiCr)或TiN所製成。該電阻層42的沉積作業可牽涉到PVD或CVD而具有範圍200－5000的厚度。
一絕緣層46係經沉積於該電阻層42b上且經圖案化。該絕緣層46可為絕緣之目的而覆蓋其他的電路範圍。該絕緣層46可為由SiO2、SixNy、SiON、Ta2O5、氧化Zr或其他介電材料所製成。該絕緣層46的沉積作業可牽涉到PVD或CVD。
一鈍化層48係經構成於圖2a－2b中所建立的結構上以供結構支撐及電氣隔離。該鈍化層48可為由SiO2、SixNy、SiON、聚亞醯胺(PI)、苯環丁烯(BCB)、聚苯並噁唑(PBO)或其他絕緣材料所製成。可利用一經遮罩定義之微影術製程來移除一部份的鈍化層48，藉以曝出該等導體層40及絕緣層38和46。
在圖2c裡，一即如Cu鍍置之金屬鍍層50係經沉積且藉厚型光阻52所圖案化。該鍍置層50具有一附著層及種源層。該附著層可為由Ti、TiW、Ta/TaN或Cr所製成。該種源層通常為Cu。一光阻層52係於該Cu層54的鍍置層50之上所圖案化。該Cu層54可按如一敷形塗層而沉積於溝槽34及36上。或者，該Cu層54可為透過一填入製程所構成，這可將Cu沉積至穿孔34及36內。可利用該Cu層54以構成互聯以及電感器分支或傳輸線。該等電感器分 支係透過Cu鍍置而連同於TSV金屬沉積所構成。該等溝槽34及36內之Cu材料可為與在該鈍化層48上的Cu層54及54a所同時構成。或者，該等Cu層的雙鍍處理填入該等溝槽34及36，並在不同時間處構成該Cu層54a。在穿孔34及36內的選擇性導體層40可改善該等穿孔內的金屬步階覆蓋和Cu填入製程。該等Cu層54可為根據經構成於該基板30上之個別元件的連接性而定所電氣共用或電氣隔離。
在圖2d裡，該光阻52係經移除。一部份的鍍置層50則由蝕刻處理所移除。一鈍化層58係鍍附於圖2a－2c的結構上以供結構支撐及電氣隔離。該鈍化層58可為由SiO2、SixNy、SiON、PI、BCB、PBO、環氧樹脂或其他絕緣材料所製成。
在圖2e中，該半導體晶圓28係經背部研磨以暴露出TSV 34及36。從而，導體穿孔34及36穿過該矽晶基板30。一鈍化層60係經沉積於該半導體晶圓28的背面上且經圖案化。該鈍化層60可為由SiO2、SixNy、SiON、PI、BCB、PBO、環氧樹脂或其他絕緣材料所製成。一底層球點金屬化(UBM)62係經沉積且圖案化以電氣接觸於該等TSV 34及36內的Cu層54。該等UBM 62可以用Ti、Ni、NiV、Cu或Cu合金所製造。該等UBM 62可為一多重金屬堆疊，並且具有附著層、阻障層及濕化層。該附著層可為由Ti、Cr、Al、TiW或氮化鈦(TiN)所製成。該阻障層可為由Ni、NiV、CrCu或TiW所製成。而該濕化層可為由Cu、Au或Ag所 製成。該等經曝出的TSV 34及36可用來該等UBM 62之對準。或者，可利用一背面對準(BSA)紅外線(IR)對準以構成該等UBM 62。
一導電焊燒材料係經由一汽化、電鍍鍍置、無電鍍置、焊球滴落或網版印刷製程而沉積於該等UBM 62上。該焊燒材料可為任合金屬合金或導電材料，即如Sn、鉛(Pb)、Ni、Au、Ag、Cu、鉍(Bi)及其合金。該焊燒材料通常為無鉛物，像是Sn96.5Ag3.5。該焊燒材料係藉由將該導體材料加熱至高於其熔點所重流，藉以構成球型的焊球或球點66。在一些應用裡，該等焊燒球點66係經二次重流以改善對該等UBM 62的電氣接觸。該等UBM 62及焊燒球點66代表一種互聯結構。
在圖2f裡，一選擇性的聚合黏膠層70係經塗佈於該鈍化層58上。晶片載體72係藉聚合黏膠層70而接附於該半導體晶圓28。或者，可施用背面研磨貼帶或永久性鑄造複合模而無須載體72。當施用永久性鑄造複合模時，該鈍化層58可為選擇性。可在晶切處理之前，或之後，將該背面研磨貼帶或聚合黏膠並連同該載體72予以移除。或者，該黏膠及載體可保持為永久地接附且成為該晶粒的一部份。
該等像是電阻器、電感器及電容器的被動電路構件佔據該基板30表面上之有限空間的顯著部份。像是UBM 62及焊燒球點66的互聯結構係經設置於該晶粒的背面上。該半導體封裝68利用許多TSV，像是34及36，經由UBM 62將位於該晶粒頂面上的被動電路構件電氣連接至位於該晶 粒背面上的焊燒球點66，藉此提供更高的晶粒面積使用度並改善可靠性。
圖2e的半導體元件具有大量的被動電路構件。該Cu層54a代表一經圈迴於該基板30表面上之電感器的截面視圖。該電感器係經構成如該基板表面上之經圈迴或捲繞的金屬層。該等導體層40及Cu層54可為電氣共用或電氣隔離，藉此根據所欲電路功能以連接該等被動電路構件。例如，置於TSV 34及36上方之Cu層54的局部可為電氣接觸於Cu層54a，藉以經由UBM 62將由該Cu層54a所構成之電感器的兩者末端分別地連接至位於TSV 34及36下方的焊燒球點66。
按一類似方式，該電阻層42a亦提供一被動電路構件，亦即一連接於該等導體層40之間的電阻器。在電阻層42a間而置於導體層40上方的Cu層54可局部電氣接觸置於TSV 34及36上方的Cu層54a，藉此經由UBM 62將由該電阻層42a所構成之電阻器的兩者末端分別地連接至位於TSV 34及36下方的焊燒球點66。
在另一範例裡，該等導體層40、電阻層42b、絕緣層46、導體層50及Cu層54的組合組成一被動電路，亦即一電阻器而經串接於一金屬－絕緣器－金屬(MIM)電容器。位於電阻層42b下方而接觸導體層40的Cu層54之局部電氣接觸置於TSV 34上方的Cu層54。置於絕緣層46上方之Cu層54的局部則電氣接觸置於TSV 36上方的Cu層54。
從而，該等TSV 34及36可允許將該等被動電路構件 設置在該晶粒的頂面，並且電氣連接至該等設置在該晶粒之背面處的互聯結構。此一位於該基板30頂面上之被動電路構件以及位於該基板30背面上之互聯結構的設置方式可提供更高的晶粒面積使用度並改善可靠性。該等TSV提供頂面被動電路構件與背面互聯結構之間的電氣連接。該電感器及MIM讓該半導體元件能夠執行反應性電路功能而無須使用外部電路構件。
圖3說明該半導體封裝之一替代性具體實施例。重分佈層(RDL)74及80係經構成於該鈍化層60上。在一具體實施例裡，該等RDL 74及80可包含一濕化層、阻障層及附著層。該等RDL 74及80可分別地提供該TSV 34內之Cu材料與焊燒球點78及82之間的電氣接觸。該等RDL 74及80可為由Al、鋁銅合金(AlCu)、Cu或銅合金並連同該等附著及阻障層所製成。該附著層可為Ti、TiN、TiW、Cr或Ta。該阻障層則可為NiV、TaN、TiW或CrCu。RDL 74及80運作如一中介導體層，藉此將電氣信號自焊燒球點78及82導送至該晶粒的各種區域，包含主動及被動電路在內，並且在該半導體封裝86的整合過程中提供各式電氣互聯選項。該等RDL 74及80可提供導送選項，藉此重新配位該等焊燒球點78及82而離於TSV 34及36。一鈍化層84係經構成於該等RDL 74及80和鈍化層60上。
圖4說明該半導體封裝之一替代性具體實施例。一TSV34係利用圖2a－2f中的所述步驟而構成於該半導體封裝的左側面上。一線路接附點板90則是構成於該半導體封裝的 右側面上。
圖5說明該半導體封裝之另一具體實施例。在此具體實施例裡，多個TSV 34及36和焊燒球點66係經供置於該半導體封裝的兩個末端上。被動元件及/或類比電路110係經架置於該鈍化層58上而具底層填入材料114，並由接觸點板112電氣連接。半導體晶粒116係經架置於該鈍化層58而具底層填入材料118，並藉由焊燒球點120而電氣連接於Cu層54。半導體晶粒122係經架置於該鈍化層58而具底層填入材料124，並藉焊燒球點126而電氣連接於Cu層54。具適當熱膨脹係數(CTE)的鑄造複合模128或其他合成聚合材料係經沉積在如圖5所構成之結構上。可利用頂面研磨處理以獲得一更為平坦表面。
圖6a說明半導體晶圓129，此者具有一由矽晶或其他體型半導體材料所製成的基板130。可利用像是KOH之濕性矽晶蝕刻製程以將溝槽或穿孔134及136切入該基板130內。溝槽134與136在後來的階段將變成該等TSV。一絕緣層138係經CVD並依循該基板之廓形而沉積於該基板130上，同時提供一對於溝槽134及136的穿孔襯墊層。該絕緣層138可為由SiO2、SiON、SixNy、Ta2O5、ZrO或其他具有介電性質之材料所製成。該絕緣層138的厚度範圍為從500至30μm，而此厚度通常約為1000。
在圖6b裡，一導電層140係經沉積於該絕緣層138上且經圖案化。該導電層140可為由Al、Al合金、Ti/TiN/Al/TiN、Cu、Ni、Au、Ag或其他導電材料所製成。該導電 層140在穿孔134及136內的圖案可為選擇性。該導電層140的沉積作業可利用PVD、CVD、汽化、電鍍鍍置、無電鍍置或網版印刷製程。該導電層140可根據該基板130上所構成之個別元件的連接性而為電氣共用或電氣隔離。
一電阻層142係經標註為電阻層142a及142b，且沉積於該絕緣層138及該導體層140上並經圖案化。該電阻層142是由具有達約100歐姆/平方之電阻性的矽化物、掺質聚Si、TaN或NiCr所製成。該電阻層142的沉積作業可涉及到PVD或CVD。
一絕緣層146係經圖案化且沉積於該電阻層142b上。該絕緣層146可為由SiO2、SixNy、SiON、Ta2O5、Zr2O5或其他介電材料所製成。該絕緣層146的沉積作業可涉及到PVD或CVD，而其典型厚度為200－4000。
一鈍化層148係經構成於由圖6a－6b所建立之結構上以供結構支撐及電氣隔離。該鈍化層148可為由SiO2、SixNy、SiON、PI、BCB、PBO或其他絕緣材料所製成。可利用一經遮罩定義之微影術製程來移除一部份的鈍化層148以供曝出該等導體層140及絕緣層138和146。
在圖6c裡，一即如Cu鍍置之金屬鍍置150係經沉積且藉厚型光阻152所樣式化。該鍍置層150具有一附著層及種源層。該附著層可為由Ti、TiW、Ta/TaN或Cr所製成。該附著層通常為Cu。一光阻層152係經圖案化於該Cu層154的鍍置層150之上。該Cu層154亦可按如一敷形塗層而沉積於溝槽134及136上。或者，該Cu層154可為透過 一填入製程所構成，這可將Cu沉積入穿孔134及136內。該Cu層154可用以構成互聯以及電感器分支或傳輸線。該等電感器分支係透過Cu鍍置而連同於TSV金屬沉積所構成。該Cu層154係經沉積於溝槽134及136內以及該基板130表面上之其他位置處的導體材料，藉以構成導體層及被動元件或類比電路。該等溝槽134及136內之Cu材料可為在該鈍化層148上的Cu層154及154a所同時構成。或者，該等Cu層的雙鍍處理填入該等溝槽134及136，並在不同時間處構成該Cu層154a。在溝槽134及136內的Cu鍍置速率隨著該導體層140改善。該等Cu層154可為根據經構成於該基板130上之個別元件的連接性而為電氣共用或電氣隔離。
在圖6d裡，該光阻152係經移除。一部份的Cu鍍置層150則由蝕刻處理所移除。一鈍化層158係經鍍附於圖6a－6c的結構上以提供結構支撐及電氣隔離。該鈍化層158可為由SiO2、SixNy、SiON、PI、BCB、PBO或其他絕緣材料所製成。
在圖6e中，該半導體晶圓170係經背部研磨以曝出TSV 134及136。從而，導體穿孔134及136穿過該矽晶基板130。一鈍化層160係經沉積於該半導體晶圓170的背面上且經圖案化。該鈍化層160可為由SiO2、SixNy、SiON、PI、BCB、PBO、環氧樹脂或其他絕緣材料所製成。一UBM 162係經沉積且圖案化以電氣接觸於該等TSV 134及136內的Cu層154。該等UBM162可為Ti、Ni、NiV、Cu、或Cu合 金所製成。該等UBM 162可為一多重金屬堆疊，並且具有附著層、阻障層及濕化層。該附著層可為由T`i、Cr、Al、TiW或氮化鈦(TiN)所製成。該阻障層可為由Ni、NiV、CrCu或TiW所製成。而該濕化層可為由Cu、Au或Ag所製成。該等經曝出的TSV 134及136可用來對準該等UBM 162。或者，可利用一BSA/IR對準以構成該等UBM 162。
一導電焊燒材料係經由一汽化、電鍍鍍置、無電鍍置、焊球滴落或網版印刷製程而沉積於該等UBM 162上。該焊燒材料可為任合金屬合金或導電材料，即如Sn、Pb、Ni、Au、Ag、Cu、Bi及其合金。該焊燒材料係藉由將該導體材料加熱至高於其熔點所重流以構成球型焊球或球點166。在一些應用裡，該等焊燒球點166係經二次重流以改善對該等UBM 162的電氣接觸。該等UBM 162及焊燒球點166代表一種互聯結構。
該等像是電阻器、電感器及電容器的被動電路構件佔據該基板130表面上之有限空間的顯著部份。像是UBM 162及焊燒球點166的互聯結構係經設置於該晶粒的背面上。該半導體封裝170利用許多TSV，像是134及136，經由UBM 162將位於該晶粒頂面上的被動電路構件電氣連接至位於該晶粒背面上的焊燒球點166，藉此提供更高的晶粒面積使用度並改善可靠性。
圖6e的半導體元件具有大量的被動電路構件。該Cu層154a代表一經圈迴於該基板130表面上之電感器的截面視圖。該電感器係經構成如該基板表面上之經圈迴或捲繞 的金屬層。該等導體層140及Cu層154可為電氣共用或電氣隔離，藉此根據所欲電路功能以連接該等被動電路構件。例如，置於TSV 134及136上方之Cu層154的局部可電氣接觸於Cu層154a，藉以經由UBM 162將由該Cu層154a所構成之電感器的兩者末端分別地連接至位於TSV 134及136下方的焊燒球點166。
按一類似方式，該電阻層142a亦提供一被動電路構件，亦即一連接於該等導體層140之間的電阻器。位於電阻層142a間而置於導體層140上方的Cu層154之局部電氣接觸置於TSV 134及136上方的Cu層154，藉此經由UBM 162將由該電阻層142a所構成之電阻器的兩者末端分別地連接至位於TSV 134及136下方的焊燒球點166。
在另一範例裡，該等導體層140、電阻層142b、絕緣層146、導體層150及Cu層154的組合組成一被動電路，亦即一電阻器而經串接於一MIM電容器。位於電阻層142b下方而電氣接觸於導體層140的Cu層154之局部電氣接觸置於TSV 134上方的Cu層154。置於絕緣層146上方之Cu層154的局部電氣接觸置於TSV 136上方的Cu層154。
從而，該等TSV 134及136可允許將該等被動電路構件設置在該晶粒的頂面，並且電氣連接至該等設置在該晶粒之背面處的互聯結構。此一位於該基板130頂面上之被動電路構件以及位於該基板130背面上之互聯結構的設置方式可提供更高的晶粒面積使用度並改善可靠性。該等TSV提供於頂面被動電路構件與背面互聯結構之間的電氣連 接。該電感器及MIM電容器允許該半導體元件能夠執行反應性電路功能而無須使用外部電路器件。
雖既已詳細說明本發明的一或更多具體實施例，然熟諳本項技藝之人士將能瞭解確可對該等具體實施例進行多項修改及調適，而仍不致悖離如後載申請專利範圍中所陳述的本發明範圍。
10‧‧‧覆晶式半導體元件
12‧‧‧主動區域
14‧‧‧晶粒
16‧‧‧晶片載體基板/印刷電路板(PCB)
20‧‧‧焊燒球點結構
22‧‧‧焊燒球點/焊球
24‧‧‧球點點板/互聯處所
26‧‧‧球點點板/互聯處所
28‧‧‧半導體晶圓
30‧‧‧矽晶基板
34‧‧‧溝槽/穿孔
36‧‧‧溝槽/穿孔
38‧‧‧絕緣層
40‧‧‧導電層
42/42a/42b‧‧‧電阻層
46‧‧‧絕緣層
48‧‧‧鈍化層
50‧‧‧鍍置層
52‧‧‧光阻
54‧‧‧Cu層
58‧‧‧鈍化層
60‧‧‧鈍化層
62‧‧‧底層球點金屬化(UBM)
66‧‧‧焊球/球點
68‧‧‧半導體封裝
70‧‧‧聚合黏膠層
72‧‧‧晶片載體
74‧‧‧重分佈層(RDL)
78‧‧‧焊燒球點
80‧‧‧重分佈層(RDL)
82‧‧‧焊燒球點
84‧‧‧鈍化層
86‧‧‧半導體封裝
90‧‧‧線路接附點板
110‧‧‧被動元件/類比電路
112‧‧‧接觸點板
114‧‧‧底層填入材料
116‧‧‧半導體晶粒
118‧‧‧底層填入材料
120‧‧‧焊燒球點
122‧‧‧半導體晶粒
124‧‧‧底層填入材料
128‧‧‧鑄造複合模
130‧‧‧基板
134‧‧‧溝槽/穿孔
136‧‧‧溝槽/穿孔
138‧‧‧絕緣層
140‧‧‧導電層
142/142a/142b‧‧‧電阻層
146‧‧‧絕緣層
148‧‧‧鈍化層
150‧‧‧鍍置層
152‧‧‧光阻
154‧‧‧Cu層
158‧‧‧鈍化層
160‧‧‧鈍化層
162‧‧‧底層球點金屬化(UBM)
166‧‧‧焊球/球點
170‧‧‧半導體晶圓
圖1係一覆晶半導體元件，此者具有焊燒球點，該等球點可提供該晶粒之一主動區域與一晶片載體基板間的電氣互聯；圖2a－2f說明一構成被動電路構件的製程，而此構件具有通至位於該半導體封裝上之背面焊燒球點的直通基板穿孔；圖3說明一半導體封裝，此者具有被動電路構件以及通至焊燒球點的背面RDL；圖4說明一半導體封裝，此者具有經互聯至頂面線路接附點板的被動電路構件以及通至背面焊燒球點的直通基板穿孔；圖5說明一半導體封裝，此者具有經互聯至其他半導體封裝的被動電路構件；以及圖6a－6e說明一構成被動電路構件的替代性製程，此者具有通至位在該半導體封裝上之背面焊燒球點的直通基板穿孔。
30‧‧‧矽晶基板
34‧‧‧溝槽/穿孔
36‧‧‧溝槽/穿孔
38‧‧‧絕緣層
40‧‧‧導電層
42/42a/42b‧‧‧電阻層
46‧‧‧絕緣層
48‧‧‧鈍化層
50‧‧‧鍍置層
54‧‧‧Cu層
58‧‧‧鈍化層
60‧‧‧鈍化層
62‧‧‧底層球點金屬化(UBM)
66‧‧‧焊球/球點
68‧‧‧半導體封裝

Claims (25)

  1. 一種製作一半導體元件的方法，包含如下步驟：提供一基板；在該基板內構成一穿孔；於該基板的一第一表面之上以及在該穿孔內構成一導電層以構成在該基板中的一導體穿孔；在該基板的該第一表面之上構成一第一被動元件，其中該第一被動元件的一部份和該導體穿孔使用該導體層而同時一起形成；在該基板的該第一表面之上構成一第二被動元件，其中該第二被動元件的一部份使用該導體層來形成；在該基板的該第一表面之上構成一絕緣層；在該基板的該第一表面之上構成一類比電路；從該基板之相對於該類比電路的一第二表面移除該基板的部份以曝露在該導體穿孔內的該導體層；在該基板的該第二表面之上構成一底層球點金屬化(UBM)層而電氣接觸於該導體穿孔內的該導體層；在該UBM層上沉積焊燒材料；以及重流該焊燒材料以在該基板的該第二表面之上構成一焊燒球點，其中該導電穿孔經由該基板將該第一被動元件、該第二被動元件和該類比電路而電氣連接至該焊燒球點。
  2. 如申請專利範圍第1項所述之方法，進一步包含在該基板上構成複數個主動元件。
  3. 如申請專利範圍第1項所述之方法，進一步包含在該等導體穿孔與UBM之間構成重分佈層。
  4. 如申請專利範圍第1項所述之方法，其中該類比電路包含一電感器、金屬-絕緣器-金屬電容器或電阻器。
  5. 如申請專利範圍第1項所述之方法，其中構成該類比電路包含構成該導體層於該基板之上並且經捲繞以表現一電感特性。
  6. 如申請專利範圍第1項所述之方法，進一步包含在該基板的該第一表面上構成一線路接附。
  7. 如申請專利範圍第1項所述之方法，進一步包含在該基板上沉積聚合黏膠，並且將一晶片載體接附至該聚合黏膠。
  8. 一種製作一半導體元件的方法，其中包含：提供一基板；構成部分通透該基板的一穿孔；在該基板之上以及在該穿孔內沉積一導體層以構成一導體穿孔；在該基板的一第一表面之上構成一被動元件，其中該被動元件的一部份使用該導體層來形成；移除該基板之相對於該被動元件的一部份以曝露該導體穿孔中的該導體層；以及在該基板之背面上構成一互聯結構而電氣接觸於該導體穿孔，其中該被動元件經由該導體穿孔而電氣連接至位於該基板背面上的互聯結構。
  9. 如申請專利範圍第8項所述之方法，其中在該基板之背面上構成該互聯結構包含：構成一底層球點金屬化層而電氣接觸於該導體穿孔；以及在該底層球點金屬化層上構成一焊燒球點。
  10. 如申請專利範圍第8項所述之方法，進一步包含在該導體穿孔與該互聯結構之間構成一重分佈層。
  11. 如申請專利範圍第8項所述之方法，其中該被動元件係一電感器。
  12. 如申請專利範圍第11項所述之方法，其中該電感器是由銅所製成。
  13. 如申請專利範圍第8項所述之方法，其中該被動元件係一金屬-絕緣器-金屬電容器。
  14. 如申請專利範圍第8項所述之方法，其中該被動元件係一電阻器。
  15. 如申請專利範圍第8項所述之方法，進一步包含在該基板的一表面之上構成一線路接附。
  16. 一種製作一半導體元件的方法，其中包含：提供一基板；構成部分通透該基板的一穿孔；在該基板之上以及在該基板中的該穿孔中配置一導體層以形成一被動元件的一部份於該基板之上；以及在相對於該被動元件的該基板之背面上構成一互聯結構，該互聯結構電氣接觸於該穿孔內的該導體層。
  17. 如申請專利範圍第16項所述之方法，其中在該基板之背面上構成該互聯結構包含：構成一底層球點金屬化層而電氣接觸於該穿孔；以及在該底層球點金屬化層上構成一焊燒球點。
  18. 如申請專利範圍第16項所述之方法，其中該被動元件係電氣接觸在該穿孔內的導體層。
  19. 如申請專利範圍第16項所述之方法，進一步包含在該穿孔與該互聯結構之間構成一重分佈層。
  20. 如申請專利範圍第16項所述之方法，其中該被動元件係一電感器、電容器或電阻器。
  21. 一種半導體元件，其中包含：一基板，其含有一穿孔，該穿孔係部份通透該基板所構成；以及一導體層，其被沉積於該基板之上以及該穿孔之中以在該基板之上構成一被動元件的一部分。
  22. 如申請專利範圍第21項所述之半導體元件，其進一步包含：一底層球點金屬化層，此者係電氣接觸於該穿孔內的導體材料；以及一焊燒球點，此者係經構成在該底層球點金屬化層上。
  23. 如申請專利範圍第22項所述之半導體元件，進一步包含一重分佈層，此者係經構成於該穿孔與該底層球點金屬化層之間。
  24. 如申請專利範圍第21項所述之半導體元件，其中該 被動元件係一電感器、電容器或電阻器。
  25. 如申請專利範圍第21項所述之半導體元件，進一步包含一線路接附，此者係經構成於該基板的頂面上。
TW097137851A 2007-11-29 2008-10-02 用於形成由直通矽晶穿孔連接至背面互聯結構的被動電路元件之半導體元件與方法 TWI490957B (zh)

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US7691747B2 (en) 2010-04-06
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