TWI484608B - 高溫應用所用之銲錫凸塊／凸塊下金屬層結構 - Google Patents

高溫應用所用之銲錫凸塊／凸塊下金屬層結構 Download PDF

Info

Publication number
TWI484608B
TWI484608B TW096145429A TW96145429A TWI484608B TW I484608 B TWI484608 B TW I484608B TW 096145429 A TW096145429 A TW 096145429A TW 96145429 A TW96145429 A TW 96145429A TW I484608 B TWI484608 B TW I484608B
Authority
TW
Taiwan
Prior art keywords
layer
bump
metal
alloy
gold
Prior art date
Application number
TW096145429A
Other languages
English (en)
Other versions
TW200836313A (en
Inventor
Michael E Johnson
Thomas Strothmann
Joan Vrtis
Original Assignee
Flipchip Int Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Flipchip Int Llc filed Critical Flipchip Int Llc
Publication of TW200836313A publication Critical patent/TW200836313A/zh
Application granted granted Critical
Publication of TWI484608B publication Critical patent/TWI484608B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04073—Bonding areas specifically adapted for connectors of different types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

高溫應用所用之銲錫凸塊/凸塊下金屬層結構
本揭露大致係關於電子產品的封裝，而更明確地說，係關於其上形成焊錫或互連凸塊(interconnect bump)的凸塊下金屬層(under bump metallurgy,UBM)結構。
半導體產業習知表面黏著技術(Surface mount technology)利用焊錫凸塊陣列積體電路(IC)封裝技術(例如，覆晶組裝(Flip chip assemblies)、晶片尺寸封裝(chip scale package)以及球狀閘陣列(Ball grid array)結構)來簡化積體電路(例如，包含發光二極體(light emitting diodes,LEDs)之積體電路)的封裝與互連線路。一般而言，在積體電路封裝或其他基材的表面上形成許多圓形(由上方觀看為如此，或者在三度空間中為半球體)的焊錫凸塊，使其與形成於上述基材中或附著於其上的主動或被動元件形成電性接觸。接著將上述之焊錫凸塊對準於形成在第二基材(第一基材將會黏附在此第二基材上)上對應之圖案中的焊墊。一般係在諸如矽次黏著基材(silicon submount)或其他基材之半導體晶圓(例如，Si或GaAs)的頂部生成上述之焊錫凸塊。一般而言，該晶圓的上表面上會形成隔離層或鈍化層(passivation layer)，而可透過形成於該鈍化層中的通孔(via)接觸一系列外露的傳導墊(稱為I/O焊墊)。
一般係將各個焊錫凸塊形成於I/O焊墊其中之一的頂部，該I/O焊墊一般係由鋁金屬製程所形成，然而可應用其他金屬，諸如銅與某些實例中的金。形成焊錫凸塊中，通常先在元件金屬層上形成UBM結構，接著在UBM結構頂部形成焊錫凸塊。
應用焊錫凸塊之元件的熱性能(thermal performance)可能受限於焊錫凸塊結構(包括焊錫凸塊以及其相關之UBM結構)的耐熱性。更明確地說，傳統的焊錫凸塊結構無法在較高溫度(例如，接近或高於250℃)下良好地運作，通常係由於焊錫凸塊結構中不欲之擴散與/或其他不欲之熱性能。
現行的焊錫凸塊連結因為其熱穩定與/或性能的不足而無法承受實質上較高的運作溫度(通常可在較高功率的元件上發現)。再者，現行的高溫焊錫可能含有會污染電子元件(與焊錫凸塊結構相連)之其他部分的金屬。例如，在發光二極體元件中，上述污染物的擴散可能不良地改變散發光線的顏色。
此外，取決於使用的材料，焊錫凸塊結構中的熱不穩定度可能起因於元件的長期連續使用(即便在低溫下)。現行的焊錫凸塊結構雖然在較低溫度的運作中被視為熱穩定，但因為在較高溫度下缺少足夠的穩定性與/或性能，所以無法轉換至高溫應用中。
因此，需要一種改良的焊錫凸塊結構，該結構在較高的運作溫度下更具熱穩定性及具有更好的性能，且可用在電子產品封裝(例如，發光二極體的積體電路封裝)中的互連線路應用(運作溫度約250℃或更高)中。
接下來的敘述與附圖所描述之特定實施例足以讓那些熟悉技術之人士實施本文所述之結構與方法。其他實施例可併入結構、方法與其他改變。實例僅代表可能的變化。
本揭露提出一互連凸塊結構，其具有一焊錫凸塊(或是如下所述由不是焊錫的材料所構成之凸塊)形成於一UBM支撐結構上。此互連或焊錫凸塊結構通常具有改善之熱穩定性(與先前之焊錫凸塊結構相比)，且亦可在250℃或更高(較佳為超過300℃)的運作溫度下更長時間地運作，如下列多個實施例所述。焊錫凸塊結構利用一多層UBM結構，該結構可更耐不欲之擴散並保護元件金屬層同時在焊錫與元件金屬層之間提供良好的附著/結合。選擇用於UBM結構之不同層的材料時，樂見所選之材料提供可耐不欲之擴散(可導致互連的缺陷)的一或更多層。
第一實施例中，UBM結構包括Ni－P、Pd－P與金等層。Ni－P與Pd－P層作為擴散阻障層與/或可焊/可接層。上方覆蓋的金層作為一保護層以避免下方金屬在凸塊附著製程之前受到氧化。
第二實施例中，UBM結構包括Ni－P與金等層。Ni－P層作為擴散阻障層與/或可焊/可接層。上方覆蓋的金層作為一保護層。
第三實施例中，UBM結構包括：(i)一金屬(例如，鈦、鋁或Ti/W合金)薄層，具有良好的導電性與附著力；(ii)一金屬(例如，NiV、W、Ti、Pt、Ti/W合金或Ti/W/N合金)阻障層，作為一金屬阻障且係經選擇可潤濕(wettable)將使用之所選焊錫合金；以及(iii)一附加金屬(例如，Pd－P、Ni－P、NiV或Au)層，覆蓋於該金屬阻障層上。或者，在該金屬阻障層頂部具有金屬或合金的第二附加層。可利用上述形成金屬阻障層所列材料的其中之一形成第二附加層。覆蓋於上的金層作為一保護層。
舉例來說，可由一或多個下列材列在UBM結構上形成互連凸塊或焊錫凸塊：PbSbGa、PbSb、AuGe、AuSi、AuSn、ZnAl、CdAg、GeAl、Au、Ag、Pd、Pb、Ge、Sn、Si、Zn、Al或上述之組合物。在其他實施例中，作為焊錫凸塊的替代，可將金或銀凸塊置於本文所述之UBM金屬或合金任何一者(可與上述之金或銀材料的使用相容)的頂部上。
應當注意，上述可焊/可接層(們)意指其適和焊接以及打線接合(wire bonding)。這些表面即便在焊接凸塊的高溫組裝後仍適合打線接合。
 UBM結構的形成
晶圓級上，一般係在元件或矽次黏著基材或其他基材金屬層上形成UBM結構。大多數元件的金屬層通常為鋁，然而可使用其他金屬，諸如銅與較少見的金。UBM結構係多層且可包括個別的黏著層、催化層、阻障層、可焊/可接層、表面保護層與/或具由這些特性之組合的層。
舉例來說，可藉由金屬薄膜濺射法或藉由浸置鍍覆、無電(electroless)鍍覆、電解質鍍覆法或藉由濺射與鍍覆之組合形成UBM結構。雖然本文描述之特定實施例係利用鍍覆與濺射，但可利用其他形成UBM結構中一或多層的適當製造方法(例如，蒸鍍(evaporation)、印刷等)。
利用鍍覆形成UBM結構
下方描述利用鍍覆技術形成UBM結構之五個不同、非限制性實例。各個實例中，首先透過浸置鍍覆法在元件金屬層表面上沉積催化薄層。應當注意第1至第5圖中並未顯示UBM結構的犧牲金屬與催化層以便清楚描述。下列實例為可預知的實例。
實例1 參照第1 圖，在元件201 的金屬表面202 上形成UBM結構200 的初始層，而金屬表面通常為鋁或銅。為了描述之故，顯示具有元件金屬表面202 以及圍繞之鈍化層203 的單一I/O焊墊。
初始層係耗損金屬(sacrificial metal)或催化劑之一薄層，且係透過浸鍍法沉積於金屬表面202 上。若該元件具有鋁的金屬結構，則該沉積金屬為鋅(耗損金屬層)。若該元件之金屬結構為銅，則該沉積金屬為鈀(進一步鍍覆所用之催化劑)。
應當注意此揭露中提到Pd係用來當作催化劑，因此在最終的UBM結構中保留非常薄的一層Pd。然而，此揭露中提到鋅係用來當作耗損金屬，那麼在最終的UBM結構中大體上不殘留Zn層。再者，當基材/晶圓進入無電鍍覆槽時，在鎳鍍覆開始前Zn立即溶解並回到溶液中。最適合將鋅層描述成具有保護Al不受氧化之效果的耗損金屬層。一但在Ni槽中移除Zn薄層後，可暴露乾淨(未氧化)的Al。Ni可鍍覆於乾淨的Al上而不是受氧化的Al上。
沉積金屬催化或耗損層後，形成含有P的鎳－磷(Ni－P)合金層204 。合金含有P的重量百分比範圍約1－16%，較佳的範圍約7－9%，且可透過無電鍍覆法加以沉積。某些實例中，合金中P的百分比可能低於1%。Ni－P沉積物的厚度範圍係0.1－50微米，較佳的範圍係1－5微米。沉積Ni－P後，透過浸鍍法沉積鈀金屬催化薄層(未顯示)。
接著，形成鈀－磷(Pd－P)合金層206 。合金含有P的重量百分比範圍約0.1－10%，較佳的範圍約0.1－5%，且可透過無電鍍覆法加以沉積。Pd－P沉積物的厚度範圍係0.1－50微米，較佳的範圍係0.1－5微米。此處的層204 與206 可提供金屬合金堆疊。
沉積Pd－P後，透過浸鍍法鍍覆一金層208 。金層的厚度範圍係0.02－3.0微米，較佳的範圍係0.05－0.1微米。
UBM結構200 的Ni－P與Pd－P層(204 、206 )可作為阻障層或可焊/可接層任一者，或是這些層提供這些功能的組合，這係取決於層的厚度。金層208 取決於層的厚度可作為一保護層或可焊/可接層。
可利用催化層(未顯示)來幫助沉積個別隨後之層，且雖然它們相當薄，它們特定的厚度可取決於沉積設備、技術、製程參數以及應用材料之品質而有所改變，而這取決於設備製造商而有所改變。或者，可在Ni－P沉積後不需沉積鈀金屬催化劑來執行上述步驟，因為取決於應用之條件與材料品質，有可能直接在Ni－P層上形成適當的Pd－P沉積物。
實例2 在耗損或催化薄層沉積、Ni－P沉積與Au層沉積(但省略Pd－P層沉積步驟)等步驟之後，根據實例1所述之步驟形成UBM結構300 (描繪於第2圖中)。因此，沉積Ni－P層204 之後，係透過浸鍍法沉積一金層208 。金層208 的厚度範圍係0.02－3.0微米，較佳的範圍係0.05－0.1微米。在此實施例中，Ni－P層作為一阻障或可焊/可接層，或提供這些功能之組合。金層取決於層的厚度可作為保護層或可焊/可接層。
實例3 此實例僅適用於具有Cu金屬結構的元件。第3圖所述之UBM結構400 係藉由下述步驟加以形成：首先沉積鈀金屬催化劑於Cu表面上(如同上述之實例1)，接著透過無電鍍覆法沉積Pd－P層402 ，其中P的重量百分比範圍係0.1－10%，更好的範圍係0.1－5%。Pd－P層402 的厚度範圍係0.1－50微米，較佳的範圍係0.1－5微米。
沉積Pd－P層之後，利用浸鍍法沉積一金層404 。金層的厚度範圍係0.02－3微米，較佳的範圍係0.05－0.1微米。在此實例中，Pd－P層作為一阻障層與可焊/可接層。Au層作為一保護層。
實例4 以類似上述實例3之方式形成UBM結構500 (描繪於第4圖中)。在此實施例中，並沒有在Pd－P層402 上沉積任何其他層。在此實施例中，因為Pd－P不像Ni－P那麼易於氧化，Pd－P層可作為一阻障層與可焊/可接層。
實例5 以類似上述實例1之方式形成UBM結構600 (描繪於第5圖中)，接著透過無電鍍覆法在第一Ni－P層204 頂部沉積第二Ni－P層602 。第二Ni－P層602 之P百分比不同於第一層204 ，而其重量百分比範圍係1－16%，但較佳的範圍係1－6%。第二Ni－P層602 的厚度範圍係0.1－50微米，較佳的範圍係1－5微米。沉積第二Ni－P層602 之後，透過浸鍍法沉積一金層604 。金層604 的厚度範圍係0.02－3微米，較佳的範圍係0.02－0.10微米。在此實施例中，第一Ni－P層204 層作為一阻障層。第二Ni－P層602 作為一阻障層與可焊層。Au層604 作為一保護層。
利用濺射沉積與鍍覆形成UBM結構
利用濺射沉積與鍍覆技術形成UBM結構的許多非限制實例描述於下。該些實例之各者中，首先透過濺射沉積製程在元件金屬表面上沉積具有良好導電性與附著力的金屬薄層。上述之金屬的實例包括鈦、鋁與TiW合金。
接下來，可將最好作為一阻障金屬且係經選擇可潤濕所選之焊錫合金的金屬沉積在傳導金屬薄層頂部。上述之金屬的實例包括NiV、W、Ti、Pt、Ti/W合金與Ti/W/N合金。在金屬快速氧化的實例(例如，NiV)中，可選擇性沉積一保護層以避免氧化，接著在沉積接隨後之層前移除該保護層。
接著可將金屬合金(諸如，Pd－P、Ni－P或NiV或TiW)沉積於阻障金屬上。在這沉積之前，可選擇性地在阻障金屬上沉積耗損或催化薄層以助於該金屬合金的沉積，而這取決於所用之合金類型。最後，沉積一金或銀層。應當注意某些下方之實例(例如，實例10與17)可省略某些上述之步驟。
實例6 首先透過在元件金屬結構202 表面上濺射沉積鈦金屬附著薄層802 以形成UBM結構800 (描繪於第6圖中)。元件金屬結構202 通常係鋁、銅或金。
接下來，將鎳釩(作為阻障金屬)阻障層804 濺射於附著層802 上。然而，NiV層804 一但接觸空氣之後會快速地氧化，因此可能會造成該材料難以蝕刻與照下圖案。因此，可利用一選擇性施用的保護層(未顯示)來避免NiV材料的氧化。例如，可利用濺射沉積來沉積鋁之薄層。可在鍍覆金屬於NiV表面之前移除鋁層。
在沉積NiV層804 或移除鋁(若有應用來避免氧化)之後，可選擇性地透過浸鍍法在NiV層804 頂部沉積鈀金屬催化薄層(未顯示)。接著，透過無電鍍覆法在鈀金屬催化層(若應用催化劑)或NiV層(若無應用催化劑)頂部沉積鈀－磷(Pd－P)合金層806 ，其中P的重量百分比範圍係0.1－10%，較佳的範圍係0.1－5%。Pd－P沉積物的厚度最好係介於0.1－5微米之間。
接著，透過浸鍍法鍍覆金層808 。金層的厚度範圍係0.02－3.0微米，較佳的範圍係0.05－0.10微米。
在此實施例中，NiV與Pd－P層804 與806 取決於層的厚度可作為阻障層與/或可焊層。金層808 可作為保護層。
實例7 除了以一鋁層(作為一附著層)替換上述初步金屬沉積步驟中的鈦層802 之外，採用實例6的步驟形成一類似結構800 的UBM結構。
實例8 除了以一鎢層替換阻障金屬沉積步驟中的NiV層804 之外，採用實例6或7的步驟形成一類似結構800 的UBM結構。
實例9 除了在附著層802 與阻障層804 兩者中應用鈦之外，採用實例6的步驟形成一類似結構800 的UBM結構。
實例10 利用上述實例6之初步金屬沉積、阻障金屬沉積、選擇性施用的保護層沉積與金層沉積等步驟形成一UBM結構900 (描繪於第7圖中)。透過浸鍍法在NiV層804 頂部沉積金層808 (注意在此實例中省略Pd－P層806 )。Au層808 的厚度範圍係0.02－3.0微米，較佳的範圍係1－2微米。在此實施例中，NiV層804 可作為阻障層與/或可焊層。Au層808 取決於層的厚度可作為保護層或可焊/可接層。
實例11 首先採用實例6之初步金屬沉積步驟形成一UBM結構1000 (描繪於第8圖中)，其中鈦層802 係沉積於金屬層202 上。之後，透過濺射法在鈦層802 上沉積鎢(W)層1002 。沉積鎢層1002 之後，透過無電鍍覆法沉積鎳－磷(Ni－P)層1004 ，其中P的範圍係1－16%，較佳係介於7－9%之間。Ni－P層1004 的厚度範圍係0.1－50微米，較佳係介於1－5微米之間。沉積Ni－P之後，透過浸鍍法鍍覆金層808 。金層808 的厚度範圍係0.02－3.0微米，較佳的範圍係0.02－0.10微米。
實例12 除了以一濺射之NiV層替換實例11之Ni－P層1004 之外，形成一類似實例11之UBM結構1000 的UBM結構。
實例13 除了以一濺射之Ti/W合金層替換實例11之W層1002 之外，形成一類似實例11之UBM結構1000 的UBM結構。
實例14 除了以一濺射之Ti/W/N合金層替換實例11之W層1002 之外，形成一類似實例11之UBM結構1000 的UBM結構。
實例15 除了以一濺射之Ti/W合金層替換實例11之W層1002 (阻障金屬沉積步驟)以及以一濺射之NiV合金層替換Ni－P層1004 (合金沉積步驟)之外，形成一類似實例11之UBM結構1000 的UBM結構。
實例16 除了以一濺射之Ti/W/N合金層替換實例11之W層1002 (阻障金屬沉積步驟)以及以一濺射之NiV合金層替換Ni－P層1004 (合金沉積步驟)之外，形成一類似實例11之UBM結構1000 的UBM結構。
實例17 首先在元件金屬結構202 上沉積鈦層802 ，接著透過無電或浸置鍍覆法沉積金層808 來形成UBM結構1100 (描繪於第9圖中)。舉例來說，此Au層808 的厚度範圍約0.02－3微米。在此實施例中，鈦層802 作為附著層與阻障層。金層808 取決於層的厚度作為保護層或可焊層。
舉例而言，實例6－17的個別濺射金屬/合金層之厚度範圍約0.01－1微米(取決於所欲之功能)。該厚度最好足以形成一良好阻障且同時確保應力相關之剝落(peeling)或斷裂(cracking)達到最小。
作為上述實例中所描述之無電與浸置鍍覆方法的替代，可透過電解質鍍覆法執行鍍覆。可藉由電解質鍍覆法完成無電與浸置鍍覆。對於無電鍍覆之合金而言，僅鍍覆合金的金屬(例如，Ni或Pd)成分(即，並無鍍覆磷合金成分)。電解質鍍覆法不需要催化層。可利用電解質鍍覆法替代地鍍覆實例6－17中所述之濺射Ti與W層。
實例18 透過濺射法在元件的銅或鋁金屬結構202 表面上形成一UBM結構1200 (描繪於第10圖中)。明確地說，濺射金屬的第一層1202 係TiW合金，且其厚度範圍約50－10,000埃。濺射金屬的第二層1204 係Ti/W/N合金，且其厚度範圍約50－10,000埃。濺射金屬的第三層1206 係TiW合金，且其厚度範圍約50－10,000埃。濺射金屬的第四層1208 係金，且其厚度範圍約50－10,000埃。
實例19 此處之UBM結構類似於實例18，除了不利用UBM結構1200 的第一層TiW合金1202 。
實例20 此處之UBM結構類似於實例18，除了不利用UBM結構1200 的第三層TiW合金1206 。
實例21 此處之UBM結構類似於實例18，除了不利用UBM結構1200 的第一與第三層(1202 、1206 )TiW合金。
實例22 此處之UBM結構類似於實例18，除了不利用UBM結構1200 的第二與第三層(1204 、1206 )之Ti/W/N與TiW合金。
實例23 如同第11圖中所述，以元件金屬(金)層1302 形成一UBM結構1300 。形成結構1300 時，在元件金屬層1302 頂部上濺射金層1304 。舉例而言，金層的厚度範圍約50－10,000埃。
實例24 形成一類似UBM結構1300 之UBM結構，其中並沒有金屬濺射於元件金屬層1302 頂部。元件金屬層1302 本身作為UBM結構，其上稍後形成焊錫凸塊。
實例25 形成一類似實例23之UBM結構1300 的UBM結構，但在濺射層1304 之後，藉由諸如無電鍍覆、浸置鍍覆或電解質鍍覆方法在層1304 頂部鍍覆一額外的金層(未顯示)，該層厚度介於約0.5－150微米。
焊錫凸塊的形成
形成UBM結構之後，根據上述實例其中之一或其他適當製造方法可在UBM結構上形成互連凸塊(例如，焊錫凸塊)。舉例來說，在晶圓面形成焊錫凸塊並透過迴焊(reflow)或鍍覆方法將其附著於UBM結構。第12圖提供焊錫凸塊結構1400的大致描述。雖然下方之實例描述利用錫膏印刷(solder paste printing)與鍍覆方法來形成焊錫凸塊1402，但可利用預先形成的錫球沉積與其他適當方法來在UBM結構上形成焊錫凸塊。
1.以印刷銲膏沉積來形成焊錫凸塊 在焊錫凸塊結構1400 的第一實施例中，將由適當高溫合金製成的錫膏藉由印刷方法透過原位或分離印刷模板(stencil)中的開口沉積在UBM結構上。接著迴焊沉積之錫膏以形成焊錫凸塊1402 。舉例來說，迴焊之後得到之焊錫凸塊的高度約1－500微米。迴焊期間，在焊錫凸塊與下方之UBM結構之間形成金屬鏈結。適當的錫膏合金包括下列實例：金/錫共熔合金(80Au/20Sn，共熔溫度280℃)；鉛/銀共熔合金(97.5Pb/2.5Ag，共熔溫度303℃)；鉛/銀/錫共熔合金(97.5Pb/1.5Ag/1Sn，共熔溫度309℃)；鉛/錫高度合金(95Pb/5Sn，熔點314℃)；金/鍺共熔合金(88Au/12Ge，共熔溫度356℃)；金/矽共熔合金(97Au/3Si，共熔溫度363℃)；鋅/鋁共熔合金(94Zn/6Al，共熔溫度381℃)；以及鍺/鋁共熔合金(55Ge/45Al，共熔溫度424℃)。
2.以鍍覆沉積來形成焊錫凸塊 在凸塊結構的第二實施例中，可在鋁或銅元件、矽次黏著基材或其他基材之金屬結構表面或例如任何實例1－10中所述之UBM結構上鍍覆適當材料好形成凸塊以用於互連。在此實施例中，鍍覆之材料的厚度介於約1與500微米之間。可取決於即將鍍覆之材料種類與厚度而透過無電、浸置或電解質方法執行鍍覆。可將凸塊施加於元件或基材上。可透過熱超音波(thermo－sonic)或熱壓縮(thermo－compression)晶粒附著技術或迴焊技術(若可應用)將元件附著於基材。可用於此實施例之適當鍍覆金屬或合金包括下列實例：金(Au)、銀(Ag)、鈀(Pd)、鉛/銀共熔合金(97.5Pb/2.5Ag)、鉛/錫高度合金(95Pb/5Sn)、鋅/鋁共熔合金(94Zn/6Al)以及金/錫共熔合金(80Au/20Sn)。
在焊錫凸塊結構的第三實施例中，如同上述之第二實施例般施加凸塊材料。在此實施例中，以迴焊技術透過利用焊錫合金將元件、矽次黏著基材或其他基材附著於相應之基材上。利用此方法，將熔點低於凸塊材料的焊錫合金材料施加於凸塊表面或相對應之基材附著表面的任一者上。此材料作為一熔點較低(與焊錫凸塊相比)表面，凸塊與相應之基材附著表面兩者可在迴焊之後結合於該材料上。這可在一較低的迴焊溫度(比起迴焊該凸塊所須溫度)下形成一可靠的連結。可在此實施例中應用之適當焊錫合金材料包括下列實例：鉛/銀共熔合金(97.5Pb/2.5Ag，共熔溫度303℃)；鉛/銀/錫共熔合金(97.5Pb/1.5Ag/1Sn，共熔溫度309℃)；鉛/錫高度合金(95Pb/5Sn，熔點314℃)；金/鍺共熔合金(88Au/12Ge，共熔溫度356℃)；金/矽共熔合金(97Au/3Si，共熔溫度363℃)；鋅/鋁共熔合金(94Zn/6Al，共熔溫度381℃)；鍺/鋁共熔合金(55Ge/45Al，共熔溫度424℃)；以及金/錫共熔合金(80Au/20Sn，共熔溫度280℃)。
3.以預先形成之錫球形成焊錫凸塊 以任何已經討論之凸塊材料構成的預先形成錫球可沉積於任何上述之UBM結構以形成高溫互連結構。
結論 取決於特定實施例，上述互連凸塊結構之應用的實例可包括下列：含有一或多個互連之功率放大級(power amplification stage)的電子組件；球狀閘陣列封裝上需要高散熱條件之高密度、多層互連積體電路電子元件；含有一或多層互連、嵌入式電路之多層電路板；以及在正常運作條件下輸出大輸出功率與/或消耗大功率發光二極體元件。上述之互連凸塊結構通常用於許多電子封裝應用中，包括諸如球狀閘陣列(BGA)、晶片尺寸封裝(CSP)以及覆晶結構。
雖然已經參照示範性實施例呈現本揭露，但上述之描述僅為說明之目的，不應視為本發明之範圍的限制。那些熟悉技術之人士可在不悖離由申請專利範圍所提出之本發明精神與範圍的情況下，對所述之實施例作出各種改良與變動。將由接下來的申請專利範圍來確定本發明。
200、300、400、500、600、800、900、1000、1100、1200、1300．．．UBM結構
201．．．元件
202．．．金屬結構
203．．．保護層
204、1004．．．Ni－P合金層
206、402、806．．．Pd－P合金層
208、404、604、808、1304．．．金層
602．．．第二Ni－P合金層
802．．．鈦金屬附著薄層
804．．．鎳釩阻障層
1002．．．鎢層
1202．．．第一層
1204．．．第二層
1206．．．第三層
1208．．．第四層
1302．．．元件金屬層
1400．．．焊錫凸塊結構
為了更完整地了解本揭露，現參照下述之圖式，其中所有圖式中相同的元件符號代表相同的元件：第1至5圖描述利用鍍覆所形成之UBM結構。
第6至9圖描述利用濺射沉積與鍍覆所形成之UBM結構。
第10與11圖描述透過在元件金屬結構上濺射所形成之UBM結構。
第12圖描述焊錫凸塊形成於UBM結構上的焊錫凸塊結構。
本文提出之範例描述特定之實施例，且不預期上述之範例以任何方式作為限制。
201‧‧‧元件
202‧‧‧金屬結構
203‧‧‧鈍化層
1400‧‧‧焊錫凸塊結構

Claims (31)

  1. 一種互連結構，包含：一金屬結構層，具有一Cu金屬結構表面；一Pd催化層，形成於該Cu金屬結構表面上；一Ni-P合金層，形成於該Pd催化層上；一Pd-P層，覆蓋於該Ni-P合金層上；一金層，覆蓋於該Pd-P層上；以及一凸塊或打線，覆蓋於該金層上。
  2. 如申請專利範圍第1項所述之結構，其中該凸塊係一焊錫材料層。
  3. 如申請專利範圍第1項所述之結構，其中該凸塊係一純淨金屬互連凸塊。
  4. 如申請專利範圍第1項所述之結構，其中該凸塊係一焊錫凸塊。
  5. 如申請專利範圍第1項所述之結構，其中該凸塊係由選自下列所構成之群組之一材料所形成：PbSbGa、AuGe、AuSi、AuSn、ZnAl、CdAg、GeAl、Au、Pd、Ge、Si、Al與上述之組合。
  6. 如申請專利範圍第1項所述之結構，更包含一Pd催化層，配置於該Ni-P合金層與該Pd-P層之間。
  7. 如申請專利範圍第1項所述之結構，其中該Ni-P合金層係一第一Ni-P層，且該結構更包含一第二Ni-P層配置於該第一Ni-P層與該金層之間，其中該第二Ni-P層之P的重量百分比低於該第一Ni-P層之P的重量百分比。
  8. 如申請專利範圍第1項所述之結構，其中該凸塊係由98Pb/1.2Sb/0.8Ga、88Au/12Ge、97Au/3Si、94Zn/6Al、95Cd/5Ag、55Ge/45Al或80Au/20Sn所形成。
  9. 如申請專利範圍第1項所述之結構，其中該凸塊係由AuGe、AuSi、AuSn、Au或上述之組合所形成。
  10. 一種發光二極體(LED)元件，包含一互連結構，其中該互連結構包含：一接觸墊，該接觸墊包含Al或Cu；一Pd催化層，配置於該接觸墊上；一Ni-P合金層，覆蓋於該Pd催化層上；一Pd-P層，覆蓋於該Ni-P合金層上；一金層，覆蓋於該Pd-P層上；以及 一凸塊或打線，覆蓋於該金層上；其中該互連結構係可在高於250℃的溫度下運作。
  11. 如申請專利範圍第10項所述之元件，其中該金層之厚度係約0.02至3.0微米。
  12. 如申請專利範圍第10項所述之元件，其中該凸塊係由選自下列所構成之群組之一材料所形成：PbSbGa、AuGe、AuSi、AuSn、ZnAl、CdAg、GeAl、Au、Pd、Ge、Si、Al與上述之組合。
  13. 如申請專利範圍第10項所述之元件，其中該Ni-P合金層包含約1至16重量百分比之範圍內的P。
  14. 如申請專利範圍第10項所述之元件，其中該Ni-P合金層的厚度係約0.1至50微米。
  15. 如申請專利範圍第10項所述之元件，更包含一Pd金屬催化薄層，配置於該Ni-P合金層與該Pd-P層之間。
  16. 如申請專利範圍第10項所述之元件，其中該Pd-P層包含約0.1至10重量百分比之範圍內的P。
  17. 如申請專利範圍第10項所述之元件，其中該Pd-P層的厚度係約0.1至50微米。
  18. 如申請專利範圍第10項所述之元件，其中該Ni-P合金層係一第一Ni-P層，且該元件更包含一第二Ni-P層，介於該第一Ni-P層與該凸塊之間，其中該第二Ni-P層之P的重量百分比低於該第一Ni-P層之P的重量百分比。
  19. 如申請專利範圍第18項所述之元件，其中該第二Ni-P層包含約1至16重量百分比之範圍內的P。
  20. 如申請專利範圍第10項所述之元件，其中該互連結構係利用一或更多個下列製程所形成：印刷焊膏之沉積、鍍覆(plated)之沉積、預先形成之球形配置或利用熔點不同之焊錫的製程。
  21. 如申請專利範圍第20項所述之元件，其中該凸塊係由具有介於約1與500微米之間的高度之材料所形成。
  22. 一種互連結構，包含：一金屬結構層，具有一Cu金屬結構表面，該金屬結構層位於一半導體晶圓或基材上方；一Pd催化層，位於該Cu金屬結構表面上； 一Ni-P合金層，位於該Pd催化層上；以及一Pd-P層，覆蓋於該Ni-P合金層上。
  23. 如申請專利範圍第22項所述之互連結構，更包含一金層覆蓋於該Pd-P層上。
  24. 如申請專利範圍第22項所述之互連結構，更包含一凸塊或打線覆蓋於該Pd-P層上。
  25. 一種形成一互連結構的方法，包含：形成一鋁金屬結構表面；沉積一耗損Zn金屬層於該鋁金屬結構表面上；形成一Ni-P合金層於該耗損Zn金屬層上；形成一Pd-P層覆蓋於該Ni-P合金層上；形成一金層覆蓋於該Pd-P層上；以及形成一凸塊或打線覆蓋於該金層上。
  26. 如申請專利範圍第25項所述之方法，其中該凸塊係由選自下列所構成之群組之一材料所形成：PbSbGa、AuGe、AuSi、AuSn、ZnAl、CdAg、GeAl、Au、Pd、Ge、Si、Al與上述之組合。
  27. 如申請專利範圍第25項所述之方法，更包含：在形成 該Pd-P層之前，形成一Pd催化層於該Ni-P合金層上。
  28. 如申請專利範圍第25項所述之方法，其中該耗損Zn金屬層係透過浸置鍍覆法所沉積。
  29. 一種形成一互連結構的方法，包含：形成一銅或鋁金屬結構表面於一半導體晶圓或基材上方；形成一Pd催化層或一耗損Zn金屬層於該金屬結構表面上；形成一Ni-P合金層於該Pd催化層或該耗損Zn金屬層上；以及形成一Pd-P層覆蓋於該Ni-P合金層上。
  30. 如申請專利範圍第29項所述之方法，更包含：形成一金層覆蓋於該Pd-P層上。
  31. 如申請專利範圍第30項所述之方法，更包含：形成一凸塊或打線覆蓋於該金層上。
TW096145429A 2006-12-11 2007-11-29 高溫應用所用之銲錫凸塊／凸塊下金屬層結構 TWI484608B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/609,036 US20080136019A1 (en) 2006-12-11 2006-12-11 Solder Bump/Under Bump Metallurgy Structure for High Temperature Applications

Publications (2)

Publication Number Publication Date
TW200836313A TW200836313A (en) 2008-09-01
TWI484608B true TWI484608B (zh) 2015-05-11

Family

ID=39497008

Family Applications (2)

Application Number Title Priority Date Filing Date
TW096145429A TWI484608B (zh) 2006-12-11 2007-11-29 高溫應用所用之銲錫凸塊／凸塊下金屬層結構
TW102105302A TW201330206A (zh) 2006-12-11 2007-11-29 高溫應用所用之銲錫凸塊／凸塊下金屬層結構

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW102105302A TW201330206A (zh) 2006-12-11 2007-11-29 高溫應用所用之銲錫凸塊／凸塊下金屬層結構

Country Status (6)

Country Link
US (1) US20080136019A1 (zh)
EP (1) EP2100328A4 (zh)
KR (1) KR20090103911A (zh)
CN (1) CN101632160B (zh)
TW (2) TWI484608B (zh)
WO (1) WO2008073807A1 (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006040847A1 (ja) * 2004-10-14 2006-04-20 Ibiden Co., Ltd. プリント配線板及びプリント配線板の製造方法
WO2009146373A1 (en) * 2008-05-28 2009-12-03 Mvm Technoloiges, Inc. Maskless process for solder bumps production
US20120280023A1 (en) * 2008-07-10 2012-11-08 Lsi Corporation Soldering method and related device for improved resistance to brittle fracture
WO2010051106A2 (en) * 2008-09-12 2010-05-06 Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University Methods for attaching flexible substrates to rigid carriers and resulting devices
TWI394253B (zh) * 2009-03-25 2013-04-21 Advanced Semiconductor Eng 具有凸塊之晶片及具有凸塊之晶片之封裝結構
US8536458B1 (en) 2009-03-30 2013-09-17 Amkor Technology, Inc. Fine pitch copper pillar package and method
TWI469288B (zh) * 2009-06-11 2015-01-11 Chipbond Technology Corp 凸塊化晶片結構及其應用之半導體覆晶裝置
US8569897B2 (en) * 2009-09-14 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protection layer for preventing UBM layer from chemical attack and oxidation
KR101077340B1 (ko) * 2009-12-15 2011-10-26 삼성전기주식회사 기판 제조용 캐리어 부재 및 이를 이용한 기판의 제조방법
US8264089B2 (en) * 2010-03-17 2012-09-11 Maxim Integrated Products, Inc. Enhanced WLP for superior temp cycling, drop test and high current applications
US8492893B1 (en) * 2011-03-16 2013-07-23 Amkor Technology, Inc. Semiconductor device capable of preventing dielectric layer from cracking
JP5675525B2 (ja) * 2011-07-28 2015-02-25 日産自動車株式会社 半導体装置の製造方法及び半導体装置
US8865586B2 (en) * 2012-01-05 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. UBM formation for integrated circuits
CN103249256A (zh) * 2012-02-14 2013-08-14 景硕科技股份有限公司 线路图案的表面处理结构
US9425064B2 (en) * 2012-12-18 2016-08-23 Maxim Integrated Products, Inc. Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages
KR20140130618A (ko) * 2013-05-01 2014-11-11 서울바이오시스 주식회사 솔더 페이스트를 통해 접착된 발광 다이오드를 갖는 발광 다이오드 모듈 및 발광 다이오드
US9196812B2 (en) 2013-12-17 2015-11-24 Samsung Electronics Co., Ltd. Semiconductor light emitting device and semiconductor light emitting apparatus having the same
US9779969B2 (en) * 2014-03-13 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method
US9627335B2 (en) * 2014-05-08 2017-04-18 Infineon Technologies Ag Method for processing a semiconductor workpiece and semiconductor workpiece
CN104201121A (zh) * 2014-09-17 2014-12-10 北京理工大学 一种铜柱凸点封装结构的成型方法
CN107251216B (zh) * 2015-02-25 2021-03-23 英特尔公司 用于微电子结构中的互连垫的表面末道层
KR102627991B1 (ko) * 2016-09-02 2024-01-24 삼성디스플레이 주식회사 반도체 칩, 이를 구비한 전자장치 및 반도체 칩의 연결방법
CN107579032B (zh) * 2017-07-27 2019-04-09 厦门市三安集成电路有限公司 一种化合物半导体器件的背面制程方法
JP7172211B2 (ja) * 2017-07-28 2022-11-16 Tdk株式会社 導電性基板、電子装置及び表示装置
US20210217919A1 (en) * 2018-05-28 2021-07-15 Ecole Polytechnique Federale De Lausanne (Epfl) Excitonic device and operating methods thereof
KR102617086B1 (ko) 2018-11-15 2023-12-26 삼성전자주식회사 Ubm을 포함하는 웨이퍼-레벨 반도체 패키지
CN117549616A (zh) 2019-04-02 2024-02-13 住友电气工业株式会社 复合部件和散热部件
US11682640B2 (en) * 2020-11-24 2023-06-20 International Business Machines Corporation Protective surface layer on under bump metallurgy for solder joining
US20240106397A1 (en) * 2022-09-23 2024-03-28 Wolfspeed, Inc. Transistor amplifier with pcb routing and surface mounted transistor die
WO2024065293A1 (zh) * 2022-09-28 2024-04-04 泉州三安半导体科技有限公司 一种发光二极管及发光装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164224A (ja) * 1986-12-26 1988-07-07 Furukawa Electric Co Ltd:The 電気接続用テ−プ状リ−ド
US20020121709A1 (en) * 2000-12-28 2002-09-05 Fujitsu Limited External connection terminal and semiconductor device
US6798050B1 (en) * 1999-09-22 2004-09-28 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor element with copper pad mounted on wiring substrate and method for fabricating the same
US6945447B2 (en) * 2002-06-05 2005-09-20 Northrop Grumman Corporation Thermal solder writing eutectic bonding process and apparatus
US20050224981A1 (en) * 2004-04-08 2005-10-13 Nishant Sinha Semiconductor processing methods for forming electrical contacts
WO2006040847A1 (ja) * 2004-10-14 2006-04-20 Ibiden Co., Ltd. プリント配線板及びプリント配線板の製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69829018T2 (de) * 1997-06-10 2006-03-23 Canon K.K. Substrat und Verfahren zu dessen Herstellung
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
SE512906C2 (sv) * 1998-10-02 2000-06-05 Ericsson Telefon Ab L M Förfarande vid lödning av ett halvledarchip samt RF-power transistor för genomförande därav
US6259161B1 (en) * 1999-06-18 2001-07-10 Mitsubishi Denki Kabushiki Kaisha Circuit electrode connected to a pattern formed on an organic substrate and method of forming the same
US6506672B1 (en) * 1999-06-30 2003-01-14 University Of Maryland, College Park Re-metallized aluminum bond pad, and method for making the same
KR100298827B1 (ko) * 1999-07-09 2001-11-01 윤종용 재배선 기판을 사용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
JP2001339141A (ja) * 2000-05-29 2001-12-07 Kyocera Corp 配線基板
US6445069B1 (en) * 2001-01-22 2002-09-03 Flip Chip Technologies, L.L.C. Electroless Ni/Pd/Au metallization structure for copper interconnect substrate and method therefor
JP2002280731A (ja) * 2001-03-22 2002-09-27 Hitachi Chem Co Ltd はんだボールを有する配線板とその製造方法
US6902098B2 (en) * 2001-04-23 2005-06-07 Shipley Company, L.L.C. Solder pads and method of making a solder pad
US6737353B2 (en) * 2001-06-19 2004-05-18 Advanced Semiconductor Engineering, Inc. Semiconductor device having bump electrodes
JP2003037133A (ja) * 2001-07-25 2003-02-07 Hitachi Ltd 半導体装置およびその製造方法ならびに電子装置
JP3615206B2 (ja) * 2001-11-15 2005-02-02 富士通株式会社 半導体装置の製造方法
TW578244B (en) * 2002-03-01 2004-03-01 Advanced Semiconductor Eng Underball metallurgy layer and chip structure having bump
JP2003338516A (ja) * 2002-05-20 2003-11-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3851320B2 (ja) * 2004-03-25 2006-11-29 Ｔｄｋ株式会社 回路装置及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164224A (ja) * 1986-12-26 1988-07-07 Furukawa Electric Co Ltd:The 電気接続用テ−プ状リ−ド
US6798050B1 (en) * 1999-09-22 2004-09-28 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor element with copper pad mounted on wiring substrate and method for fabricating the same
US20020121709A1 (en) * 2000-12-28 2002-09-05 Fujitsu Limited External connection terminal and semiconductor device
US6945447B2 (en) * 2002-06-05 2005-09-20 Northrop Grumman Corporation Thermal solder writing eutectic bonding process and apparatus
US20050224981A1 (en) * 2004-04-08 2005-10-13 Nishant Sinha Semiconductor processing methods for forming electrical contacts
WO2006040847A1 (ja) * 2004-10-14 2006-04-20 Ibiden Co., Ltd. プリント配線板及びプリント配線板の製造方法

Also Published As

Publication number Publication date
EP2100328A4 (en) 2011-12-07
TW201330206A (zh) 2013-07-16
KR20090103911A (ko) 2009-10-01
WO2008073807A1 (en) 2008-06-19
TW200836313A (en) 2008-09-01
EP2100328A1 (en) 2009-09-16
CN101632160B (zh) 2012-06-13
US20080136019A1 (en) 2008-06-12
CN101632160A (zh) 2010-01-20

Similar Documents

Publication Publication Date Title
TWI484608B (zh) 高溫應用所用之銲錫凸塊／凸塊下金屬層結構
JP6352205B2 (ja) 銅柱バンプ上の金属間化合物の接合のための構造
JP4195886B2 (ja) 無鉛はんだを用い反応バリア層を有するフリップ・チップ用相互接続構造を形成するための方法
JP5604665B2 (ja) 銅の追加によるハンダ相互接続の改良
KR100772920B1 (ko) 솔더 범프가 형성된 반도체 칩 및 제조 방법
JP5208500B2 (ja) 組込方法及びこの方法により製造されたアセンブリ
US20040238955A1 (en) Semiconductor device and method of fabricating the same
US20030222352A1 (en) Under-bump metallugical structure
JP2008500181A (ja) はんだの組成物、及びはんだ接続部を製造する方法
CN109755208B (zh) 一种接合材料、半导体装置及其制造方法
JP2008543035A (ja) Ｕｂｍパッド、はんだ接触子及びはんだ接合方法
WO2007097508A1 (en) Semiconductor chip with solder bump suppressing growth of inter-metallic compound and method of frabricating the same
US20090020871A1 (en) Semiconductor chip with solder bump suppressing growth of inter-metallic compound and method of fabricating the same
US20050012211A1 (en) Under-bump metallugical structure
JP2007123577A (ja) 半導体装置
JP2012190939A (ja) 半導体装置およびその製造方法
US11552042B2 (en) Solder material with two different size nickel particles
JP4726409B2 (ja) 半導体素子及びその製造方法
TWI450347B (zh) 銲線接合結構

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees