TWI470793B - 半導體裝置及其製造方法，以及電源供應器 - Google Patents

半導體裝置及其製造方法，以及電源供應器 Download PDF

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Publication number
TWI470793B
TWI470793B TW100145911A TW100145911A TWI470793B TW I470793 B TWI470793 B TW I470793B TW 100145911 A TW100145911 A TW 100145911A TW 100145911 A TW100145911 A TW 100145911A TW I470793 B TWI470793 B TW I470793B
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Taiwan
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nitride semiconductor
semiconductor layer
layer
type nitride
forming
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TW100145911A
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TW201324771A (zh
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Atsushi Yamada
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Transphorm Japan Inc
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    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Description

半導體裝置及其製造方法，以及電源供應器
本文中揭示之實施例係關於半導體裝置及其製造方法，以及電源供應器。
氮化物半導體裝置係以其較高飽和電子速度和較寬能帶間隙為特徵。已經已有藉由利用此等特性積極發展出具有較高電耐壓和較高輸出之裝置。
尤其是，使用於此種具有較高電耐壓和較高輸出之裝置之氮化物半導體裝置之一種類型為場效電晶體，尤其是，高電子遷移率電晶體(high electron mobility transistor,HEMT)。
舉例而言，有一種包含HEMT結構之GaN-HEMT，其中AlGaN供應層堆疊在GaN電子中轉層上。於GaN-HEMT中，由於AlGaN與GaN之晶格常數差，而於AlGaN中產生應變(strain)，該應變誘發壓電極化(piezo polarization)。藉由AlGaN之壓電極化和自發極化(spontaneous polarization)產生較高密度二維電子氣體(two-dimensional electron gas,2DEG)。於此種方式，GaN-HEMT可以提供具有較高電耐壓和較高輸出之裝置。
亦已經發展各種技術實現於提供較高密度2DEG之GaN-HEMT中常閉型操作(normally-off operation)。
舉例而言，有一種蝕刻在閘電極正下方之電子供應層之技術實現常閉型操作。以下將該技術稱為第一種技術。
或可取而代之，(有意注入載子)在有意注入載子觀點上具有根據全然不同於接面場效電晶體(JFET)原理操作之裝置。具體而言，於裝置中另外一種技術藉由僅在閘電極正下方設置具有p型導電率之半導體層而實現常閉型操作。下文中，此技術稱之為第二種技術。另一種的技術提供氮化物半導體層，該氮化物半導體層在閘電極正下方包含具有p型導電率區域，同時於其餘的區域設置高電阻區域。於此種技術中，將氫阻障膜或氫擴散膜設置在該較高電阻區域上。下文中，此技術稱之為第三種技術。
然而，於以上說明之上述第一種技術中，蝕刻會在通道區域的附近引致損害，該損害於通道區域增加電阻和漏電流。
於上述第二種技術中，需要藉由蝕刻等方法去除具有p型導電率形成在閘極電極正下方以外之區域中之半導體層。此方法引致於通道區域附近之損害，導致於通道區域中增加電阻。
依照實施例之一個態樣，本半導體裝置及電源供應器包含含有載子中轉層(carrier transit layer)和載子供應層之氮化物半導體堆疊結構；設置在該氮化物半導體堆疊結構上並且包含主動區域和非主動區域之p型氮化物半導體層；設置在該p型氮化物半導體層中之該非主動區域上之n型氮化物半導體層；以及設置在該p型氮化物半導體層中該主動區域上之閘極電極。
依照實施例之另一個態樣，本製造半導體裝置之方法包含形成含有載子中轉層和載子供應層之氮化物半導體堆疊結構；形成p型氮化物半導體層在該氮化物半導體堆疊結構之上；形成n型氮化物半導體層在該p型氮化物半導體層上；去除部分之該n型氮化物半導體層；藉由實施熱處理形成主動區域於該p型氮化物半導體層之一部分；以及形成閘極電極在該p型氮化物半導體層中之該主動區域上。
上述第三種技術於通道區域中維持低電阻具有困難。
因此，希望達成於通道區域中常閉型操作同時維持低電阻。
下文中，將參照圖式說明依照實施例之半導體裝置和製造該半導體裝置之方法，以及電源供應器。
[第一個實施例]
現在將參照第1至5D圖說明依照第一個實施例之半導體裝置和製造該半導體裝置之方法。
依照第一個實施例之半導體裝置為化合物半導體裝置，尤其是，使用氮化物半導體裝置之具有較高電耐壓和較高輸出之裝置。應該注意的是此種半導體裝置亦稱之為氮化物半導體裝置。
再者，此種半導體裝置包含使用氮化物半導體材料之場效電晶體。於本實施例中，半導體裝置包含接面場效電晶體(junction field-effect transistor)。應該注意的是此種電晶體亦稱之為氮化物半導體場效電晶體(nitride semiconductor field-effect transistor)。
具體而言，此實施例之半導體裝置包含使用GaN-系半導體材料並且達成常閉型操作之GaN-HEMT。應該注意的是此種裝置亦稱之為GaN-系半導體裝置。
如第1圖中所描繪，此實施例之半導體裝置包含氮化物半導體堆疊結構，其中核層2、i-GaN電子中轉層3、i-AlGaN間隔件層4、和n-AlGaN電子供應層5堆疊在半導體基板1上。
應該注意的是氮化物半導體堆疊結構亦稱之為化合物半導體堆疊結構、或GaN-HEMT結構、或AlGaN/GaN-HEMT結構、或GaN-HEMT結晶。電子中轉層亦稱之為載子中轉層。電子供應層亦稱之為載子供應層。
尤其是，於此半導體裝置中，p-GaN層6和n-GaN層7設置在如上述列出之氮化物半導體堆疊結構上。
於此種實施例中，p-GaN層6為摻雜有例如是Mg之p型雜質之GaN層，並且包含主動區域(活性化區域(activated region))10，於此區域中p型雜質被活性化；和除了主動區域10之外之區域，亦即，非主動區域10A，於此區域中p型雜質藉由加入氫而被減活。換言之，於p-GaN層6中，p型雜質被部分活性化。於是，於p-GaN層6中主動區域10為具有固定電荷之區域，而非主動區域10A為沒有固定電荷之區域。換言之，於p-GaN層6中之主動區域10為展現p型導電率之區域。應該注意的是p-GaN層6亦稱之為p型氮化物半導體層。於p-GaN層6中之非主動區域10A亦稱之為i-GaN層，因為非主動區域10A不展現導電率並且具有相當於能帶結構中未摻雜GaN層能階之能階(energy level)。
n-GaN層7為一種摻雜有n型雜質之GaN層，並且設置在p-GaN層6中之非主動區域10A上。反之，沒有n-GaN層7設置於p-GaN層6中主動區域10上。換言之，n-GaN層7覆蓋p-GaN層6中之非主動區域10A，而不覆蓋p-GaN層6中之主動區域10。應該注意的是n-GaN層7亦稱之為n型氮化物半導體層。
上述之氮化物半導體層結構進一步包含在氮化物半導體堆疊結構之上之源極電極11、汲極電極12、和閘極電極13。於本實施例中，源極電極11和汲極電極12設置在n-AlGaN電子供應層5上。閘極電極13設置在p-GaN層6中之主動區域10上。此處，於p-GaN層6中之主動區域10與閘極電極13形成彼此肖特基接觸(Schottky-contact)(肖特基接面)。雖然未顯示，但是表面被用例如像是SiN膜之鈍化膜覆蓋，並且亦設有互連接、焊墊、等等。
如上述說明，此實施例之半導體裝置包含在氮化物半導體堆疊結構之通道區域之上之p-GaN層6，亦即，電子(載子)通行區域，以及閘極電極13設置在p-GaN層6之主動區域10上。於此種結構中，p-GaN層6於閘極電極13下方之區域中被耗盡，以及如第2A圖和2B圖中所描繪，此能帶由p-GaN層6中之固定電荷(-)所提升。結果，於AlGaN/GaN-HEMT結構中GaN層與AlGaN層之間之介面中導電帶之能階EC超過費米能階(Fermi level)EF ，抑制2DEG之產生，由此達成常閉型操作。應該注意的是，第2A圖例示於AlGaN/GaN-HEMT結構中之GaN與AlGaN層之能帶結構，表示由於發生於AlGaN層之壓電極化和自發極化導致較高密度2DEG產生於GaN層與AlGaN層之間之介面中。
反之，除了主動區域10外之p-GaN層6中之區域10A不被活性化，而n-GaN層7設置在非活性化區域(非主動區域)10A上。更具體而言，於p-GaN層6中之非活性化區域10A系設置在汲極電極12與閘極電極13之間、以及源極電極11與閘極電極13之間之通道區域之上，而n-GaN層7係設置在非活性化區域10A上。
現將討論採用此種結構之理由。
更具體而言，於p-GaN層6中之非活性化區域10A，亦即，展現在AlGaN/GaN-HEMT結構之上之i-GaN層將升高能帶，如第2A和2C圖中所描繪。此情況增加汲極電極12與閘極電極13之間、以及源極電極11與閘極電極13之間通道區域中之電阻。此情況導致裝置性能之劣化。因此，將n-GaN層7設置在p-GaN層6中之非活性化區域10A上，亦即，i-GaN層上，以降低能帶，如第2C和3圖中所描繪。更具體而言，由展現於AlGaN/GaN-HEMT結構上i-GaN層所提升之能帶藉由於耗竭之n-GaN層7中之固定電荷(+)而下降。由此，於AlGaN/GaN-HEMT結構中於GaN層與AlGaN層之間之介面中導電帶中能階EC 變成相當於無p-GaN層6和n-GaN層7之AlGaN/GaN-HEMT結構之能階(參看第2A圖)。此情況使得可以維持於汲極電極12與閘極電極13之間、以及源極電極11與閘極電極13之間之通道區域中之低電阻。
如上所述，藉由於汲極電極12與閘極電極13之間、和源極電極11與閘極電極13之間之p-GaN層6中之非活性化區域10A上設置n-GaN層7，因此可以維持通道區域之低電阻。換言之，p-GaN層6和n-GaN層7之設置使得常閉型操作能成立，而不會劣化裝置性能。
如將於後文中說明，取決於在半導體裝置製程期間於p-GaN層6中形成主動區域10，n-GaN層7運作為用來防止從其餘區域中p-GaN層6氫脫附之薄膜。此意味著n-GaN層7用於維持於通道區域中之低電阻，以及抑制氫脫附薄膜之動作與功能。
如上所述，p-GaN層6和n-GaN層7堆疊於其上之氮化物半導體堆疊結構定義一個整體之氮化物半導體堆疊結構，包含p-GaN層6和n-GaN層7。於此種結構中，因為氮化物半導體堆疊結構之表面位於更遠離通道區域，亦可以抑制電流崩塌現象。
再者，如將於後文中說明，對於p-GaN層6中部分活性化之p型雜質，用光電化學蝕刻形成開口於n-GaN層7中，該光電化學蝕刻使得能夠製造高品質裝置而沒有損害於通道區域附近。或可取而代之，如果用乾蝕刻形成開口於n-GaN層7附近，則也許損害p-GaN層6。然而，因為p-GaN層6遠離通道區域，因此於裝置特徵之衝擊低，並且仍然可以維持於通道區域中之低電阻。
如上述說明，於本實施例中，設置在氮化物半導體堆疊結構上之p型氮化物半導體層和n型氮化物半導體層為包含相同氮化物半導體材料之GaN層6和7。於是，減少結晶缺陷，其亦有助於達成高品質裝置。
其次，將參照第4A至4C圖和第5A至5D圖說明依照此實施例製造半導體裝置之方法。
初始，如第4A圖中所描述，在半絕緣SiC基板1之上用例如金屬有機氣相磊晶(MOVPE)等依序形成核層2、i-GaN電子中轉層3、i-AlGaN間隔件層4、n-AlGaN電子供應層5、p-GaN層6、和n-GaN層7。
更具體而言，將包含核層2、i-GaN電子中轉層3、i-AlGaN間隔件層4、和n-AlGaN電子供應層5之氮化物半導體堆疊結構(GaN-HEMT結晶)形成在半絕緣SiC基板1之上。隨後，p-GaN層6形成在氮化物半導體堆疊結構上，接著形成n-GaN層7於p-GaN層6上。於此種方式，依序形成氮化物半導體堆疊結構，p-GaN層6、和n-GaN層7。再者，因為形成在氮化物半導體堆疊結構上之p型氮化物半導體層和n型氮化物半導體層為包含於此實施例中相同氮化物半導體材料之GaN層6和7，因此結晶缺陷減少，由此達成高品質裝置。
此處，i-GaN電子中轉層3具有例如大約3 μm之厚度。i-AlGaN間隔件層4具有例如大約5nm之厚度。n-AlGaN電子供應層5具有例如大約30 nm之厚度，其中使用例如Si為n型雜質，具有例如大約5×1018 cm-3 之摻雜濃度。p-GaN層6具有例如大約50 nm之厚度，其中使用例如Mg為p型雜質，具有例如大約2×1019 cm-3 之摻雜濃度。n-GaN層7具有例如大約10 nm之厚度，其中使用例如Si為n型雜質，具有例如大約5×1018 cm-3 之摻雜濃度。
其次，形成SiO2 膜8在晶圓之整個表面上，亦即，用例如濺鍍法在n-GaN層7之表面之上。接著，形成光阻遮罩(未顯示)，該光阻遮罩於位於用例如光學微影術待形成閘極電極區域(下文中，稱之為“閘極電極形成區域”)之下方之區域具有開口。去除位於閘極電極形成區域下方區域中之SiO2 膜8，如第4B圖中所描繪。於是，在n-GaN層7上形成SiO2 膜8，該SiO2 膜在位於閘極電極形成區域下方之區域中具有開口。於此製程，亦去除已經形成在整個表面上SiO2 膜8(未顯示)之周邊之一部分。
接著，使用SiO2 膜8作為遮罩去除n-GaN層7之一部分。更具體而言，去除位於閘極電極形成區域下方之區域中n-GaN層7。此情況提供於位於閘極電極形成區域下方之區域中具有開口之n-GaN層7。
於本實施例中，用光電化學(PEC)蝕刻選擇性地僅去除n-GaN層7。於此蝕刻期間，電極連接至暴露於晶圓週邊之n-GaN層7，而將該晶圓浸入於氫氧化鉀(KOH)溶液中，同時施加紫外線輻射。該紫外線輻射具有短於對應於GaN之帶隙之波長之波長。結果，於GaN中產生電洞對(electron-hole pairs)。電子藉由施加偏壓而被吸引，並且剩餘之電洞遷移朝向GaN之表面。藉由於KOH水溶液中與OH- 離子反應氧化和分解作用之重複循環而蝕刻GaN之表面。於此種方式，因為僅有n-GaN層7被選擇性地去除而沒有對p-GaN層6造成任何損害，因此達成高品質通常是關閉的類型之裝置(通常是關閉類型之GaN-HEMT)而於通道區域之附近沒有任何的損害。
雖然於上述例子中n-GaN層7用光電化學蝕刻去除，但是並不限制於此種方式。舉例而言，可以用乾蝕刻去除n-GaN層7。於此情況，也許損害p-GaN層6。然而，因為p-GaN層6遠離通道區，因此於裝置特性的影響低，並且仍能維持於通道區域低電阻。
隨後，SiO2 膜(保護膜)9例如用濺鍍形成在晶圓之整個表面上，亦即，於位於閘極電極形成區域下方、n-GaN層7之側、和SiO2 膜8之表面之區域之p-GaN層6表面，如第4C圖所示。換句話說，整個表面用SiO2 膜9覆蓋。
在熱處理用來定義稍後將說明之主動區域10之前，藉由用SiO2 膜9作為保護膜覆蓋p-GaN層6和n-GaN層7之表面，防止於熱處理期間從GaN氮氣之解吸(desorption)(蒸發)。因此，SiO2 膜9作為保護膜亦稱之為氮解吸禁止膜。因為SiO2 膜9滲透氫氣，因此其不作為氫解吸禁止膜。
隨後，實施熱處理，以使p-GaN層6(亦即，於位於閘極電極形成區域下方區域中之p-GaN層6)之部分中之p型雜質(此處，為鎂)活性化，由此定義於p-GaN層6之部分中之主動區域10。值得注意的是此種熱處理亦稱之為雜質活性化處理。
舉例而言，於氮氣環境中實施大約600℃至1000℃之間(例如，大約750℃)之熱處理，以使位於閘極電極形成區域下方區域中之p-GaN層6中之p型雜質活性化，由此定義於p-GaN層6中之主動區域10。
如上述說明，形成在p-GaN層6上之n-GaN層7於位於閘極電極形成區域下方區域中具有開口。更具體而言，於位於閘極電極形成區域下方區域中之p-GaN層6不被n-GaN層7所覆蓋，而其他區域則用n-GaN層7覆蓋。值得注意的是於p-GaN層6中之p型雜質(此處，為鎂)由於氫之存在而非活性，該氫氣於形成p-GaN層6時即已被包含。
當此種結構經歷熱處理時，n-GaN層7防止氫從由n-GaN層7覆蓋之區域中之p-GaN層6解吸，亦即，防止於非位於閘極電極形成區域下方區域中之p-GaN層6氫解吸。結果，摻雜至p-GaN層6之p型雜質未於用n-GaN層7覆蓋之區域中被活性化，並且保持非活性。反之，來自p-GaN層6和摻雜至p-GaN層6之p型雜質之氫解吸於未用n-GaN層7覆蓋之區域，亦即，於位於閘極電極形成區域下方區域中之p-GaN層6之區域被活性化。如上述說明，藉由用n-GaN層7覆蓋非位於閘極電極形成區域下方區域中之p-GaN層6，僅僅摻雜至位於閘極電極形成區域下方區域中之p-GaN層6之p型雜質可以被選擇性地活性化。更具體而言，藉由用n-GaN層7覆蓋非位於閘極電極形成區域下方區域中之p-GaN層6，主動區域10僅被定義於位於閘極電極形成區域下方區域中之p-GaN層6，同時定義其他區域為非主動(非活性化)區域10A。於此情況，n-GaN層7作用為用來防止氫從p-GaN層6解吸之薄膜，或者用來防止p-GaN層6之活性化之薄膜。因此，n-GaN層7亦稱之為氫解吸禁止膜(hydrogen desorption inhibition film)或活性化禁止膜(activation inhibition film)。
於實施如上述之熱處理後，用例如濕蝕刻去除SiO2 膜8、9，如第5A圖中所描繪。
隨後，雖然未顯示，用例如光學微影術形成於元件隔離區中具有開口之光阻遮罩，並且用例如氯系氣體之乾蝕刻、或離子植入，使用此遮罩建立元件隔離。
隨後，用例如光學微影術形成於將形成源極和汲極之區域中具有各自開口之光阻遮罩(未顯示)。然後，使用此光阻遮罩用例如氯系氣體之乾蝕刻，去除於將形成源極和汲極電極區域中之p-GaN層6和n-GaN層7，如第5B圖中所描繪。
隨後，用例如光學微影術和蒸發和剝離(lift-off)技術，將源極電極11和汲極電極12分別形成在待形成源極和汲極電極之區域，如第5C圖中所描繪。更具體而言，於n-AlGaN電子供應層5上，藉由依序堆疊Ta和Al而形成由Ta/Al層製成之源極電極11和汲極電極12。於此實施例中，Ta之厚度例如可能大約20nm，而Al之厚度例如可能大約200 nm。其後，例如於氮氣環境中藉由實施大約400℃與大約1000℃之間(例如，於550℃)之熱處理而建立歐姆接觸特性。
隨後，用例如光學微影術和蒸發和剝離技術，將閘極電極13形成在閘極電極形成區域，如第5D圖中所描繪。更具體而言，於p-GaN層6中主動區域10上，藉由依序堆疊Ni和Au而形成由Ni/Al製成之閘極電極13。於此實施例中，Ni之厚度例如可能大約30 nm，而Au之厚度例如可能大約400 nm。於上述製程中，形成閘極電極13肖特基接觸至在p-GaN層6中之主動區域10。於此種方式，可以藉由形成閘極電極13於p-GaN層6中主動區域10上而達成常閉型操作。
其後，雖然未顯示，表面用例如是SiN膜之鈍化膜覆蓋，並且亦形成互連接、焊墊、等等以製造半導體裝置(GaN-HEMT)。
如上述說明，依照此實施例之半導體裝置和製造該半導體裝置之方法具有優點在於可以達成通常是關閉的操作同時於通道中保持低電阻。
雖然於上述實施例中p-GaN層6和n-GaN層7設置在氮化物半導體堆疊結構上，但是並不限制於此種方式。任何適合的p型氮化物半導體層和n型氮化物半導體層可以設置在氮化物半導體堆疊結構之上。此處，p型氮化物半導體層可以是包含GaN、AlN或InN結晶，或者他們的混合結晶之任何適當的層，而n型氮化物半導體層可以是包含GaN、AlN或InN結晶，或者他們的混合結晶之任何適當的層。舉例而言，p型氮化物半導體層可以是包含譬如AlGaN、InAlN、InGaN、InN、和AlInGaN之氮化物半導體材料。再者，n型氮化物半導體層可以是包含譬如AlGaN、InAlN、InGaN、InN、和AlInGaN之氮化物半導體材料之任何適當的層。當p型氮化物半導體層和n型氮化物半導體層包含相同的氮化物半導體材料時，結晶缺陷減少，其減少電阻和電流崩潰，由此達成高品質裝置。
再者，雖然於上述實施例中閘極電極13形成在p-GaN層6中主動區域10上，但是並不限制於此種方式。閘極電極13可以設置在主動區域10上。更具體而言，上述實施例已說明於接面場效電晶體中，於此接面場效電晶體中閘極電極13肖特基接觸至p-GaN層6中主動區域10，但是並不限制於此種方式。舉例而言，如第6圖中所描繪，實施例可以組構為金屬絕緣半導體(MIS)型場效電晶體，其中閘極絕緣膜14設置在閘極電極13與p-GaN層6中主動區域10之間。於第6圖中，對與於上述實施例(參看第1圖)中那些相同的元件附註相同的參考符號。
對於MIS型場效電晶體，於依照上述實施例之製造半導體裝置之方法中，於形成源極電極11和汲極電極12並且實施熱處理用來建立歐姆接觸特性之後，於形成閘極電極13之前，可以形成閘極絕緣膜14。
舉例而言，閘極絕緣膜14可以形成在晶圓之整個表面上，亦即，於p-GaN層6中主動區域10之表面、n-GaN層7之表面、和源極電極11與汲極電極12之表面。然後，可以以上述實施例相似之方式形成閘極電極在閘極絕緣膜14之表面。
應該注意的是，閘極絕緣膜14可以具有例如從大約2 nm至大約200 nm，例如，大約10 nm之厚度。再者，可以用例如ALD、電漿CVD、和濺鍍技術形成閘極絕緣膜14。舉例而言，Si、Al、Hf、Zr、Ti、Ta、和W之氧化物、氮化物、或氧氮化物可以使用為用於閘極絕緣膜14之金屬。舉例而言，閘極絕緣膜14可以是AlO膜。
再者，氮化物半導體堆疊結構並不限制於上述實施例中之該種樣式，而是亦可以使用任何其他的氮化物半導體堆疊結構，只要該氮化物半導體堆疊結構包含載子中轉層和載子供應層即可。舉例而言，可以使用可以用來構造場效電晶體，譬如使用氮化物半導體場效電晶體之氮化物半導體堆疊結構。舉例而言，氮化物半導體堆疊結構之材料可以使用包含GaN、AlN或InN結晶，或者他們的混合結晶之任何材料。應該注意的是氮化物半導體堆疊結構亦稱之為半導體磊晶結構(semiconductor epitaxial structure)。
再者，雖然上述實施例中使用SiC，但是並不限制於此種方式。舉例而言，亦可以使用其他的半導體基板，譬如藍寶石基板(sapphire substrate)、Si基板、和GaN基板。再者，雖然上述實施例中使用半絕緣SiC基板，但是並不限制於此種方式。舉例而言，亦可以使用具有n型或p型導電率之基板。
再者，於上述實施例中源極、汲極、和閘極電極之層結構並不受限於上述實施例中特定的層結構，而是亦可以使用其他的層結構。舉例而言，於上述實施例中源極、汲極、和閘極電極之層結構可以為單層或多層。再者，形成源極、汲極、和閘極電極之技術僅為範例，亦可以使用任何其他的技術。
再者，舉例而言，於上述實施例中雖然實施熱處理用來建立源極和汲極電極之歐姆接觸特性，但是並不限制於此種方式。可以省略用來建立源極和汲極電極之歐姆接觸特性之熱處理，只要能夠建立源極和汲極電極之歐姆接觸特性而沒有熱處理亦無妨。再者，雖然於上述實施例中閘極電極沒有經過熱處理，但是可以於閘極電極上施行熱處理。
[第二個實施例]
接著，茲參照第7和8圖說明依照第二個實施例之半導體裝置和製造該半導體裝置之方法。
依照本實施例之半導體裝置為一種包含依照上述第一個實施例和其變形之任何其中一種半導體裝置(GaN-HEMT)(如半導體晶片)之半導體封裝件。應該注意的是，此種半導體晶片亦稱之為HEMT晶片。
下文中，將參照分離的封裝件作為範例，說明本實施例。
如第7圖中所描繪，此種半導體裝置包含依照上述第一個實施例和其變異之任何其中一種安裝半導體晶片14之台片(stage)30、閘極引線17、源極引線19、汲極引線18、銲線16(於此實施例中為鋁線)、和封裝樹脂20。應該注意的是，封裝樹脂亦稱之為成型樹脂。
於安裝於台片30上之此種半導體晶片14中閘極焊墊31、源極焊墊32、和汲極焊墊33透過鋁線分別連接至閘極引線17、源極引線19、和汲極引線18，然後經過樹脂封裝。
於此實施例中，於半導體晶片14中基板之背面用晶粒附接材料15(於此實施例中為銲料)與之固接之台片30電性連接至汲極引線18。應該注意的是，組構並不限制於上述之其中一種，而台片30可以電性連接至源極引線19。
其次，將說明依照本實施例製造半導體裝置(分離的封裝件)之方法。
首先，將依照上述第一個實施例和其變形之任何其中一種半導體晶片14(GaN-HEMT)用例如晶粒附接材料15(於此實施例中為銲料)固接於引線框之台片30上。
接著，於此半導體晶片14中閘極銲墊31、汲極銲墊33、和源極銲墊32例如透過鋁線16黏接而分別連接至閘極引線17、汲極引線18、和源極引線19。
於使用例如轉換模具技術而樹脂封裝後，重複該引線框。
本實施例(分離的封裝件,discrete package)之半導體裝置可以依上述步驟製造。
雖然已經參照分離的封裝件說明此實施例，其中於半導體晶片14中將銲墊31-33用作為黏接銲墊而用於此實施例中導線黏接，但是並不限制於此種方式，而是亦可以使用其他的半導體封裝件。舉例而言，可以使用其中於半導體晶片中將銲墊使用為用於無線銲接(wireless bonding)，例如是覆晶銲接(flip chip bonding)之銲墊之半導體封裝件。亦可以使用晶圓層級封裝(wafer level package)。或可取而代之，亦可以使用分離封裝件以外的半導體封裝件。
其次，將參照第8圖說明包含上述GaN-HEMT之含有分離的封裝件之電源供應裝置。
下文中，將參照範例說明實施例，於此實施例中包含於上述半導體封裝件中之GaN-HEMT(參看第1圖)使用於設於用於伺服器之電源供應裝置中之功率因素校正(power factor correction,PFC)電路中。
如第8圖中所描繪，此PFC電路包含二極體橋26、扼流線圈(choke coil)22、第一電容器24、包含於上述半導體封裝件中之GaN-HEMT 21、二極體23、和第二電容器25。
於此實施例中，此PFC電路係組構成包含安裝於電路基板上之二極體橋26、扼流線圈22、第一電容器24、包含於上述半導體封裝件中之GaN-HEMT 21、二極體23、和第二電容器25。
於本實施例中，於上述半導體封裝件中之汲極引線18、源極引線19、和閘極引線17係分別插入於電路基板上之汲極引線槽、源極引線槽、和閘極引線槽中，然後用例如銲料固接。於此種方式，包含於上述半導體封裝件中之GaN-HEMT 21連接至形成在電路基板上之PFC電路。
於此PFC電路中，扼流線圈22之一端和第二電容器25之陽極端連接至GaN-HEMT 21中之汲極電極D。第一電容器24之一端連接至扼流線圈22之另一端，而第二電容器25之一端連接至二極體23之陰極端。第一電容器24之另一端、於GaN-HEMT 21中之源極電極S和第二電容器25之另一端接地。二極體橋26之一對端子連接至第一電容器24之二個端子，而二極體橋26之另一對端子連接至輸入端用以接收交流(AC)電壓。第二電容器25之二個端子連接至輸出端用以輸出直流(DC)電壓。閘極驅動器(未顯示)連接至GaN-HEMT 21中之閘極電極G。於此PFC電路中，藉由由閘極驅動器使該GaN-HEMT 21活性化，將透過輸入端接收之AC電壓轉換成DC電壓，而將該DC電壓從輸出端輸出。
因此，依照本實施例之電源供應裝置具有改善可靠度之優點。更具體而言，因為此電源供應裝置具有依照上述第一個實施例和其變形之任何其中一種之半導體晶片56，因此可以建構可靠的電源供應裝置。
雖然已經說明了上述實施例，於該實施例中上述的半導體裝置(GaN-HEMT或包含GaN-HEMT之半導體封裝件)係使用於設置在用於伺服器之電源供應裝置中之PFC電路中，但是並不限制於此種方式。舉例而言，上述的半導體裝置(GaN-HEMT或包含GaN-HEMT之半導體封裝件)亦可以使用於譬如非伺服器電腦之電子家電(電子器具)中。或可取而代之，上述之半導體裝置(半導體封裝件)亦可以使用於設置在電源供應裝置中之其他的電路。
本說明書中所引述之所有的實例和條件語言係意欲用於教學目的幫助讀者了解本發明和由發明人提供以推動此技術之概念，並且將被解釋為此情況但是不限制於此情況。例如，引述的實例和狀況，於此說明書中此等實例之組構不相關於說明本發明之優越性和缺失性。雖然已經詳細說明本實施例，但是應該了解本發明可以作各種的變化、替代、和改變而不會偏離本發明之精神和範圍。
1．．．半導體基板(半絕緣SiC基板)
2．．．核層
3．．．i-GaN電子中轉層(載子中轉層)
4．．．i-AlGaN間隔件層
5．．．n-AlGaN電子供應層(載子供應層)
6．．．p-GaN層(p型氮化物半導體層)
7．．．n-GaN層(n型氮化物半導體層)
8、9．．．SiO2 膜(活性化區域)
10．．．主動(活性化)區域
10A．．．非主動區域(非活性化區域)
11．．．源極電極
12．．．汲極電極
13．．．閘極電極
14．．．閘極絕緣膜(半導體晶片)
15．．．晶粒附接材料
16．．．銲線(鋁線)
17．．．閘極引線
18．．．汲極引線
19．．．源極引線
20．．．封裝樹脂
21．．．GaN-HEMT
22．．．扼流線圈
23．．．二極體
24．．．第一電容器
25．．．第二電容器
26．．．二極體橋
30．．．台片
31．．．閘極銲墊
32．．．源極銲墊
33．．．汲極銲墊
56．．．半導體晶片
第1圖為例示依照第一個實施例半導體裝置(GaN-HEMT)之結構之示意剖面圖；
第2A圖為AlGaN/GaN-HEMT之能帶結構輪廓；
第2B圖為p-GaN層(具有p型導電率之GaN層)設置在閘極電極正下方AlGaN層上之能帶結構輪廓；
第2C圖為i-GaN層出現在閘極電極正下方以外區域上(亦即，在通道區域上)之能帶結構輪廓；
第3圖為依照第一個實施例半導體裝置(GaN-HEMT)之能帶結構輪廓；
第4A至4C圖為例示製造依照第一個實施例半導體裝置(GaN-HEMT)之方法之示意剖面圖；
第5A至5D圖為例示製造依照第一個實施例半導體裝置(GaN-HEMT)之方法之示意剖面圖；
第6圖為例示依照第一個實施例之變體之半導體裝置(GaN-HEMT)之結構之示意剖面圖；
第7圖為例示依照第二個實施例半導體裝置(半導體層封裝件)之結構之示意平面圖；以及
第8圖為例示依照第二個實施例包含於電源供應器中PFC電路之結構之示意圖。
1．．．半導體基板(半絕緣SiC基板)
2．．．核層
3．．．i-GaN電子中轉層(載子中轉層)
4．．．i-AlGaN間隔件層
5．．．n-AlGaN電子供應層(載子供應層)
6．．．p-GaN層(p型氮化物半導體層)
7．．．n-GaN層(n型氮化物半導體層)
10．．．主動(活性化)區域
10A．．．非主動區域(非活性化區域)
11．．．源極電極
12．．．汲極電極
13．．．閘極電極

Claims (20)

  1. 一種半導體裝置，包括：包括載子中轉層和載子供應層之氮化物半導體堆疊結構；設置在該氮化物半導體堆疊結構上並且包括活性化區域和非活性化區域之p型氮化物半導體層；設置在該p型氮化物半導體層中之該非活性化區域上之n型氮化物半導體層；以及設置在該p型氮化物半導體層中該活性化區域上之閘極電極。
  2. 如申請專利範圍第1項所述之半導體裝置，其中，該活性化區域為具有固定電荷之區域，而該非活性化區域為沒有固定電荷之區域。
  3. 如申請專利範圍第1項或第2項所述之半導體裝置，其中，該p型氮化物半導體層和該n型氮化物半導體層包含相同的氮化物半導體材料。
  4. 如申請專利範圍第1項或第2項所述之半導體裝置，其中，該p型氮化物半導體層包含GaN、AlN或InN結晶，或他們的混合結晶，而n型氮化物半導體層包含GaN、AlN或InN結晶，或他們的混合結晶。
  5. 如申請專利範圍第1項或第2項所述之半導體裝置，其中，該p型氮化物半導體層為p型GaN層，而該n型氮化物半導體層為n型GaN層。
  6. 如申請專利範圍第1項或第2項所述之半導體裝置，其中，於該p型氮化物半導體層中之該活性化區域與該閘極電極肖特基接觸。
  7. 如申請專利範圍第1項或第2項所述之半導體裝置，進一步包括於該p型氮化物半導體層中該活性化區域與該閘極電極之間之閘極絕緣膜。
  8. 如申請專利範圍第1項或第2項所述之半導體裝置，其中，該氮化物半導體堆疊結構包含GaN、AlN或InN結晶，或他們的混合結晶。
  9. 一種半導體裝置，包括：安裝具有依照申請專利範圍第1項或第2項所述結構之半導體晶片之台片；連接至該半導體晶片中該閘極銲墊之閘極引線；連接至該半導體晶片中該源極銲墊之源極引線；連接至該半導體晶片中該汲極銲墊之汲極引線；以及封裝樹脂。
  10. 一種電源供應器裝置，包括依照申請專利範圍第1項或第2項所述之該半導體裝置。
  11. 一種半導體裝置之製造方法，包括下列步驟：形成包括載子中轉層和載子供應層之氮化物半導體堆疊結構；在該氮化物半導體堆疊結構之上形成p型氮化物半導體層；在該p型氮化物半導體層上形成n型氮化物半導體層；去除部分之該n型氮化物半導體層；藉由實施熱處理形成活性化區域於該p型氮化物半導體層之部分；以及在該p型氮化物半導體層中該活性化區域之上形成閘極電極。
  12. 如申請專利範圍第11項所述之半導體裝置之製造方法，其中，該去除部分之該n型氮化物半導體層之步驟包括用光電化學蝕刻去除該部分之該n型氮化物半導體層之步驟。
  13. 如申請專利範圍第11項或第12項所述之半導體裝置之製造方法，進一步包括：在形成活性化區域之前，先形成保護膜覆蓋該p型氮化物半導體層和該n型氮化物半導體層之表面之步驟；以及於形成該活性化區域後去除該保護膜之步驟。
  14. 如申請專利範圍第11項或第12項所述之半導體裝置之製造方法，其中，係連續形成該氮化物半導體堆疊結構、該p型氮化物半導體層、和該n型氮化物半導體層。
  15. 如申請專利範圍第11項或第12項所述之半導體裝置之製造方法，其中，該形成該n型氮化物半導體層之步驟包括使用與該p型氮化物半導體層之材料相同的材料形成該n型氮化物半導體層之步驟。
  16. 如申請專利範圍第11項或第12項所述之半導體裝置之製造方法，其中，該形成該p型氮化物半導體層之步驟包括形成包含GaN、AlN或InN結晶，或他們的混合結晶之p型氮化物半導體層之步驟，而該形成該n型氮化物半導體層之步驟包括形成包含GaN、AlN或InN結晶，或他們的混合結晶之n型氮化物半導體層之步驟。
  17. 如申請專利範圍第11項或第12項所述之半導體裝置之製造方法，其中，該形成該p型氮化物半導體層之步驟包括形成p型GaN層之步驟，而該形成該n型氮化物半導體層之步驟包括形成n型GaN層之步驟。
  18. 如申請專利範圍第11項或第12項所述之半導體裝置之製造方法，其中，該形成該閘極電極之步驟包括形成肖特基接觸至該p型氮化物半導體層中之該活性化區域之閘極電極之步驟。
  19. 如申請專利範圍第11項或第12項所述之半導體裝置之製造方法，進一步包括於形成該活性化區域之後和形成該閘極電極之前，形成閘極絕緣膜之步驟。
  20. 如申請專利範圍第11項或第12項所述之半導體裝置之製造方法，其中，該形成該氮化物半導體堆疊結構之步驟包括形成包含GaN、AlN或InN結晶，或他們的混合結晶之氮化物半導體堆疊結構之步驟。
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