WO2020215322A1 - 一种半导体结构及其制备方法 - Google Patents

一种半导体结构及其制备方法 Download PDF

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WO2020215322A1
WO2020215322A1 PCT/CN2019/084603 CN2019084603W WO2020215322A1 WO 2020215322 A1 WO2020215322 A1 WO 2020215322A1 CN 2019084603 W CN2019084603 W CN 2019084603W WO 2020215322 A1 WO2020215322 A1 WO 2020215322A1
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layer
type semiconductor
semiconductor layer
gate
gate structure
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PCT/CN2019/084603
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to CN201980095825.7A priority Critical patent/CN114072925B/zh
Priority to PCT/CN2019/084603 priority patent/WO2020215322A1/zh
Publication of WO2020215322A1 publication Critical patent/WO2020215322A1/zh
Priority to US17/510,558 priority patent/US20220052191A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the invention relates to the field of semiconductors, and in particular to a semiconductor structure and a preparation method thereof.
  • gallium nitride As a third-generation semiconductor material, gallium nitride has the characteristics of large forbidden band width, high electron saturation speed, and high two-dimensional electron gas concentration. It is considered an excellent material for the preparation of semiconductor devices, especially the AlGaN/GaN heterojunction structure. GaN-based electronic devices have a wide range of applications.
  • the current main methods are: 1. Etch grooves under the gate to improve gate control ability, but the etching accuracy is difficult Control, reduce the output current, affect the gain of the device; 2. Introduce a dielectric layer under the gate to reduce leakage, but as the device size decreases in proportion, the thinning of the dielectric layer will make the gate control ability weaker and weaker , The leakage is more serious; Third, the passivation layer is introduced to suppress current collapse, but the thickness of the passivation layer is not easy to control, too thick will introduce parasitic capacitance, resulting in degradation of the frequency characteristics of the device.
  • the present invention provides a semiconductor structure and a preparation method thereof to increase the threshold voltage of the device, while at the same time greatly reducing gate leakage, improving the output characteristics of the device and the control ability of the gate to the channel.
  • An embodiment of the present application provides a semiconductor structure, including:
  • a gate structure provided on the barrier layer wherein the gate structure includes a p-type semiconductor layer provided on the barrier layer, an n-type semiconductor layer provided on the p-type semiconductor layer, a device A gate on the n-type semiconductor layer, wherein the gate penetrates the n-type semiconductor layer, and the bottom of the gate is in contact with the p-type semiconductor layer.
  • the gate structure further includes a dummy layer provided between the p-type semiconductor layer and the barrier layer.
  • the semiconductor structure further includes: a nucleation layer and a buffer layer arranged between the substrate and the channel layer.
  • the semiconductor structure further includes: a source electrode and a drain electrode located on both sides of the gate structure.
  • An embodiment of the present application also provides a method for manufacturing a semiconductor structure, including:
  • a channel layer and a barrier layer are sequentially superposed and grown on the substrate;
  • a gate structure is prepared on the barrier layer, wherein the gate structure includes a p-type semiconductor layer provided on the barrier layer, an n-type semiconductor layer provided on the p-type semiconductor layer, and The gate on the n-type semiconductor layer, wherein the gate penetrates the n-type semiconductor layer, and the bottom of the gate is in contact with the p-type semiconductor layer.
  • the manufacturing process of the gate structure includes:
  • the p-type semiconductor layer and the n-type semiconductor layer on both sides of the gate are etched to form a gate structure.
  • the manufacturing process of the gate structure may further include:
  • the groove is etched from the side of the n-type semiconductor layer away from the p-type semiconductor layer.
  • the groove completely penetrates the n-type semiconductor layer and stops at the p-type semiconductor layer or completely penetrates the n-type semiconductor layer and partially penetrates the p-type semiconductor layer.
  • the p-type semiconductor layer and the n-type semiconductor layer on both sides of the gate are etched to form a gate structure.
  • the manufacturing process of the gate structure further includes:
  • the groove is etched from the side of the mask layer away from the n-type semiconductor layer.
  • the groove completely penetrates the mask layer, and the n-type semiconductor layer stops at the p-type semiconductor layer or completely penetrates the mask layer.
  • Type semiconductor layer partly through the p-type semiconductor layer;
  • the p-type semiconductor layer and the n-type semiconductor layer on both sides of the gate are etched to form a gate structure.
  • the gate structure further includes: forming a dummy layer between the p-type semiconductor layer and the barrier layer.
  • the preparation method of the semiconductor structure further includes: forming a nucleation layer and a buffer layer between the substrate and the channel layer.
  • the method for preparing the semiconductor structure further includes: preparing a source electrode and a drain electrode on both sides of the gate structure.
  • the semiconductor structure and the preparation method thereof provided by the present invention adopt a self-aligning process to improve the control ability of the gate to the channel; the entire gate structure is used to increase the threshold voltage of the device, and at the same time, the gate is greatly reduced. Leakage improves the output characteristics of the device and improves the control ability of the gate to the channel.
  • Figures 1 to 6 are steps of the method for preparing the semiconductor structure provided by the present invention.
  • FIG. 7 is a semiconductor structure according to another embodiment of the present invention.
  • FIG. 8 is a semiconductor structure according to another embodiment of the present invention.
  • Icon 1-substrate; 2-nucleation layer; 3-buffer layer; 4-channel layer; 5-barrier layer; 61-rise layer; 62-p-type semiconductor layer; 63-n-type semiconductor layer; 631 -Groove; 64-mask layer; 65-gate; 6-gate structure; 7-source; 8-drain.
  • An embodiment of the present application provides a method for manufacturing a semiconductor structure, including:
  • Step 1 As shown in FIG. 1a, a substrate 1 is provided, and a channel layer 4 and a barrier layer 5 are sequentially grown on the substrate 1.
  • the substrate 1 may be selected from semiconductor materials, ceramic materials, or polymer materials.
  • the substrate 1 is preferably sapphire, silicon carbide, silicon, lithium niobate, silicon on insulating substrate (SOI), nitrogen Gallium or aluminum nitride.
  • the channel layer 4 and the barrier layer 5 are GaN-based materials.
  • the so-called GaN-based materials are semiconductor materials that include at least Ga atoms and N atoms, such as GaN, AlGaN, InGaN, AlInGaN, etc., in this embodiment,
  • the channel layer 4 may be GaN
  • the barrier layer 5 may be AlGaN.
  • the channel layer 4 and the barrier layer 5 form a heterojunction, and a two-dimensional electron gas is formed at the interface.
  • the manufacturing method of the semiconductor structure further includes: forming a nucleation layer 2 and a buffer layer 3 between the substrate 1 and the channel layer 4, as shown in FIG. 1b.
  • a nucleation layer 2 in order to reduce dislocation density and defect density, improve crystal quality and other technical requirements, it can further include forming a nucleation layer 2 above the substrate 1.
  • the nucleation layer 2 can be AlN, AlGaN, and GaN. One or more of.
  • the GaN-based semiconductor structure may further include forming a buffer layer 22 above the nucleation layer 21.
  • the buffer layer 22 may include GaN, AlGaN, or AlInGaN. One or more of.
  • Step 2 As shown in FIG. 2c, a gate structure 6 is prepared on the barrier layer 5, wherein the gate structure 6 includes a p-type semiconductor layer 62 provided on the barrier layer 5, The n-type semiconductor layer 63 on the p-type semiconductor layer, the gate 65 provided on the n-type semiconductor layer, wherein the gate 65 penetrates the n-type semiconductor layer 63, and the bottom of the gate 65 is connected to The p-type semiconductor layer contacts. It is understandable that the bottom of the gate 65 may directly contact the upper surface of the p-type semiconductor; or the gate 65 may partially penetrate the p-type semiconductor layer to achieve the bottom of the gate 65 in contact with the p-type semiconductor layer.
  • the manufacturing process of the gate structure 6 includes:
  • Step S1 As shown in FIG. 2a, a p-type semiconductor layer 62 is grown on the barrier layer 5, and an n-type semiconductor layer 63 is selectively epitaxially grown on the p-type semiconductor layer 62 so that the n-type semiconductor layer 63 is in the middle A groove 631 is left, and the groove 631 penetrates the n-type semiconductor layer 63;
  • Step S2 As shown in FIG. 2b, a gate 65 is formed in the groove 631 of the n-type semiconductor layer 63;
  • Step S3 As shown in FIG. 2c, the p-type semiconductor layer 62 and the n-type semiconductor layer 63 on both sides of the gate 65 are etched to form the gate structure 6.
  • the dashed frame in the figure is the entire gate structure 6.
  • the preparation process of the gate structure 6 may be:
  • Step S1 As shown in FIG. 3a, a p-type semiconductor layer 62 and an n-type semiconductor layer 63 are grown on the barrier layer 5;
  • Step S2 As shown in FIG. 3b, the groove 631 is etched from the side of the n-type semiconductor layer 63 away from the p-type semiconductor layer 62, the groove 631 penetrates the n-type semiconductor layer 63, and the etching stops at p Type semiconductor layer 62;
  • Step S3 As shown in FIG. 3c, a gate 65 is formed 631 in the groove of the n-type semiconductor layer 63;
  • Step S4 As shown in FIG. 3d, the p-type semiconductor layer 62 and the n-type semiconductor layer 63 on both sides of the gate 65 are etched to form a gate structure 6.
  • the groove 631 may also completely penetrate the n-type semiconductor layer 63 and partially penetrate the p-type semiconductor layer; the other steps are the same, as shown in FIGS. 4a-4d.
  • it may also include the use of a mask layer to etch the n-type semiconductor, so as to avoid damage to the n-type semiconductor by direct etching, specifically:
  • a mask layer 64 is formed on the n-type semiconductor layer 63;
  • the groove 631 is etched from the side of the mask layer 64 away from the n-type semiconductor layer 63.
  • the groove completely penetrates the mask layer, and the n-type semiconductor layer stops at the p-type semiconductor layer.
  • the layer either completely penetrates the mask layer, the n-type semiconductor layer, or partially penetrates the p-type semiconductor layer;
  • the mask layer 64 is removed before step S3.
  • the mask layer 64 includes photoresist, SiO 2 , SiN, etc.
  • the preparation method of the semiconductor structure further includes: the gate structure 6 further includes a dummy layer 61 disposed between the p-type semiconductor layer 62 and the barrier layer 5, and the dummy layer 61 is a GaN-based material.
  • the specific preparation process includes:
  • a dummy layer 61 is formed on the barrier layer 5;
  • the dummy layer 61, the p-type semiconductor layer 62, and the n-type semiconductor layer 63 on both sides of the gate are etched to form the gate structure 6.
  • the manufacturing method of the semiconductor structure further includes: after the gate structure 6 is prepared, a source 7 and a drain 8 are formed on both sides of the gate structure 6, as shown in FIG.
  • This application provides a semiconductor structure, as shown in FIG. 6, including:
  • the semiconductor structure further includes: a source 7 and a drain 8 located on both sides of the gate structure 6.
  • the semiconductor structure further includes: the gate structure 6 further includes a dummy layer 61 provided between the p-type semiconductor layer 62 and the barrier layer 5, as shown in FIG. 7.
  • the dummy layer 61 is a GaN-based material.
  • the dummy layer 61 may be GaN.
  • the GaN dummy layer serves as a barrier layer to prevent the diffusion of impurities in the p-type semiconductor layer 62 and prevent the impurity diffusion from causing trenches. Channel degradation improves the output characteristics of the device.
  • the semiconductor structure further includes: a nucleation layer 2 and a buffer layer 3 arranged between the substrate 1 and the channel layer 4, as shown in FIG. 8.
  • the semiconductor structure and the preparation method thereof provided by the present invention adopt a self-aligning process to improve the control ability of the gate to the channel; p-type semiconductor and n-type semiconductor are arranged in the gate area to increase the threshold voltage of the semiconductor device and avoid the gate
  • the vertical leakage of the pole structure can also reduce the side leakage of the gate structure domain.
  • the semiconductor structure and the preparation method provided by the present invention also avoid channel degradation and improve the overall output characteristics of the device.

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Abstract

一种半导体结构及其制备方法，包括：衬底（1）、沟道层（4）、势垒层（5）、栅极结构（6）、源极（7）、漏极（8），其中所述栅极结构（6）包括p型半导体层（62）、n型半导体层（63）、栅极（65）；提高了栅极（65）对沟道的控制能力；提高半导体器件的阈值电压，避免栅极结构（6）垂直漏电，降低栅极结构（6）侧面漏电；避免沟道退化，提高器件的整体输出特性。

Description

一种半导体结构及其制备方法 技术领域
本发明涉及半导体领域，具体而言，涉及一种半导体结构及其制备方法。
背景技术
氮化镓作为第三代半导体材料，具有禁带宽度大、电子饱和速度高、二维电子气浓度高等特点，被认为是制备半导体器件的优良材料，特别是AlGaN/GaN异质结结构，在氮化镓基电子器件中有广泛的应用。
为了让氮化镓基电子器件更适用于高温、高压、高频以及大功率领域，目前的主要做法是：一、在栅极下方刻蚀凹槽，提高栅极控制能力，但是刻蚀精度难以控制，降低输出电流，影响器件增益；二、在栅极下方引入介质层以减小漏电，但是随着器件尺寸的等比例减小，介质层的减薄会使得栅极控制能力越来越弱，漏电比较严重；三、引入钝化层来抑制电流崩塌，但是钝化层的厚度不易掌控，过厚会引入寄生电容，导致器件频率特性退化。
发明内容
有鉴于此，本发明提供了一种半导体结构及其制备方法，提高器件的阈值电压，同时较大程度的减小栅极漏电，提高器件的输出特性以及栅极对沟道的控制能力。
本申请的一实施例中提供了一种半导体结构，包括：
衬底，
依次设于所述衬底上的沟道层、势垒层；
设于所述势垒层上的栅极结构，其中所述栅极结构包括设于所述势垒层上的p型半导体层、设于所述p型半导体层上的n型半导体层、设于n型半导体层上的栅极，其中所述栅极贯穿所述n型半导体层，并且所述栅极底部与p型半导体层接触。
进一步的，所述栅极结构还包括设于p型半导体层与势垒层之间的冒层。
进一步的，所述半导体结构还包括：设于衬底与沟道层之间的成核层、缓冲层。
进一步的，所述半导体结构还包括：位于所述栅极结构两侧的源极、漏极。
本申请的一实施例中还提供了一种半导体结构的制备方法，包括：
提供一衬底；
在所述衬底上依次叠加生长沟道层、势垒层；
在所述势垒层上制备栅极结构，其中所述栅极结构包括设于所述势垒层上的p型半导体层、设于所述p型半导体层上的n型半导体层、设于n型半导体层上的栅极，其中所述栅极贯穿所述n型半导体层，并且所述栅极底部与p型半导体层接触。
进一步的，所述栅极结构的制备过程包括：
在所述势垒层上生长p型半导体层；
在所述p型半导体层上选择性外延生长n型半导体层，使得n型半导体层中间留有凹槽，所述凹槽贯穿n型半导体层；
在所述凹槽中形成栅极；
刻蚀所述栅极两侧的p型半导体层、n型半导体层形成栅极结构。
进一步的，所述栅极结构的制备过程还可以包括：
在所述势垒层上生长p型半导体层、n型半导体层；
从所述n型半导体层远离p型半导体层的一侧开始刻蚀凹槽，所述凹槽完全贯穿n型半导体层，停止于p型半导体层或者完全贯穿n型半导体层、部分贯穿p型半导体层；
在所述凹槽中形成栅极；
刻蚀所述栅极两侧的p型半导体层、n型半导体层形成栅极结构。
进一步的，所述栅极结构的制备过程还包括：
在所述势垒层上生长p型半导体层、n型半导体层、掩膜层；
从所述掩膜层远离所述n型半导体层的一侧开始刻蚀凹槽，所述凹槽完全贯穿掩膜层、n型半导体层停止于p型半导体层或者完全贯穿掩膜层、n型半导体层、部分贯穿p型半导体层；
去除掩膜层；
在所述凹槽中形成栅极；
刻蚀所述栅极两侧的p型半导体层、n型半导体层形成栅极结构。
进一步的，所述栅极结构还包括：在p型半导体层与势垒层之间形成冒层。
进一步的，所述半导体结构的制备方法还包括：在衬底与沟道层之间形成成核层、缓冲层。
进一步的，所述半导体结构的制备方法还包括：在所述栅极结构两侧制备源极、漏极。
本发明提供了的半导体结构及其制备方法，采用自对准工艺，提高了栅极对沟道的控制能力；通过整个栅极结构来提高器件的阈值电压，同时较大程度的减小栅极漏电，提高器件的输出特性，提高栅极对沟道的控制能力。
为使本发明的上述和其他目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合附图，作详细说明如下。
附图简要说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。通过附图所示，本发明的上述及其它目的、特征和优势将更加清晰。在全部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本发明的主旨。
图1-图6是本发明提供的半导体结构的制备方法步骤；
图7是本发明提供另一实施例的半导体结构；
图8是本发明提供另一实施例的半导体结构。
图标：1-衬底；2-成核层；3-缓冲层；4-沟道层；5-势垒层；61-冒层；62-p型半导体层；63-n型半导体层；631-凹槽；64-掩膜层；65-栅极；6-栅极结构；7-源极；8-漏极。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。同时，在本发明的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。在本发明实施例的描述中，将理解的是：当层(或膜)、区域、图案或结构被称作在另一衬底、另一层(或膜)、另一区域、另一垫或另一图案“上”或“下”时，其可以“直接地”或“间接地”在另一衬底、层(或膜)、区域、垫或图案上，或者还可以存在一个或更多个中间层。已经参照附图描述了层的这种位置。出于方便或清楚的目的，附图中所示出的每个层的厚度和尺寸可能被放大、省略或示意性地绘制。此外，元件的尺寸不完全反映实际尺寸。
本申请的一实施例中提供了一种半导体结构的制备方法，包括：
步骤1：如图1a所示，提供一衬底1，在所述衬底上1依次叠加生长沟道层4、势垒层5。
其中所述衬底1可选自半导体材料、陶瓷材料或高分子材料等，本实施例中，衬底1优选为蓝宝石、碳化硅、硅、铌酸锂、绝缘衬底硅(SOI)、氮化镓或氮化铝。
其中所述沟道层4、势垒层5为GaN基材料，所谓GaN基材料为至少包括 Ga原子、N原子的半导体材料，如GaN、AlGaN、InGaN、AlInGaN等，本实施例中，所述沟道层4可为GaN，势垒层5可为AlGaN，所述沟道层4与势垒层5形成异质结，在其界面处形成二维电子气。
进一步的，所述半导体结构的制备方法还包括：在所述衬底1与所述沟道层4之间形成成核层2、缓冲层3，如图1b所示。以GaN基半导体为例，为降低位错密度和缺陷密度，提升晶体质量等技术需求，可进一步包括在衬底1上方形成成核层2，该成核层2可为AlN、AlGaN和GaN中的一种或多种。此外，为了缓冲衬底上方外延结构中的应力，避免外延结构开裂，该GaN基半导体结构还可进一步包括在成核层21上方形成缓冲层22，该缓冲层22可包括GaN、AlGaN、AlInGaN中的一种或多种。
步骤2：如图2c所示，在所述势垒层5上制备栅极结构6，其中所述栅极结构6包括设于所述势垒层5上的p型半导体层62、设于所述p型半导体层上的n型半导体层63、设于所述n型半导体层上的栅极65，其中所述栅极65贯穿所述n型半导体层63，并且所述栅极65底部与所述p型半导体层接触。可以理解的是，所述栅极65底部可以直接与所述p型半导体的上表面接触；也可以使栅极65部分贯穿p型半导体层实现栅极65底部与p型半导体层接触。
本发明一实施例中，所述栅极结构6的制备过程包括：
步骤S1：如图2a所示，在所述势垒层5上生长p型半导体层62，在所述p型半导体层62上选择性外延生长n型半导体层63，使得n型半导体层63中间留有凹槽631，所述凹槽631贯穿n型半导体层63；
步骤S2：如图2b所示，在所述n型半导体层63的凹槽631中形成栅极65；
步骤S3：如图2c所示，刻蚀所述栅极65两侧的p型半导体层62、n型半导体层63形成栅极结构6，图中虚线框中为整个栅极结构6。
本发明另一实施例中，所述栅极结构6的制备过程可以是：
步骤S1：如图3a所示，在所述势垒层5上生长p型半导体层62、n型半导体层63；
步骤S2：如图3b所示，从所述n型半导体层63远离p型半导体层62的一侧开始刻蚀凹槽631，所述凹槽631贯穿n型半导体层63，刻蚀停止于p型半导体层62；
步骤S3：如图3c所示，在所述n型半导体层63的凹槽中631形成栅极65；
步骤S4：如图3d所示，刻蚀所述栅极65两侧的p型半导体层62、n型半导体层63形成栅极结构6。
本实施例中，对于步骤S1，所述凹槽631还可以完全贯穿n型半导体层63，并且部分贯穿p型半导体层；其它步骤相同，如图4a-4d所示。
进一步的，本发明另一实施例中，还可以包括采用掩膜层来实现对n型半导体的刻蚀，避免直接刻蚀对n型半导体的损害，具体的：
如图5a所示，在步骤S2之前，在所述n型半导体层63上形成掩膜层64；
如图5b所示，从所述掩膜层64远离所述n型半导体层63的一侧开始刻蚀凹槽631，所述凹槽完全贯穿掩膜层、n型半导体层停止于p型半导体层或者完全贯穿掩膜层、n型半导体层、部分贯穿p型半导体层；
如图5c所示，在步骤S3之前去除掩膜层64。
其它步骤与第二实施例相同，具体如图5d-5e，本实施例中，所述掩膜层64包括光刻胶、SiO 2、SiN等。
进一步的，所述半导体结构的制备方法还包括：所述栅极结构6还包括冒层61，设于p型半导体层62与势垒层5之间，所述冒层61为GaN基材料。具体制备过程包括：
在生长p型半导体层62之前，在所述势垒层5上先形成冒层61；
在形成栅极之后，刻蚀栅极两侧的冒层61、p型半导体层62、n型半导体层63形成栅极结构6。
其余步骤与上述实施例一致，在此不再赘述。
进一步的，所述半导体结构的制备方法还包括：制备完栅极结构6之后，在栅极结构6的两侧形成源极7、漏极8，如图6所示。
本申请提供了一种半导体结构，如图6所示，包括：
衬底1，
依次设于所述衬底1上的沟道层4、势垒层5；
设于所述势垒层5上的栅极结构6，其中所述栅极结构6包括p型半导体层62、n型半导体层63、栅极65，所述栅极65贯穿所述n型半导体层63；
进一步的，所述半导体结构还包括：位于所述栅极结构6两侧的源极7、漏极8。
进一步的，所述半导体结构还包括：所述栅极结构6还包括设于p型半导体层62与势垒层5之间的冒层61，如图7所示。
所述冒层61为GaN基材料，本实施例中，所述冒层61可为GaN，所述GaN冒层作为阻挡层，可阻止p型半导体层62中杂质的扩散，避免杂质扩散导致沟道退化，提高器件的输出特性。
进一步的，所述半导体结构还包括：设于衬底1与沟道层4之间的成核层2、缓冲层3，如图8所示。
本发明提供的半导体结构及其制备方法，采用自对准工艺，提高了栅极对沟道的控制能力；在栅极区域设置p型半导体、n型半导体，提高半导体器件的阈值电压，避免栅极结构垂直漏电，还可以降低栅极结构域侧面漏电，此外本发明提供的半导体结构及其制备方法还避免沟道退化，提高器件的整体输出特性。
还需要说明的是，在本发明的描述中，除非另有明确的规定和限定，术语“设置”、“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本发明的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描 述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种半导体结构，其特征在于，包括：
    衬底，
    依次设于所述衬底上的沟道层、势垒层；
    设于所述势垒层上的栅极结构，其中所述栅极结构包括设于所述势垒层上的p型半导体层、设于所述p型半导体层上的n型半导体层、设于n型半导体层上的栅极，其中所述栅极贯穿所述n型半导体层，并且所述栅极底部与p型半导体层接触。
  2. 根据权利要求1所述的半导体结构，其特征在于，还包括：设于所述栅极结构两侧的源极、漏极。
  3. 根据权利要求1所述的半导体结构，其特征在于，还包括：设于衬底与沟道层之间的成核层、缓冲层。
  4. 根据权利要求1所述的半导体结构，其特征在于：所述栅极结构还包括设于p型半导体层与势垒层之间的冒层。
  5. 根据权利要求1或4所述的半导体结构，其特征在于：所述沟道层、势垒层、冒层为GaN基材料。
  6. 一种半导体结构的制备方法，其特征在于，包括：
    提供一衬底；
    在所述衬底上依次叠加生长沟道层、势垒层；
    在所述势垒层上制备栅极结构，其中所述栅极结构包括设于所述势垒层上的p型半导体层、设于所述p型半导体层上的n型半导体层、设于n型半导体层上的栅极，其中所述栅极贯穿所述n型半导体层，并且所述栅极底部与p型半导体层接触。
  7. 根据权利要求6所述的半导体结构的制备方法，其特征在于，还包括：在所述栅极结构两侧制备源极、漏极。
  8. 根据权利要求6所述的半导体结构的制备方法，其特征在于：所述栅极结构的制备步骤包括：
    S1:在所述势垒层上生长p型半导体层；
    S2:在所述p型半导体层上选择性外延生长n型半导体层，使得n型半导体层中间留有凹槽，所述凹槽贯穿n型半导体层；
    S3:在所述凹槽中形成栅极；
    S4:刻蚀所述栅极两侧的p型半导体层、n型半导体层形成栅极结构。
  9. 根据权利要求6所述的半导体结构的制备方法，其特征在于：所述栅极结构的制备步骤包括：
    S1:在所述势垒层上生长p型半导体层、n型半导体层；
    S2:从所述n型半导体层远离p型半导体层的一侧开始刻蚀凹槽，所述凹槽完全贯穿n型半导体层，停止于p型半导体层或者完全贯穿n型半导体层、部分贯穿p型半导体层；
    S3:在所述凹槽中形成栅极；
    S4:刻蚀所述栅极两侧的p型半导体层、n型半导体层形成栅极结构。
  10. 根据权利要求9所述的半导体结构的制备方法，其特征在于：所述栅极结构的制备步骤还包括：
    在步骤S2之前，在所述n型半导体层上形成掩膜层；
    从所述掩膜层远离所述n型半导体层的一侧开始刻蚀凹槽，
    所述凹槽完全贯穿掩膜层、n型半导体层停止于p型半导体层或者完全贯穿掩膜层、n型半导体层、部分贯穿p型半导体层；
    在步骤S3之前去除掩膜层。
  11. 根据权利要求10所述的半导体结构的制备方法，其特征在于：所述掩膜层包括光刻胶、SiO 2、SiN等。
  12. 根据权利要求6所述的半导体结构的制备方法，其特征在于，还包括：在衬底上与沟道层之间形成成核层、缓冲层。
  13. 根据权利要求6所述的半导体结构的制备方法，其特征在于：所述栅极结构还包括在势垒层与p型半导体层之间形成冒层。
  14. 根据权利要求6或13所述的半导体结构的制备方法，其特征在于：所述沟道层、势垒层、冒层为GaN基材料。
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