WO2021184299A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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WO2021184299A1
WO2021184299A1 PCT/CN2020/080215 CN2020080215W WO2021184299A1 WO 2021184299 A1 WO2021184299 A1 WO 2021184299A1 CN 2020080215 W CN2020080215 W CN 2020080215W WO 2021184299 A1 WO2021184299 A1 WO 2021184299A1
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layer
semiconductor
heterojunction
heavily doped
gate
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PCT/CN2020/080215
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to US17/795,481 priority Critical patent/US20230053045A1/en
Priority to CN202080097589.5A priority patent/CN115244709A/zh
Priority to PCT/CN2020/080215 priority patent/WO2021184299A1/zh
Publication of WO2021184299A1 publication Critical patent/WO2021184299A1/zh

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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

Definitions

  • This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof.
  • the wide-gap semiconductor material group III nitride has the excellent characteristics of large forbidden bandwidth, high pressure resistance, high temperature resistance, high electron saturation speed and drift speed, and easy formation of high-quality heterostructures. It is very suitable for manufacturing high-temperature, high-frequency, high-power electronic devices.
  • Enhanced devices have a very wide range of applications in the field of power electronics due to their normally-off characteristics. There are many ways to implement enhanced devices, such as depleting the two-dimensional electron gas by arranging a p-type semiconductor at the gate.
  • the inventor of the present application found that the enhanced device realized by arranging a p-type semiconductor at the gate has a lower threshold voltage, and this method needs to etch the p-type semiconductor outside the gate area, but the etching inevitably leads to etching Eclipse loss.
  • the ohmic contact layer needs to be formed by high-temperature annealing, which affects the performance of the semiconductor structure.
  • the first aspect of the present invention provides a semiconductor structure, including:
  • a p-type semiconductor layer located in the groove and in the gate region on the transition layer;
  • a heavily n-type ion doped layer located on the p-type semiconductor layer of the gate region, and/or on the source region of the heterojunction, and/or on the drain region of the heterojunction.
  • the material of the n-type ion heavily doped layer includes a group III nitride material.
  • the transition layer is also located in the groove.
  • the non-gate region on the transition layer also has the p-type semiconductor layer.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top.
  • the n-type ion heavily doped layer contacts the channel layer or the barrier layer.
  • the heterojunction includes a group III nitride material.
  • the in-situ insulating layer has a single-layer structure, and the material of the single-layer structure includes: a mixture of one or more of SiN and AlN; or the in-situ insulating layer has a laminated structure, so The laminated structure includes from bottom to top: SiN layer and AlN layer, AlN layer and SiN layer, or SiN layer, AlN layer and SiN layer.
  • the transition layer has a single-layer structure, and the material of the single-layer structure includes: a mixture of one or more of AlN, SiAlN, and AlGaN; or the transition layer has a laminated structure, and the laminated structure
  • the layer structure includes at least two layers of an AlN layer, a SiAlN layer, and an AlGaN layer.
  • the semiconductor structure further includes: a gate located on the n-type ion heavily doped layer in the gate region, a source located on the n-type ion heavily doped layer in the source region, and The drain located on the n-type ion heavily doped layer in the drain region.
  • a second aspect of the present invention provides a method for manufacturing a semiconductor structure, including:
  • An n-type ion heavily doped layer is formed on the p-type semiconductor layer of the gate region, and/or on the source region of the heterojunction, and/or on the drain region of the heterojunction.
  • the material of the n-type ion heavily doped layer includes a group III nitride material.
  • the manufacturing method further includes: patterning the p-type semiconductor layer, and retaining the p-type semiconductor layer in the gate region.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top.
  • the n-type ion heavily doped layer contacts the channel layer or the barrier layer.
  • the heterojunction includes a group III nitride material.
  • the in-situ insulating layer has a single-layer structure, and the material of the single-layer structure includes: a mixture of one or more of SiN and AlN; or the in-situ insulating layer has a laminated structure, so The laminated structure includes from bottom to top: SiN layer and AlN layer, AlN layer and SiN layer, or SiN layer, AlN layer and SiN layer.
  • the transition layer has a single-layer structure, and the material of the single-layer structure includes: a mixture of one or more of AlN, SiAlN, and AlGaN; or the transition layer has a laminated structure, and the laminated structure
  • the layer structure includes at least two layers of an AlN layer, a SiAlN layer, and an AlGaN layer.
  • the manufacturing method further includes: forming a gate on the n-type ion heavily doped layer in the gate region, forming a source on the n-type ion heavily doped layer in the source region, and A drain is formed on the n-type ion heavily doped layer in the drain region.
  • a third aspect of the present invention provides a method for manufacturing a semiconductor structure, including:
  • An n-type ion heavily doped layer is formed on the p-type semiconductor layer of the gate region, and/or on the source region of the heterojunction, and/or on the drain region of the heterojunction.
  • the material of the n-type ion heavily doped layer includes a group III nitride material.
  • the manufacturing method further includes: patterning the p-type semiconductor layer, and retaining the p-type semiconductor layer in the gate region.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top.
  • the n-type ion heavily doped layer contacts the channel layer or the barrier layer.
  • the heterojunction includes a group III nitride material.
  • the in-situ insulating layer has a single-layer structure, and the material of the single-layer structure includes: a mixture of one or more of SiN and AlN; or the in-situ insulating layer has a laminated structure, so The laminated structure includes from bottom to top: SiN layer and AlN layer, AlN layer and SiN layer, or SiN layer, AlN layer and SiN layer.
  • the transition layer has a single-layer structure, and the material of the single-layer structure includes: a mixture of one or more of AlN, SiAlN, and AlGaN; or the transition layer has a laminated structure, and the laminated structure
  • the layer structure includes at least two layers of an AlN layer, a SiAlN layer, and an AlGaN layer.
  • the manufacturing method further includes: forming a gate on the n-type ion heavily doped layer in the gate region, and forming a source on the n-type ion heavily doped layer in the source region, and A drain is formed on the n-type ion heavily doped layer in the drain region.
  • the present invention has the following beneficial effects:
  • the semiconductor structure of the present invention includes: a semiconductor substrate, a heterojunction, an in-situ insulating layer, a transition layer, a p-type semiconductor layer, and an n-type ion heavily doped layer, wherein the semiconductor substrate, the heterojunction and the in-situ The insulating layer is distributed from bottom to top, the in-situ insulating layer has a groove, the transition layer is at least on the in-situ insulating layer outside the groove, the p-type semiconductor layer is located in the groove and the gate area on the transition layer, the n-type The heavily ion-doped layer is located on the p-type semiconductor layer in the gate region, and/or on the source region of the heterojunction, and/or on the drain region of the heterojunction.
  • the transition layer facilitates the formation of the p-type semiconductor layer outside the groove during the process.
  • the in-situ insulating layer and the transition layer can reduce the gate leakage current formed by the channel leakage to the gate in the device, so the thickness of the barrier layer in the heterojunction can be smaller, which can increase the threshold voltage; in addition, due to the in-situ
  • the arrangement of the insulating layer can reduce the square resistance, increase the concentration of two-dimensional electron gas, improve the control ability of the gate to the channel, and increase the working current.
  • the arrangement of the transition layer can prevent the selective growth of p-type semiconductor on the in-situ insulating layer on the one hand, thereby improving the quality of the p-type semiconductor layer, and on the other hand, it can also prevent atoms (such as Si atoms) in the in-situ insulating layer. Diffusion into the p-type semiconductor layer affects the p-type semiconductor layer.
  • the n-type ion heavily doped layer makes the source and the source region of the heterojunction, the drain and the drain region of the heterojunction, and the p-type semiconductor layer of the gate and the gate region directly form an ohmic contact layer, Avoid high temperature annealing.
  • the heterojunction includes a channel layer and a barrier layer from bottom to top.
  • the channel layer and the barrier layer may each have one layer; or b) the channel layer and the barrier layer may each have multiple layers and are alternately distributed; or c) one layer of channel layer and two layers or More than two barrier layers to meet different functional requirements.
  • the heterojunction includes a group III nitride material.
  • the group III nitride material may include any one or a combination of GaN, AlGaN, and AlInGaN.
  • the semiconductor structure of the present invention has strong compatibility with existing HEMT devices.
  • the p-type semiconductor layer includes a group III nitride material.
  • the material of the transition layer includes: at least one of AlN, SiAlN, and AlGaN.
  • the group III nitride material may include any one or a combination of GaN, AlGaN, and AlInGaN.
  • the transition layer is formed by an in-situ growth process, which can improve the quality of the subsequent p-type semiconductor layer.
  • the non-gate region on the transition layer also has a p-type semiconductor layer.
  • the p-type semiconductor layer on the transition layer can be patterned, leaving only the p-type semiconductor layer in the gate area, consuming the excess two-dimensional electron gas under the gate; due to the existence of the in-situ insulating layer and the transition layer, the non-gate
  • the p-type semiconductor layer in the pole region may not be patterned, and both the p-type semiconductor layer in the gate region and the non-gate region remain in the semiconductor structure.
  • the source and drain are in contact with the channel layer or the barrier layer to meet the requirements of different semiconductor structures.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention
  • FIG. 2 is a flowchart of a manufacturing method of a semiconductor structure according to the first embodiment of the present invention
  • 3 to 5 are schematic diagrams of intermediate structures corresponding to the process in FIG. 2;
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 8 is a flowchart of a manufacturing method of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 11 is a flowchart of a manufacturing method of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 12 is a schematic diagram of an intermediate structure corresponding to the process in FIG. 11;
  • FIG. 13 is a schematic structural diagram of a semiconductor structure according to a sixth embodiment of the present invention.
  • FIG. 14 is a schematic structural diagram of a semiconductor structure according to a seventh embodiment of the present invention.
  • FIG. 15 is a schematic structural diagram of a semiconductor structure according to an eighth embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure according to a first embodiment of the present invention.
  • the semiconductor structure 1 includes:
  • the groove 13 penetrates the in-situ insulating layer 12 (refer to FIG. 4);
  • transition layer 14 located in the groove 13 and on the in-situ insulating layer 12;
  • the n-type ion heavily doped layer 16 is located on the p-type semiconductor layer 15 in the gate region and on the source region and drain region of the heterojunction 11;
  • the gate 17a is located on the n-type ion heavily doped layer 16 in the gate region
  • the source 17b is located on the n-type ion heavily doped layer 16 in the source region
  • the material of the semiconductor substrate 10 may be sapphire, silicon carbide, silicon, GaN or diamond.
  • the heterojunction 11 may include a channel layer 11a and a barrier layer 11b from bottom to top.
  • a two-dimensional electron gas may be formed at the interface between the channel layer 11a and the barrier layer 11b.
  • the channel layer 11a is an intrinsic GaN layer
  • the barrier layer 11b is an n-type AlGaN layer.
  • the combination of the channel layer 11a and the barrier layer 11b may also be GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN or InN/InAlN.
  • two or more barrier layers 11b to form a multi-barrier structure.
  • the material of the nucleation layer may be, for example, AlN, AlGaN, etc.
  • the material of the buffer layer may include AlN, GaN, AlGaN. , At least one of AlInGaN.
  • the nucleation layer can alleviate the epitaxially grown semiconductor layer, such as the lattice mismatch and thermal mismatch between the channel layer 11a in the heterojunction 11 and the semiconductor substrate 10, and the buffer layer can reduce the epitaxially grown semiconductor layer. The dislocation density and defect density are improved, and the crystal quality is improved.
  • the in-situ insulating layer 12 is an insulating layer formed by an in-situ growth process.
  • One of the functions of the in-situ insulating layer 12 is to electrically insulate the gate 17a and the barrier layer 11b outside the groove 13.
  • the in-situ insulating layer 12 can also suppress the current collapse effect.
  • the in-situ insulating layer 12 has a single-layer structure, and the material of the single-layer structure includes one or a mixture of SiN and AlN.
  • the in-situ insulating layer 12 is a laminated structure, which from bottom to top may include: SiN layer and AlN layer, AlN layer and SiN layer, or SiN layer, AlN layer and SiN layer, etc. .
  • the transition layer 14 may be formed by an in-situ growth process.
  • the transition layer 14 has a single-layer structure, and the material of the single-layer structure may include: one or a mixture of AlN, SiAlN, and AlGaN.
  • the transition layer 14 has a laminated structure, and the laminated structure may include at least two layers among an AlN layer, a SiAlN layer, and an AlGaN layer.
  • the transition layer 14 of the above material can solve the problem that the p-type III nitride material cannot grow on the in-situ insulating layer 12, so the p-type semiconductor layer 15 can be formed outside the groove 13.
  • the p-type semiconductor layer 15 may be a group III nitride material, for example, at least one of GaN, AlGaN, and AlInGaN, and the p-type dopant ions may be magnesium ions to deplete the two-dimensional electron gas under the gate region. To form an enhanced device.
  • the p-type semiconductor layer 15 has a recessed area at the corresponding groove 13, and a part of the gate 17 a is located in the recessed area.
  • the upper surface of the p-type semiconductor layer 15 and the lower surface of the gate 17a may also be flat.
  • the source electrode 17b and the drain electrode 17c are in contact with the barrier layer 11b, and the n-type ion heavily doped layer 16 is formed between the source electrode 17b and the barrier layer 11b, and between the drain electrode 17c and the barrier layer 11b.
  • Ohmic contact; the gate 17a and the p-type semiconductor layer 15 are heavily doped with n-type ions to also form an ohmic contact.
  • the source electrode 17b, the drain electrode 17c, and the gate electrode 17a may be made of metal, such as Ti/Al/Ni/Au, Ni/Au and other existing conductive materials.
  • the n-type ion heavily doped layer 16 can make the source 17b and the source region of the heterojunction 11, the drain 17c and the drain region of the heterojunction 11, the gate 17a and the p-type semiconductor layer 15 of the gate region different
  • the ohmic contact layer can be directly formed by high temperature annealing.
  • an n-type ion heavily doped layer 16 may also be provided on the p-type semiconductor layer 15 in the gate region and on at least one of the source region and the drain region of the heterojunction 11.
  • the drain region and the drain 17c of the heterojunction 11 where the n-type ion heavily doped layer 16 is not provided are subjected to high temperature annealing to form an ohmic contact layer.
  • the n-type ion may be at least one of Si ion, Ge ion, Sn ion, Se ion, or Te ion.
  • the doping concentration can be greater than 1E19/cm 3 .
  • the n-type ion heavily doped layer 16 may be a group III nitride material, for example, at least one of GaN, AlGaN, and AlInGaN.
  • the in-situ insulating layer 12 and the transition layer 14 reduce the gate leakage current formed by the channel leaking to the gate 17a, so the thickness of the barrier layer 11b in the heterojunction 11 can be small, which can The threshold voltage is reduced; in addition, due to the in-situ insulating layer 12, the surface resistance can be reduced, and the concentration of two-dimensional electron gas can be increased, thereby improving the gate's ability to control the channel and increasing the operating current.
  • the sheet resistance (area resistance) between the source 17b and the drain 17c can be reduced from 2300 ⁇ / ⁇ to 325 ⁇ / ⁇ , and the two-dimensional electron gas concentration in the heterojunction 11 can be reduced from 2.4E12/cm 2 increased to 1.03E13/cm 2 .
  • the thickness of the barrier layer 11b is 15 nm-25 nm to ensure the generation of a sufficient concentration of two-dimensional electron gas.
  • the thickness of the barrier layer 11b when the thickness of the barrier layer 11b is in the range of 1 nm to 15 nm, a sufficient concentration of two-dimensional electron gas can be generated; preferably, the thickness of the barrier layer 11b can be controlled below 10 nm.
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor structure according to the first embodiment of the present invention
  • FIGS. 3 to 5 are schematic diagrams of intermediate structures corresponding to the flow in FIG. 2.
  • a semiconductor substrate 10 is provided, and a heterojunction 11 is formed on the semiconductor substrate 10.
  • the material of the semiconductor substrate 10 may be sapphire, silicon carbide, silicon, GaN or diamond.
  • the heterojunction 11 may include a channel layer 11a and a barrier layer 11b from bottom to top.
  • the channel layer 11a is an intrinsic GaN layer
  • the barrier layer 11b is an n-type AlGaN layer.
  • the combination of the channel layer 11a and the barrier layer 11b may also be GaN/AlN, GaN/InN, GaN/InAlGaN, GaAs/AlGaAs, GaN/InAlN or InN/InAlN.
  • the formation process of the channel layer 11a and the barrier layer 11b may include: atomic layer deposition (ALD, Atomic Layer Deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxial growth (MBE, Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD), or Metal Organic Compound Chemical Vapor Deposition (MOCVD, Metal -Organic Chemical Vapor Deposition), or a combination thereof.
  • ALD Atomic Layer Deposition
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxial growth
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal Organic Compound Chemical Vapor Deposition
  • One layer or two or more barrier layers 11b to form a multi-barrier structure In addition to the channel layer 11a and the barrier layer 11b shown in FIG. One layer or two or more barrier layers 11b to form a multi-barrier structure.
  • a nucleation layer and a buffer layer may be formed in sequence.
  • the material of the nucleation layer may be, for example, AlN, AlGaN, etc., and the material of the buffer layer may include AlN. , At least one of GaN, AlGaN, AlInGaN.
  • the method of forming the buffer layer may be the same as the method of forming the heterojunction 11.
  • the nucleation layer can alleviate the epitaxially grown semiconductor layer, such as the lattice mismatch and thermal mismatch between the channel layer 11a in the heterojunction 11 and the semiconductor substrate 10, and the buffer layer can reduce the epitaxially grown semiconductor layer. The dislocation density and defect density are improved, and the crystal quality is improved.
  • an in-situ insulating layer 12 is formed on the heterojunction 11.
  • the in-situ insulating layer 12 is an insulating layer formed by an in-situ growth process.
  • the in-situ insulating layer 12 has a single-layer structure, and the material of the single-layer structure includes one or a mixture of SiN and AlN.
  • the in-situ insulating layer 12 is a laminated structure, which from bottom to top may include: SiN layer and AlN layer, AlN layer and SiN layer, or SiN layer, AlN layer and SiN layer, etc. .
  • step S3 in FIG. 2 and as shown in FIG. 4 a groove 13 penetrating the in-situ insulating layer 12 is formed.
  • the groove 13 can be formed by dry etching or wet etching. Specifically, a patterned mask layer is formed on the in-situ insulating layer 12 first.
  • the mask layer may be a photoresist layer, which is patterned by a process of exposure first and then development.
  • the dry etching gas can be CF 4 , C 3 F 8, etc.
  • the wet etching solution can be hot phosphoric acid.
  • a transition layer 14 and a p-type semiconductor layer 15 are sequentially formed in the groove 13 and on the in-situ insulating layer 12.
  • the transition layer 14 may be formed by an in-situ growth process.
  • the transition layer 14 has a single-layer structure, and the material of the single-layer structure may include: one or a mixture of AlN, SiAlN, and AlGaN.
  • the transition layer 14 has a laminated structure, and the laminated structure may include at least two layers of an AlN layer, a SiAlN layer, and an AlGaN layer.
  • the p-type semiconductor layer 15 includes a group III nitride material, for example, at least one of GaN, AlGaN, and AlInGaN, and the p-type dopant ions may be magnesium ions.
  • the formation process of the p-type semiconductor layer 15 can refer to the formation process of the channel layer 11a and the barrier layer 11b.
  • the p-type semiconductor layer 15 has a recessed area at the corresponding groove 13.
  • the upper surface of the p-type semiconductor layer 15 may also be flat.
  • an n-type ion heavily doped layer 16 is formed on the p-type semiconductor layer 15 in the gate region and on the source region and the drain region of the heterojunction 11 .
  • the n-type ion heavily doped layer 16 may be a group III nitride material, for example, at least one of GaN, AlGaN, AlInGaN, and the n-type dopant ion may be Si ion, Ge ion, Sn ion, Se ion or At least one of Te ions.
  • the formation process of the n-type ion heavily doped layer 16 can refer to the formation process of the channel layer 11a and the barrier layer 11b, and n-type ions can be doped while growing, or n-type ions can be implanted after epitaxial growth.
  • an n-type ion heavily doped layer 16 may also be formed on the p-type semiconductor layer 15 in the gate region and on at least one of the source region and the drain region of the heterojunction 11.
  • a gate 17a is formed on the n-type ion heavily doped layer 16 in the gate region, and a source is formed on the n-type ion heavily doped layer 16 in the source region.
  • a drain electrode 17c is formed on the electrode 17b and the n-type ion heavily doped layer 16 in the drain region.
  • the material of the source electrode 17b, the drain electrode 17c, and the gate electrode 17a may be metal, such as existing conductive materials such as Ti/Al/Ni/Au, Ni/Au, etc., which are correspondingly formed by physical vapor deposition or chemical vapor deposition.
  • the p-type semiconductor layer 15 has a recessed area at the corresponding groove 13, part of the gate 17a is located in the recessed area.
  • the upper surface of the p-type semiconductor layer 15 and the lower surface of the gate 17a may also be flat.
  • FIG. 6 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
  • the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment.
  • the only difference is that the source 17b and the drain 17c contact the channel layer 11a, and the source 17b is in contact with the channel layer 11a.
  • the n-type ion heavily doped layer 16 is used to form ohmic contacts between the channel layers 11a and between the drain 17c and the channel layer 11a.
  • the manufacturing method of the semiconductor structure 2 of the second embodiment is substantially the same as the manufacturing method of the semiconductor structure 1 of the first embodiment, except that: in step S5, the source region and the drain region of the heterojunction 11
  • the n-type ion heavily doped layer 16 is formed, the p-type semiconductor layer 15, the transition layer 14, the in-situ insulating layer 12, and the barrier layer 11b in the source region and the drain region are removed, and the channel layer 11a is exposed.
  • the n-type ion heavily doped layer 16 allows the source electrode 17b and the channel layer 11a, and the drain electrode 17c and the channel layer 11a to directly form an ohmic contact layer without high-temperature thermal annealing.
  • the source 17b and the drain 17c contact the channel layer 11a, and the n-type ion heavily doped layer 16 is used between the source 17b and the channel layer 11a, or between the drain 17c and the channel layer 11a.
  • An ohmic contact is formed.
  • the channel layer 11a and the source electrode 17b without the heavily n-type ion doped layer 16 or the channel layer 11a and the drain electrode 17c without the n-type ion heavily doped layer 16 can form an ohmic contact layer by high temperature annealing.
  • FIG. 7 is a schematic structural diagram of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 8 is a flowchart of a manufacturing method of a semiconductor structure according to a third embodiment of the present invention.
  • the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structures 1 and 2 of the first and second embodiments. The only difference is: on the transition layer 14, only the gate region There is a p-type semiconductor layer 15.
  • step S4' It also includes the step of patterning the p-type semiconductor layer 15.
  • step S4' includes: sequentially forming a transition layer 14 and a p-type semiconductor layer 15 in the groove 13 and on the in-situ insulating layer 12; patterning the p-type semiconductor layer 15, leaving only the p-type semiconductor layer 15 in the gate region .
  • the patterned p-type semiconductor layer 15 can be implemented by dry etching or wet etching. Compared with the scheme of patterning the p-type semiconductor layer 15 directly formed on the barrier layer 11b, the in-situ insulating layer 12 and the transition layer 14 can prevent the barrier layer 11b from being damaged by over-etching during the patterning process.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention.
  • the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structures 1, 2, and 3 of the first, second, and third embodiments. The only difference is that the semiconductor structure 4 is In the intermediate semiconductor structure, the gate 17a, source 17b, and drain 17c are not fabricated.
  • the manufacturing method of the semiconductor structure 4 of the fourth embodiment is substantially the same as the manufacturing methods of the semiconductor structures 1, 2, and 3 of the first, second, and third embodiments, except that step S6 is omitted.
  • the semiconductor structure 4 can also be produced and sold as a semi-finished product.
  • FIG. 10 is a schematic structural diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 11 is a flowchart of a manufacturing method of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 12 is a schematic diagram of an intermediate structure corresponding to the process in FIG. 11.
  • the semiconductor structure 5 includes:
  • the groove 13 penetrates the in-situ insulating layer 12 and the transition layer 14;
  • the p-type semiconductor layer 15 located in the groove 13 and on the transition layer 14;
  • the n-type ion heavily doped layer 16 is located on the p-type semiconductor layer 15 in the gate region and on the source region and drain region of the heterojunction 11;
  • the gate 17a is located on the n-type ion heavily doped layer 16 in the gate region
  • the source 17b is located on the n-type ion heavily doped layer 16 in the source region
  • the semiconductor structure 5 of the fifth embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, except that the groove 13 penetrates the in-situ insulating layer 12 and the transition layer 14, namely The transition layer 14 is only located on the in-situ insulating layer 12 outside the groove 13.
  • Step S2' includes: The in-situ insulating layer 12 and the transition layer 14 are sequentially formed on the heterojunction 11;
  • step S3' includes: forming a groove 13 penetrating the in-situ insulating layer 12 and the transition layer 14;
  • step S4" includes: in the groove 13 and the transition A p-type semiconductor layer 15 is formed on the layer 14.
  • the source electrode 17b and the drain electrode 17c are in contact with the barrier layer 11b, and the n-type ion heavily doped layer 16 is formed between the source electrode 17b and the barrier layer 11b, and between the drain electrode 17c and the barrier layer 11b.
  • Ohmic contact; the gate 17a and the p-type semiconductor layer 15 are heavily doped with n-type ions to also form an ohmic contact.
  • the n-type ion heavily doped layer 16 can make the source 17b and the source region of the heterojunction 11, the drain 17c and the drain region of the heterojunction 11, the gate 17a and the p-type semiconductor layer 15 of the gate region different
  • the ohmic contact layer can be directly formed by high temperature annealing.
  • an n-type ion heavily doped layer 16 may also be provided on the p-type semiconductor layer 15 in the gate region and on at least one of the source region and the drain region of the heterojunction 11.
  • the drain region and the drain 17c of the heterojunction 11 where the n-type ion heavily doped layer 16 is not provided are subjected to high temperature annealing to form an ohmic contact layer.
  • the in-situ insulating layer 12 and the transition layer 14 reduce the gate leakage current formed by the channel leakage to the gate 17a, so the thickness of the barrier layer 11b in the heterojunction 11 can be small, which can Lower the threshold voltage; in addition, due to the in-situ insulating layer 12, the surface resistance can be reduced, and the concentration of the two-dimensional electron gas can be increased, thereby improving the gate's ability to control the channel and increasing the operating current.
  • the thickness of the barrier layer 11b is 15 nm-25 nm to ensure the generation of a sufficient concentration of two-dimensional electron gas.
  • the thickness of the barrier layer 11b when the thickness of the barrier layer 11b is in the range of 1 nm to 15 nm, a sufficient concentration of two-dimensional electron gas can be generated; preferably, the thickness of the barrier layer 11b can be controlled below 10 nm.
  • FIG. 13 is a schematic structural diagram of a semiconductor structure according to a sixth embodiment of the present invention.
  • the semiconductor structure 6 of the sixth embodiment is substantially the same as the semiconductor structure 5 of the fifth embodiment. The only difference is that the source 17b and the drain 17c contact the channel layer 11a, and the source 17b is in contact with the channel layer 11a.
  • the n-type ion heavily doped layer 16 is used to form ohmic contacts between the channel layers 11a and between the drain 17c and the channel layer 11a.
  • the manufacturing method of the semiconductor structure 6 of the sixth embodiment is substantially the same as the manufacturing method of the semiconductor structure 5 of the fifth embodiment, except that: in step S5, the source region and the drain region of the heterojunction 11
  • the n-type ion heavily doped layer 16 is formed, the p-type semiconductor layer 15, the transition layer 14, the in-situ insulating layer 12, and the barrier layer 11b in the source region and the drain region are removed, and the channel layer 11a is exposed.
  • the n-type ion heavily doped layer 16 allows the source electrode 17b and the channel layer 11a, and the drain electrode 17c and the channel layer 11a to directly form an ohmic contact layer without high-temperature thermal annealing.
  • the source 17b and the drain 17c contact the channel layer 11a, and the n-type ion heavily doped layer 16 is used between the source 17b and the channel layer 11a, or between the drain 17c and the channel layer 11a.
  • An ohmic contact is formed.
  • the channel layer 11a and the source electrode 17b without the heavily n-type ion doped layer 16 or the channel layer 11a and the drain electrode 17c without the n-type ion heavily doped layer 16 can form an ohmic contact layer by high temperature annealing.
  • FIG. 14 is a schematic structural diagram of a semiconductor structure according to a seventh embodiment of the present invention.
  • the semiconductor structure 7 of the seventh embodiment is substantially the same as the semiconductor structures 5 and 6 of the fifth and sixth embodiments. The only difference is: on the transition layer 14, only the gate region There is a p-type semiconductor layer 15.
  • step S4 the manufacturing method of the semiconductor structure 7 of the seventh embodiment is roughly the same as the manufacturing methods of the semiconductor structures 5 and 6 of the fifth and sixth embodiments, except that: in step S4", it also includes: patterned p-type The step of the semiconductor layer 15.
  • step S4" includes: forming a p-type semiconductor layer 15 in the groove 13 and on the transition layer 14; patterning the p-type semiconductor layer 15, leaving only the p-type semiconductor layer 15 in the gate region.
  • the patterned p-type semiconductor layer 15 can be implemented by dry etching or wet etching. Compared with the scheme of patterning the p-type semiconductor layer 15 directly formed on the barrier layer 11b, the in-situ insulating layer 12 and the transition layer 14 can prevent the barrier layer 11b from being damaged by over-etching during the patterning process.
  • FIG. 15 is a schematic structural diagram of a semiconductor structure according to an eighth embodiment of the present invention.
  • the semiconductor structure 8 of the eighth embodiment is substantially the same as the semiconductor structures 5, 6, and 7 of the fifth, sixth, and seventh embodiments. The only difference is that the semiconductor structure 8 is In the intermediate semiconductor structure, the gate 17a, source 17b, and drain 17c are not fabricated.
  • the manufacturing method of the semiconductor structure 8 of the eighth embodiment is substantially the same as the manufacturing methods of the semiconductor structures 5, 6, and 7 of the fifth, sixth, and seventh embodiments, except that step S6 is omitted.
  • the semiconductor structure 8 can also be produced and sold as a semi-finished product.

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Abstract

本申请提供了一种半导体结构及其制作方法，半导体结构中，半导体衬底、异质结与原位绝缘层自下而上分布，原位绝缘层中具有凹槽，过渡层至少位于原位绝缘层上，p型半导体层位于凹槽内以及过渡层上的栅极区域，n型离子重掺杂层位于栅极区域的p型半导体层上、和/或异质结的源极区域上、和/或异质结的漏极区域上。原位绝缘层与过渡层可减小器件中沟道泄漏到栅极形成的栅泄漏电流，因而异质结中的势垒层的厚度可以较小，阈值电压可提高；此外，可减小方块电阻，增加二维电子气的浓度，提高栅极对沟道的控制能力，提升工作电流。n型离子重掺杂层使得源极、漏极、栅极可直接形成欧姆接触层，避免高温退火。

Description

半导体结构及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
宽禁带半导体材料III族氮化物作为第三代半导体材料的典型代表，具有禁带宽带大、耐高压、耐高温、电子饱和速度和漂移速度高、容易形成高质量异质结构的优异特性，非常适合制造高温、高频、大功率电子器件。
例如AlGaN/GaN异质结由于较强的自发极化和压电极化，在AlGaN/GaN界面处存在高浓度的二维电子气(2DEG)，广泛应用于诸如高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)等半导体结构中。
增强型器件由于其常关的特性，在电力电子领域具有非常广泛应用。增强型器件的实现方式有很多种，例如在栅极处通过设置p型半导体耗尽二维电子气。
发明内容
然而本申请发明人发现：通过栅极处设置p型半导体实现的增强型器件，阈值电压较小，且该种方法需要刻蚀栅极区域以外的p型半导体，但刻蚀不可避免带来刻蚀损失。此外，欧姆接触层需高温退火形成，影响半导体结构的性能。
为解决上述问题，本发明的第一方面提供一种半导体结构，包括：
自下而上分布的半导体衬底、异质结以及原位绝缘层；
贯穿所述原位绝缘层的凹槽；
至少位于所述原位绝缘层上的过渡层；
位于所述凹槽内以及所述过渡层上的栅极区域的p型半导体层；
位于所述栅极区域的p型半导体层上，和/或所述异质结的源极区域上，和/或所述异质结的漏极区域上的n型离子重掺杂层。
可选地，所述n型离子重掺杂层的材料包括Ⅲ族氮化物材料。
可选地，所述过渡层还位于所述凹槽内。
可选地，所述过渡层上的非栅极区域也具有所述p型半导体层。
可选地，所述异质结自下而上包括沟道层与势垒层。
可选地，所述n型离子重掺杂层接触所述沟道层或所述势垒层。
可选地，所述异质结包括Ⅲ族氮化物材料。
可选地，所述原位绝缘层为单层结构，所述单层结构的材料包括：SiN、AlN中的一种或多种的混合物；或所述原位绝缘层为叠层结构，所述叠层结构自下而上包括：SiN层与AlN层，AlN层与SiN层，或SiN层、AlN层与SiN层。
可选地，所述过渡层为单层结构，所述单层结构的材料包括：AlN、SiAlN、AlGaN中的一种或多种的混合物；或所述过渡层为叠层结构，所述叠层结构包括：AlN层、SiAlN层、AlGaN层中的至少两层。
可选地，所述半导体结构还包括：位于所述栅极区域的n型离子重掺杂层上的栅极，位于所述源极区域的n型离子重掺杂层上的源极，以及位于所述漏极区域的n型离子重掺杂层上的漏极。
本发明的第二方面提供一种半导体结构的制作方法，包括：
提供半导体衬底，在所述半导体衬底上形成异质结；
在所述异质结上形成原位绝缘层；
形成贯穿所述原位绝缘层的凹槽；
在所述凹槽内以及所述原位绝缘层上依次形成过渡层与p型半导体层；
在所述栅极区域的p型半导体层上，和/或所述异质结的源极区域上，和/或所述异质结的漏极区域上形成n型离子重掺杂层。
可选地，所述n型离子重掺杂层的材料包括Ⅲ族氮化物材料。
可选地，所述制作方法还包括：图形化所述p型半导体层，保留所述栅极区域的p型半导体层。
可选地，所述异质结自下而上包括沟道层与势垒层。
可选地，所述n型离子重掺杂层接触所述沟道层或所述势垒层。
可选地，所述异质结包括Ⅲ族氮化物材料。
可选地，所述原位绝缘层为单层结构，所述单层结构的材料包括：SiN、AlN中的一种或多种的混合物；或所述原位绝缘层为叠层结构，所述叠层结构自下而上包括：SiN层与AlN层，AlN层与SiN层，或SiN层、AlN层与SiN层。
可选地，所述过渡层为单层结构，所述单层结构的材料包括：AlN、SiAlN、AlGaN中的一种或多种的混合物；或所述过渡层为叠层结构，所述叠层结构包括：AlN层、SiAlN层、AlGaN层中的至少两层。
可选地，所述制作方法还包括：在所述栅极区域的n型离子重掺杂层上形成栅极，在所述源极区域的n型离子重掺杂层上形成源极，以及在所述漏极区域的n型离子重掺杂层上形成漏极。
本发明的第三方面提供一种半导体结构的制作方法，包括：
提供半导体衬底，在所述半导体衬底上形成异质结；
在所述异质结上依次形成原位绝缘层与过渡层；
形成贯穿所述原位绝缘层与所述过渡层的凹槽；
在所述凹槽内以及所述过渡层上形成p型半导体层；
在所述栅极区域的p型半导体层上，和/或所述异质结的源极区域上，和/或所述异质结的漏极区域上形成n型离子重掺杂层。
可选地，所述n型离子重掺杂层的材料包括Ⅲ族氮化物材料。
可选地，所述制作方法还包括：图形化所述p型半导体层，保留所述栅极区域的p型半导体层。
可选地，所述异质结自下而上包括沟道层与势垒层。
可选地，所述n型离子重掺杂层接触所述沟道层或所述势垒层。
可选地，所述异质结包括Ⅲ族氮化物材料。
可选地，所述原位绝缘层为单层结构，所述单层结构的材料包括：SiN、AlN中的一种或多种的混合物；或所述原位绝缘层为叠层结构，所述叠层结构自下而上包括：SiN层与AlN层，AlN层与SiN层，或SiN层、AlN层与SiN层。
可选地，所述过渡层为单层结构，所述单层结构的材料包括：AlN、SiAlN、AlGaN中的一种或多种的混合物；或所述过渡层为叠层结构，所述叠层结构包括：AlN层、SiAlN层、AlGaN层中的至少两层。
可选地，所述制作方法还包括：在所述栅极区域的n型离子重掺杂层上形成栅极，在所述源极区域的n型离子重掺杂层上形成源极，以及在所述漏极区域的n型离子重掺杂层上形成漏极。
与现有技术相比，本发明的有益效果在于：
1)本发明的半导体结构包括：半导体衬底、异质结、原位绝缘层、过渡层、p型半导体层以及n型离子重掺杂层，其中，半导体衬底、异质结与原位绝缘层自下而上分布，原位绝缘层中具有凹槽，过渡层至少位于凹槽外的原位绝缘层上，p型半导体层位于凹槽内以及过渡层上的栅极区域，n型离子重掺杂层位于栅极区域的p型半导体层上、和/或异质结的源极区域上、和/或异质结的漏极区域上。过渡层利于工艺中p型半导体层在凹槽外形成。原位绝缘层与过渡层可以减小器件中沟道泄漏到栅极形成的栅泄漏电流，因而异质结中的势垒层的厚度可以较小，从而可以提高阈值电压；此外，由于原位绝缘层的设置，可减小方块电阻，增加二维电子气的浓度，提高栅极对沟道的控制能力，提升工作电流。
过渡层的设置，一方面可避免p型半导体在原位绝缘层上的选择性生长，从而可以提高p型半导体层的质量，另一方面还可以防止原位绝缘层中原子(例如Si原子)扩散到p型半导体层中，对p型半导体层造成影响。
n型离子重掺杂层使得源极可与异质结的源极区域、漏极可与异质结的漏极区域、栅极可与栅极区域的p型半导体层直接形成欧姆接触层，避免高温退火。
2)可选方案中，异质结自下而上包括沟道层与势垒层。具体地，a)沟道层与势垒层可以分别具有一层；或b)沟道层与势垒层可以分别具有多层，且交替分布；或c)一层沟道层与两层或两层以上的势垒层，以满足不同功能需求。
3)可选方案中，异质结包括Ⅲ族氮化物材料。Ⅲ族氮化物材料可以包括GaN、AlGaN、AlInGaN中的任一种或组合。本发明的半导体结构与现有HEMT器件兼容性强。
4)可选方案中，p型半导体层包括Ⅲ族氮化物材料。过渡层的材料包括：AlN、SiAlN、AlGaN中的至少一种。Ⅲ族氮化物材料可以包括GaN、AlGaN、 AlInGaN中的任一种或组合。过渡层采用原位生长工艺形成，可以提升后续p型半导体层的质量。
5)可选方案中，过渡层上的非栅极区域也具有p型半导体层。换言之，过渡层上的p型半导体层可以经图形化，仅保留栅极区域的p型半导体层，消耗栅极下方的多余二维电子气；由于原位绝缘层和过渡层的存在，非栅极区域的p型半导体层也可以不经图形化，栅极区域与非栅极区域的p型半导体层都保留在半导体结构中。
6)可选方案中，源极与漏极接触沟道层或势垒层，满足不同半导体结构的需求。
附图说明
图1是本发明第一实施例的半导体结构的结构示意图；
图2是本发明第一实施例的半导体结构的制作方法的流程图；
图3至图5是图2中的流程对应的中间结构示意图；
图6是本发明第二实施例的半导体结构的结构示意图；
图7是本发明第三实施例的半导体结构的结构示意图；
图8是本发明第三实施例的半导体结构的制作方法的流程图；
图9是本发明第四实施例的半导体结构的结构示意图；
图10是本发明第五实施例的半导体结构的结构示意图；
图11是本发明第五实施例的半导体结构的制作方法的流程图；
图12是图11中的流程对应的中间结构示意图；
图13是本发明第六实施例的半导体结构的结构示意图；
图14是本发明第七实施例的半导体结构的结构示意图；
图15是本发明第八实施例的半导体结构的结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
半导体结构1、2、3、4、5、6、7、8    半导体衬底10
异质结11                            原位绝缘层12
凹槽13                              过渡层14
p型半导体层15                       n型离子重掺杂层16
栅极17a                             源极17b
漏极17c                             沟道层11a
势垒层11b
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体结构的结构示意图。
参照图1所示，半导体结构1包括：
自下而上分布的半导体衬底10、异质结11以及原位绝缘层12；
贯穿原位绝缘层12的凹槽13(参照图4所示)；
位于凹槽13内以及原位绝缘层12上的过渡层14；
位于过渡层14上的p型半导体层15；
位于栅极区域的p型半导体层15上、以及异质结11的源极区域与漏极区域上的n型离子重掺杂层16；
位于栅极区域的n型离子重掺杂层16上的栅极17a，位于源极区域的 n型离子重掺杂层16上的源极17b，以及位于漏极区域的n型离子重掺杂层16上的漏极17c。
半导体衬底10的材料可以为蓝宝石、碳化硅、硅、GaN或金刚石。
异质结11自下而上可以包括沟道层11a与势垒层11b。沟道层11a与势垒层11b的界面处可形成二维电子气。一个可选方案中，沟道层11a为本征GaN层，势垒层11b为n型AlGaN层。其它可选方案中，沟道层11a与势垒层11b组合还可以为GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。此外，除了图1所示的沟道层11a与势垒层11b分别具有一层外；沟道层11a与势垒层11b还可以分别具有多层，且交替分布；或一层沟道层11a与两层或两层以上的势垒层11b，以形成多势垒结构。
异质结11与半导体衬底10之间还可以具有成核层及缓冲层(未图示)，成核层的材质可以例如为AlN、AlGaN等，缓冲层的材质可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。成核层可以缓解外延生长的半导体层，例如异质结11中的沟道层11a与半导体衬底10之间的晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
原位绝缘层12是通过原位生长工艺形成的绝缘层。原位绝缘层12的作用之一在于：电绝缘凹槽13外的栅极17a与势垒层11b。HEMT结构中，原位绝缘层12还可以抑制电流崩塌效应。
一个可选方案中，原位绝缘层12为单层结构，该单层结构的材料包括：SiN、AlN中的一种或多种的混合物。另一个可选方案中，原位绝缘层12为叠层结构，该叠层结构自下而上可以包括：SiN层与AlN层，AlN层与SiN层，或SiN层、AlN层与SiN层等。
过渡层14可以采用原位生长工艺形成。一个可选方案中，过渡层14为单层结构，该单层结构的材料可以包括：AlN、SiAlN、AlGaN中的一种或多种的混合物。另一个可选方案中，过渡层14为叠层结构，该叠层结构可以 包括：AlN层、SiAlN层、AlGaN层中的至少两层。上述材质的过渡层14能解决p型Ⅲ族氮化物材料无法在原位绝缘层12上生长的问题，因而可以在凹槽13外形成p型半导体层15。
p型半导体层15可以为Ⅲ族氮化物材料，例如为GaN、AlGaN、AlInGaN中的至少一种，其中的p型掺杂离子可以为镁离子，以耗尽栅极区域下方的二维电子气以形成增强型器件。
图1所示实施例中，p型半导体层15在对应凹槽13处具有凹陷区域，栅极17a中有部分位于该凹陷区域。一些实施例中，p型半导体层15的上表面以及栅极17a的下表面也可以呈平坦状。
图1中，源极17b与漏极17c接触势垒层11b，且源极17b与势垒层11b之间、漏极17c与势垒层11b之间都利用n型离子重掺杂层16形成欧姆接触；栅极17a与p型半导体层15之间利用n型离子重掺杂层16也形成欧姆接触。源极17b、漏极17c、栅极17a的材质可以为金属，例如Ti/Al/Ni/Au、Ni/Au等现有的导电材质。n型离子重掺杂层16能使源极17b与异质结11的源极区域、漏极17c与异质结11的漏极区域、栅极17a与栅极区域的p型半导体层15不通过高温退火即可直接形成欧姆接触层。
一些实施例中，也可以栅极区域的p型半导体层15上、异质结11的源极区域与漏极区域中的至少一个上具有n型离子重掺杂层16。未设置n型离子重掺杂层16的栅极区域的p型半导体层15与栅极17a、未设置n型离子重掺杂层16的异质结11的源极区域与源极17b、或未设置n型离子重掺杂层16的异质结11的漏极区域与漏极17c通过高温退火形成欧姆接触层。
n型离子重掺杂层16中，n型离子可以为Si离子、Ge离子、Sn离子、Se离子或Te离子中的至少一种。对于不同的n型离子，掺杂浓度可以大于1E19/cm 3。n型离子重掺杂层16可以为Ⅲ族氮化物材料，例如为GaN、AlGaN、AlInGaN中的至少一种。
上述半导体结构1中，原位绝缘层12与过渡层14减小了沟道泄漏到栅极17a形成的栅泄漏电流，因而异质结11中的势垒层11b的厚度可以较小，从而可以降低阈值电压；此外，由于原位绝缘层12的设置，可降低面电阻，增加二维电子气的浓度，从而提高了栅极对沟道的控制能力，提升工作电流。
为验证本发明的技术效果，以势垒层11b的厚度都为5nm为例，5nm Al 0.25GaN势垒层/GaN沟道层半导体结构与5nm原位SiN层/5nm Al 0.25GaN势垒层/GaN沟道层半导体结构进行对比，发现：源极17b与漏极17c之间的方块电阻(面电阻)可以从2300Ω/□降低到325Ω/□，异质结11中二维电子气浓度可以从2.4E12/cm 2增加到1.03E13/cm 2。
此外，现有的AlGaN势垒层/GaN沟道层的HEMT结构中，势垒层11b的厚度为15nm～25nm才能保证有足够浓度的二维电子气产生。而本申请中，势垒层11b的厚度范围为1nm～15nm时，就能产生足够浓度的二维电子气；较佳地，可将势垒层11b的厚度控制在10nm以下。
图2是本发明第一实施例的半导体结构的制作方法的流程图；图3至图5是图2中的流程对应的中间结构示意图。
首先，参照图2中的步骤S1与图3所示，提供半导体衬底10，在半导体衬底10上形成异质结11。
半导体衬底10的材料可以为蓝宝石、碳化硅、硅、GaN或金刚石。
异质结11自下而上可以包括沟道层11a与势垒层11b。一个可选方案中，沟道层11a为本征GaN层，势垒层11b为n型AlGaN层。其它可选方案中，沟道层11a与势垒层11b组合还可以为GaN/AlN、GaN/InN、GaN/InAlGaN、GaAs/AlGaAs、GaN/InAlN或InN/InAlN。沟道层11a与势垒层11b的形成工艺可以包括：原子层沉积法(ALD，Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma  Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式。
除了图1所示的沟道层11a与势垒层11b分别具有一层外；沟道层11a与势垒层11b还可以分别具有多层，且交替分布；或一层沟道层11a与两层或两层以上的势垒层11b，以形成多势垒结构。
在半导体衬底10上形成异质结11之前，还可以先依次形成成核层及缓冲层(未图示)，成核层的材质可以例如为AlN、AlGaN等，缓冲层的材质可以包括AlN、GaN、AlGaN、AlInGaN中的至少一种。缓冲层的形成方法可以与异质结11的形成方法相同。成核层可以缓解外延生长的半导体层，例如异质结11中的沟道层11a与半导体衬底10之间的晶格失配和热失配的问题，缓冲层可以降低外延生长的半导体层的位错密度和缺陷密度，提升晶体质量。
测试图3所示示例结构的方块电阻(面电阻)，大小为2300Ω/□。
接着，参照图2中的步骤S2与图4所示，在异质结11上形成原位绝缘层12。
原位绝缘层12是通过原位生长工艺形成的绝缘层。一个可选方案中，原位绝缘层12为单层结构，该单层结构的材料包括：SiN、AlN中的一种或多种的混合物。另一个可选方案中，原位绝缘层12为叠层结构，该叠层结构自下而上可以包括：SiN层与AlN层，AlN层与SiN层，或SiN层、AlN层与SiN层等。
之后，参照图2中的步骤S3与图4所示，形成贯穿原位绝缘层12的凹槽13。
凹槽13可以采用干法刻蚀或湿法刻蚀形成。具体地，先在原位绝缘层12上形成图形化掩膜层。掩膜层可以为光刻胶层，采用先曝光、后显影工艺 进行图形化。干法刻蚀气体可以为CF 4、C 3F 8等，湿法刻蚀溶液可以为热磷酸。
测试图4所示示例结构的方块电阻(面电阻)，大小为325Ω/□。
接着，参照图2中的步骤S4与图5所示，在凹槽13内以及原位绝缘层12上依次形成过渡层14与p型半导体层15。
过渡层14可以采用原位生长工艺形成。一个可选方案中，过渡层14为单层结构，该单层结构的材料可以包括：AlN、SiAlN、AlGaN中的一种或多种的混合物。另一个可选方案中，过渡层14为叠层结构，该叠层结构可以包括：AlN层、SiAlN层、AlGaN层中的至少两层。
p型半导体层15包括Ⅲ族氮化物材料，例如为GaN、AlGaN、AlInGaN中的至少一种，其中的p型掺杂离子可以为镁离子。p型半导体层15的形成工艺可以参照沟道层11a与势垒层11b的形成工艺。
本实施例中，p型半导体层15在对应凹槽13处具有凹陷区域。一些实施例中，p型半导体层15的上表面也可以呈平坦状。
之后，参照图2中的步骤S5与图1所示，在栅极区域的p型半导体层15上、以及异质结11的源极区域与漏极区域上形成n型离子重掺杂层16。
n型离子重掺杂层16可以为Ⅲ族氮化物材料，例如为GaN、AlGaN、AlInGaN中的至少一种，其中的n型掺杂离子可以为Si离子、Ge离子、Sn离子、Se离子或Te离子中的至少一种。n型离子重掺杂层16的形成工艺可以参照沟道层11a与势垒层11b的形成工艺，可以边生长边掺杂n型离子，也可以外延生长完后注入n型离子。
一些实施例中，也可以在栅极区域的p型半导体层15上、异质结11的源极区域与漏极区域中的至少一个上形成n型离子重掺杂层16。
再接着，参照图2中的步骤S6与图1所示，在栅极区域的n型离子重掺杂层16上形成栅极17a，源极区域的n型离子重掺杂层16上形成源极17b，以及漏极区域的n型离子重掺杂层16上形成漏极17c。
源极17b、漏极17c、栅极17a的材质可以为金属，例如Ti/Al/Ni/Au、Ni/Au等现有的导电材质，对应采用物理气相沉积法或化学气相沉积法形成。
本实施例中，由于p型半导体层15在对应凹槽13处具有凹陷区域，因而栅极17a中有部分位于凹陷区域。一些实施例中，p型半导体层15的上表面以及栅极17a的下表面也可以呈平坦状。
图6是本发明第二实施例的半导体结构的结构示意图。
参照图6与图1所示，本实施例二的半导体结构2与实施例一的半导体结构1大致相同，区别仅在于：源极17b与漏极17c接触沟道层11a，且源极17b与沟道层11a之间、漏极17c与沟道层11a之间都利用n型离子重掺杂层16形成欧姆接触。
对应地，本实施例二的半导体结构2的制作方法与实施例一的半导体结构1的制作方法大致相同，区别仅在于：步骤S5中，在异质结11的源极区域与漏极区域上形成n型离子重掺杂层16时，去除源极区域与漏极区域的p型半导体层15、过渡层14、原位绝缘层12以及势垒层11b，暴露沟道层11a。n型离子重掺杂层16使得源极17b与沟道层11a、漏极17c与沟道层11a都可不通过高温热退火直接形成欧姆接触层。
一些实施例中，源极17b与漏极17c接触沟道层11a，且源极17b与沟道层11a之间、或漏极17c与沟道层11a之间利用n型离子重掺杂层16形成欧姆接触。未设置n型离子重掺杂层16的沟道层11a与源极17b、或未设置n型离子重掺杂层16的沟道层11a与漏极17c可通过高温退火形成欧姆接触层。
图7是本发明第三实施例的半导体结构的结构示意图。图8是本发明第三实施例的半导体结构的制作方法的流程图。
参照图7、图1与图6所示，本实施例三的半导体结构3与实施例一、实施例二的半导体结构1、2大致相同，区别仅在于：过渡层14上，仅栅极 区域具有p型半导体层15。
对应地，参照图8与图2所示，本实施例三的半导体结构3的制作方法与实施例一、实施例二的半导体结构1、2的制作方法大致相同，区别仅在于：步骤S4'中，还包括：图形化p型半导体层15的步骤。换言之，步骤S4'包括：在凹槽13内以及原位绝缘层12上依次形成过渡层14与p型半导体层15；图形化p型半导体层15，仅保留栅极区域的p型半导体层15。
图形化p型半导体层15可以采用干法刻蚀或湿法刻蚀实现。相对于对直接形成在势垒层11b上的p型半导体层15进行图形化的方案，原位绝缘层12与过渡层14可防止图形化工艺中的过刻蚀损伤势垒层11b。
图9是本发明第四实施例的半导体结构的结构示意图。参照图9、图1、图6与图7所示，本实施例四的半导体结构4与实施例一、二、三的半导体结构1、2、3大致相同，区别仅在于：半导体结构4为中间半导体结构，未制作栅极17a、源极17b与漏极17c。
对应地，本实施例四的半导体结构4的制作方法与实施例一、二、三的半导体结构1、2、3的制作方法大致相同，区别仅在于：省略步骤S6。
半导体结构4也可以做为半成品生产与销售。
图10是本发明第五实施例的半导体结构的结构示意图。图11是本发明第五实施例的半导体结构的制作方法的流程图。图12是图11中的流程对应的中间结构示意图。
参照图10所示，半导体结构5包括：
自下而上分布的半导体衬底10、异质结11、原位绝缘层12以及过渡层14；
贯穿原位绝缘层12与过渡层14的凹槽13；
位于凹槽13内以及过渡层14上的p型半导体层15；
位于栅极区域的p型半导体层15上、以及异质结11的源极区域与漏极区域上的n型离子重掺杂层16；
位于栅极区域的n型离子重掺杂层16上的栅极17a，位于源极区域的n型离子重掺杂层16上的源极17b，以及位于漏极区域的n型离子重掺杂层16上的漏极17c。
参照图10、图12与图1所示，本实施例五的半导体结构5与实施例一的半导体结构1大致相同，区别仅在于：凹槽13贯穿原位绝缘层12与过渡层14，即过渡层14仅位于凹槽13外的原位绝缘层12上。
对应地，参照图11、图12与图2所示，本实施例五的半导体结构5的制作方法与实施例一的半导体结构1的制作方法大致相同，区别仅在于：步骤S2'包括：在异质结11上依次形成原位绝缘层12与过渡层14；步骤S3'包括：形成贯穿原位绝缘层12与过渡层14的凹槽13；步骤S4"包括：在凹槽13内以及过渡层14上形成p型半导体层15。
图10中，源极17b与漏极17c接触势垒层11b，且源极17b与势垒层11b之间、漏极17c与势垒层11b之间都利用n型离子重掺杂层16形成欧姆接触；栅极17a与p型半导体层15之间利用n型离子重掺杂层16也形成欧姆接触。n型离子重掺杂层16能使源极17b与异质结11的源极区域、漏极17c与异质结11的漏极区域、栅极17a与栅极区域的p型半导体层15不通过高温退火即可直接形成欧姆接触层。
一些实施例中，也可以栅极区域的p型半导体层15上、异质结11的源极区域与漏极区域中的至少一个上具有n型离子重掺杂层16。未设置n型离子重掺杂层16的栅极区域的p型半导体层15与栅极17a、未设置n型离子重掺杂层16的异质结11的源极区域与源极17b、或未设置n型离子重掺杂层16的异质结11的漏极区域与漏极17c通过高温退火形成欧姆接触层。
上述半导体结构5中，原位绝缘层12与过渡层14减小了沟道泄漏到 栅极17a形成的栅泄漏电流，因而异质结11中的势垒层11b的厚度可以较小，从而可以降低阈值电压；此外，由于原位绝缘层12的设置，可降低面电阻，增加二维电子气的浓度，从而提高了栅极对沟道的控制能力，提升工作电流。
此外，现有的AlGaN势垒层/GaN沟道层的HEMT结构中，势垒层11b的厚度为15nm～25nm才能保证有足够浓度的二维电子气产生。而本申请中，势垒层11b的厚度范围为1nm～15nm时，就能产生足够浓度的二维电子气；较佳地，可将势垒层11b的厚度控制在10nm以下。
图13是本发明第六实施例的半导体结构的结构示意图。
参照图13与图10所示，本实施例六的半导体结构6与实施例五的半导体结构5大致相同，区别仅在于：源极17b与漏极17c接触沟道层11a，且源极17b与沟道层11a之间、漏极17c与沟道层11a之间都利用n型离子重掺杂层16形成欧姆接触。
对应地，本实施例六的半导体结构6的制作方法与实施例五的半导体结构5的制作方法大致相同，区别仅在于：步骤S5中，在异质结11的源极区域与漏极区域上形成n型离子重掺杂层16时，去除源极区域与漏极区域的p型半导体层15、过渡层14、原位绝缘层12以及势垒层11b，暴露沟道层11a。n型离子重掺杂层16使得源极17b与沟道层11a、漏极17c与沟道层11a都可不通过高温热退火直接形成欧姆接触层。
一些实施例中，源极17b与漏极17c接触沟道层11a，且源极17b与沟道层11a之间、或漏极17c与沟道层11a之间利用n型离子重掺杂层16形成欧姆接触。未设置n型离子重掺杂层16的沟道层11a与源极17b、或未设置n型离子重掺杂层16的沟道层11a与漏极17c可通过高温退火形成欧姆接触层。
图14是本发明第七实施例的半导体结构的结构示意图。
参照图14、图10与图13所示，本实施例七的半导体结构7与实施例 五、实施例六的半导体结构5、6大致相同，区别仅在于：过渡层14上，仅栅极区域具有p型半导体层15。
对应地，本实施例七的半导体结构7的制作方法与实施例五、实施例六的半导体结构5、6的制作方法大致相同，区别仅在于：步骤S4"中，还包括：图形化p型半导体层15的步骤。换言之，步骤S4"包括：在凹槽13内以及过渡层14上形成p型半导体层15；图形化p型半导体层15，仅保留栅极区域的p型半导体层15。
图形化p型半导体层15可以采用干法刻蚀或湿法刻蚀实现。相对于对直接形成在势垒层11b上的p型半导体层15进行图形化的方案，原位绝缘层12与过渡层14可防止图形化工艺中的过刻蚀损伤势垒层11b。
图15是本发明第八实施例的半导体结构的结构示意图。参照图15、图10、图13与图14所示，本实施例八的半导体结构8与实施例五、六、七的半导体结构5、6、7大致相同，区别仅在于：半导体结构8为中间半导体结构，未制作栅极17a、源极17b与漏极17c。
对应地，本实施例八的半导体结构8的制作方法与实施例五、六、七的半导体结构5、6、7的制作方法大致相同，区别仅在于：省略步骤S6。
半导体结构8也可以做为半成品生产与销售。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (25)

  1. 一种半导体结构，其特征在于，包括：
    自下而上分布的半导体衬底(10)、异质结(11)以及原位绝缘层(12)；
    贯穿所述原位绝缘层(12)的凹槽(13)；
    至少位于所述原位绝缘层(12)上的过渡层(14)；
    位于所述凹槽(13)内以及所述过渡层(14)上的栅极区域的p型半导体层(15)；
    位于所述栅极区域的p型半导体层(15)上，和/或所述异质结(11)的源极区域上，和/或所述异质结(11)的漏极区域上的n型离子重掺杂层(16)。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述n型离子重掺杂层(16)的材料包括Ⅲ族氮化物材料。
  3. 根据权利要求1所述的半导体结构，其特征在于，所述过渡层(14)还位于所述凹槽(13)内。
  4. 根据权利要求1所述的半导体结构，其特征在于，所述过渡层(14)上的非栅极区域也具有所述p型半导体层(15)。
  5. 根据权利要求1所述的半导体结构，其特征在于，所述异质结(11)自下而上包括沟道层(11a)与势垒层(11b)。
  6. 根据权利要求5所述的半导体结构，其特征在于，所述n型离子重掺杂层(16)接触所述沟道层(11a)或所述势垒层(11b)。
  7. 根据权利要求1所述的半导体结构，其特征在于，所述异质结(11)包括Ⅲ族氮化物材料。
  8. 根据权利要求1所述的半导体结构，其特征在于，所述原位绝缘层(12)为单层结构，所述单层结构的材料包括：SiN、AlN中的一种或多种的混合物；或所述原位绝缘层(12)为叠层结构，所述叠层结构自下而上包括：SiN层与AlN层，AlN层与SiN层，或SiN层、AlN层与SiN层；
    和/或所述过渡层(14)为单层结构，所述单层结构的材料包括：AlN、 SiAlN、AlGaN中的一种或多种的混合物；或所述过渡层(14)为叠层结构，所述叠层结构包括：AlN层、SiAlN层、AlGaN层中的至少两层。
  9. 根据权利要求1所述的半导体结构，其特征在于，所述半导体结构还包括：位于所述栅极区域的n型离子重掺杂层(16)上的栅极(17a)，位于所述源极区域的n型离子重掺杂层(16)上的源极(17b)，以及位于所述漏极区域的n型离子重掺杂层(16)上的漏极(17c)。
  10. 一种半导体结构的制作方法，其特征在于，包括：
    提供半导体衬底(10)，在所述半导体衬底(10)上形成异质结(11)；
    在所述异质结(11)上形成原位绝缘层(12)；
    形成贯穿所述原位绝缘层(12)的凹槽(13)；
    在所述凹槽(13)内以及所述原位绝缘层(12)上依次形成过渡层(14)与p型半导体层(15)；
    在所述栅极区域的p型半导体层(15)上，和/或所述异质结(11)的源极区域上，和/或所述异质结(11)的漏极区域上形成n型离子重掺杂层(16)。
  11. 根据权利要求10所述的半导体结构的制作方法，其特征在于，所述n型离子重掺杂层(16)的材料包括Ⅲ族氮化物材料。
  12. 根据权利要求10所述的半导体结构的制作方法，其特征在于，还包括：图形化所述p型半导体层(15)，保留所述栅极区域的p型半导体层(15)。
  13. 根据权利要求10所述的半导体结构的制作方法，其特征在于，所述异质结(11)自下而上包括沟道层(11a)与势垒层(11b)。
  14. 根据权利要求13所述的半导体结构的制作方法，其特征在于，所述n型离子重掺杂层(16)接触所述沟道层(11a)或所述势垒层(11b)。
  15. 根据权利要求10所述的半导体结构的制作方法，其特征在于，所述异质结(11)包括Ⅲ族氮化物材料。
  16. 根据权利要求10所述的半导体结构的制作方法，其特征在于，所述原位绝缘层(12)为单层结构，所述单层结构的材料包括：SiN、AlN中的一种或多种的混合物；或所述原位绝缘层(12)为叠层结构，所述叠层结构自 下而上包括：SiN层与AlN层，AlN层与SiN层，或SiN层、AlN层与SiN层；
    和/或所述过渡层(14)为单层结构，所述单层结构的材料包括：AlN、SiAlN、AlGaN中的一种或多种的混合物；或所述过渡层(14)为叠层结构，所述叠层结构包括：AlN层、SiAlN层、AlGaN层中的至少两层。
  17. 根据权利要求10所述的半导体结构的制作方法，其特征在于，还包括：在所述栅极区域的n型离子重掺杂层(16)上形成栅极(17a)，在所述源极区域的n型离子重掺杂层(16)上形成源极(17b)，以及在所述漏极区域的n型离子重掺杂层(16)上形成漏极(17c)。
  18. 一种半导体结构的制作方法，其特征在于，包括：
    提供半导体衬底(10)，在所述半导体衬底(10)上形成异质结(11)；
    在所述异质结(11)上依次形成原位绝缘层(12)与过渡层(14)；
    形成贯穿所述原位绝缘层(12)与所述过渡层(14)的凹槽(13)；
    在所述凹槽(13)内以及所述过渡层(14)上形成p型半导体层(15)；
    在所述栅极区域的p型半导体层(15)上，和/或所述异质结(11)的源极区域上，和/或所述异质结(11)的漏极区域上形成n型离子重掺杂层(16)。
  19. 根据权利要求18所述的半导体结构的制作方法，其特征在于，所述n型离子重掺杂层(16)的材料包括Ⅲ族氮化物材料。
  20. 根据权利要求18所述的半导体结构的制作方法，其特征在于，还包括：图形化所述p型半导体层(15)，保留所述栅极区域的p型半导体层(15)。
  21. 根据权利要求18所述的半导体结构的制作方法，其特征在于，所述异质结(11)自下而上包括沟道层(11a)与势垒层(11b)。
  22. 根据权利要求21所述的半导体结构的制作方法，其特征在于，所述n型离子重掺杂层(16)接触所述沟道层(11a)或所述势垒层(11b)。
  23. 根据权利要求18所述的半导体结构的制作方法，其特征在于，所述异质结(11)包括Ⅲ族氮化物材料。
  24. 根据权利要求18所述的半导体结构的制作方法，其特征在于，所述 原位绝缘层(12)为单层结构，所述单层结构的材料包括：SiN、AlN中的一种或多种的混合物；或所述原位绝缘层(12)为叠层结构，所述叠层结构自下而上包括：SiN层与AlN层，AlN层与SiN层，或SiN层、AlN层与SiN层；
    和/或所述过渡层(14)为单层结构，所述单层结构的材料包括：AlN、SiAlN、AlGaN中的一种或多种的混合物；或所述过渡层(14)为叠层结构，所述叠层结构包括：AlN层、SiAlN层、AlGaN层中的至少两层。
  25. 根据权利要求18所述的半导体结构的制作方法，其特征在于，还包括：在所述栅极区域的n型离子重掺杂层(16)上形成栅极(17a)，在所述源极区域的n型离子重掺杂层(16)上形成源极(17b)，以及在所述漏极区域的n型离子重掺杂层(16)上形成漏极(17c)。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709321A (zh) * 2012-04-20 2012-10-03 程凯 增强型开关器件及其制造方法
CN107946358A (zh) * 2017-11-21 2018-04-20 华南理工大学 一种与Si‑CMOS工艺兼容的AlGaN/GaN异质结HEMT器件及其制作方法
CN108155099A (zh) * 2017-12-22 2018-06-12 中国科学院苏州纳米技术与纳米仿生研究所 一种包含介质层的p型栅HEMT器件及其制作方法
CN108649071A (zh) * 2018-05-17 2018-10-12 苏州汉骅半导体有限公司 半导体器件及其制造方法
WO2018223387A1 (zh) * 2017-06-09 2018-12-13 苏州晶湛半导体有限公司 一种增强型开关器件及其制造方法
CN109346522A (zh) * 2018-11-21 2019-02-15 芜湖启迪半导体有限公司 一种半导体结构及其形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709321A (zh) * 2012-04-20 2012-10-03 程凯 增强型开关器件及其制造方法
WO2018223387A1 (zh) * 2017-06-09 2018-12-13 苏州晶湛半导体有限公司 一种增强型开关器件及其制造方法
CN107946358A (zh) * 2017-11-21 2018-04-20 华南理工大学 一种与Si‑CMOS工艺兼容的AlGaN/GaN异质结HEMT器件及其制作方法
CN108155099A (zh) * 2017-12-22 2018-06-12 中国科学院苏州纳米技术与纳米仿生研究所 一种包含介质层的p型栅HEMT器件及其制作方法
CN108649071A (zh) * 2018-05-17 2018-10-12 苏州汉骅半导体有限公司 半导体器件及其制造方法
CN109346522A (zh) * 2018-11-21 2019-02-15 芜湖启迪半导体有限公司 一种半导体结构及其形成方法

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