WO2023273252A1 - N极性GaN晶体管结构的制备方法和半导体结构 - Google Patents

N极性GaN晶体管结构的制备方法和半导体结构 Download PDF

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WO2023273252A1
WO2023273252A1 PCT/CN2021/141765 CN2021141765W WO2023273252A1 WO 2023273252 A1 WO2023273252 A1 WO 2023273252A1 CN 2021141765 W CN2021141765 W CN 2021141765W WO 2023273252 A1 WO2023273252 A1 WO 2023273252A1
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layer
barrier layer
polar
epitaxial
polarity
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French (fr)
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李成果
曾巧玉
尹雪兵
葛晓明
陈志涛
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广东省科学院半导体研究所
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Definitions

  • the present application relates to the field of GaN-based electronic devices, in particular, to a method for preparing an N-polarity GaN transistor structure and a semiconductor structure.
  • Polarity is one of the very important properties of III-V nitride semiconductor materials.
  • Traditional GaN-based electronic and optoelectronic devices are based on Ga polar materials.
  • electronic devices based on N-polar GaN materials can have lower contact resistance, stronger high-voltage resistance, higher power density and efficiency, Advantages of more flexible structural design and size miniaturization.
  • the excellent performance of N-polar Ga(Al)N transistors in the fields of power switching and radio frequency amplification has gradually aroused great interest in academia and industry.
  • N-polarity HEMT devices exhibit ultra-low dynamic on-resistance ( ⁇ 5%) and extremely high breakdown voltage (>2000V); in the field of radio frequency amplification, N-polarity HEMT It achieves ultra-high power density (8W/mm) and power-added efficiency (27.8%), far superior to any current Ga polar devices of the same kind.
  • N-polar GaN materials are mostly based on the direct growth of metal-organic vapor phase epitaxy or molecular beam epitaxy on sapphire or SiC substrates.
  • the material has high surface roughness, poor crystal quality, and high impurity concentration, and it is difficult to obtain a material with a steep interface.
  • the AlGaN/GaN heterojunction and high-resistance GaN insulating layer lead to the problems of high channel resistance and large off-state leakage of the N-polar GaN high electron mobility transistor.
  • the present application provides a method for preparing an N-polarity GaN transistor structure and a semiconductor structure, which can obtain an N-polarity GaN high electron mobility transistor with a heterojunction having a high-resistance GaN insulating layer and a steep interface, and improve device performance.
  • Some embodiments of the present application provide a method for fabricating an N-polarity GaN transistor structure, which may include:
  • An epitaxial functional layer of an upside-down N-polar transistor is deposited on the side of the etch barrier layer away from the structural substrate, so that the side of the epitaxial functional layer far away from the structural substrate is Ga Polar face;
  • a source, a drain and a gate are formed on the side of the epitaxial functional layer away from the support substrate to form an N-polarity GaN transistor.
  • the step of removing the buffer layer and exposing the etching barrier layer, the preparation method may also include:
  • the etching blocking barrier layer is removed, and the epitaxial functional layer is exposed.
  • the step of depositing an epitaxial functional layer of an upside-down N-polarity transistor on the side of the etching barrier layer away from the structural substrate may include:
  • a Ga polarity insulating layer is deposited on the isolation layer.
  • the preparation material of the channel layer may include at least one of GaN, AlN, InAlN, AlGaN, and InAlGaN; and the preparation material of the barrier layer may include AlN, InAlN, AlGaN , InAlGaN, AlScN at least one material.
  • the forbidden band width of the barrier layer is larger than the forbidden band width of the channel layer, and a high-concentration, high electron migration is formed on the interface between the barrier layer and the channel layer near the channel layer. rate two-dimensional electron gas.
  • the preparation method may further include:
  • the p-type doped layer is made of p-GaN material.
  • the step of forming a supporting substrate by bonding on the side of the epitaxial functional layer away from the structural substrate may include:
  • the supporting substrate is bonded on the bonding layer.
  • the bonding layer may be deposited on the surface of the p-type doped layer away from the structural substrate, and the bonding layer may be bonded by direct bonding or adhesive bonding.
  • the epitaxial functional layer is bonded to the supporting substrate.
  • the etching barrier layer may be AlxGa1 - xN , where x is the composition of Al, and 0 ⁇ x ⁇ 1; the Al group in the etching barrier layer higher than the Al composition in the channel layer.
  • the thickness of the etch barrier layer may be at least 1 nm.
  • inventions of the present application provide a semiconductor structure, which is fabricated by using the method for preparing an N-polarity GaN transistor structure as described in any of the foregoing embodiments, and may include:
  • the epitaxial functional layer located on one side of the etching barrier layer, wherein the side of the epitaxial functional layer close to the etching barrier layer is an N polar surface, and the epitaxial functional layer is far away from the etching
  • One side of the etch-stop barrier layer is a Ga polar plane
  • a supporting substrate located on the side of the Ga polar surface of the epitaxial functional layer
  • a source, a drain and a gate located on the side of the N polar surface of the epitaxial functional layer
  • the epitaxial functional layer includes a channel layer deposited on the etching barrier layer, a barrier layer deposited on the channel layer, and an isolation layer deposited on the barrier layer. layer and an insulating layer deposited on the isolation layer.
  • the epitaxial functional layer may further include a p-type doped layer on the insulating layer.
  • the p-type doped layer is bonded to the supporting substrate, wherein a bonding layer is formed between the p-type doped layer and the supporting substrate.
  • the etching stopper layer is partially or completely removed in regions on both sides of the gate.
  • the gate is formed on the etching stopper layer, and the source and the drain are formed on channel layers on both sides of the gate.
  • the beneficial effects of the embodiments of the present application may at least include, for example:
  • the preparation method of the N-polarity GaN transistor structure provided by the embodiment of the present application is to form a Ga-polarity epitaxial functional layer by deposition, and bond the epitaxial functional layer to form a supporting substrate, and then remove the structural lining after inverting the epitaxial structure. bottom and buffer layers, and make source, drain and gate on the side of the exposed epitaxial functional layer away from the supporting substrate to form N-polarity GaN transistors.
  • the epitaxial structure of the N-polar GaN transistor is obtained by inverting the directly grown Ga-polar epitaxial layer upside down, its material quality is higher than that of the N-polar material directly grown by epitaxial growth, and a high-resistance GaN insulating layer and steep
  • the heterojunction of the interface can enhance the high-voltage withstand capability of the N-polar GaN transistor and reduce the conduction loss of the device.
  • this application adopts the method of first growing a Ga polar epitaxial structure and then removing the substrate and buffer layer through bonding, which can solve the problem of poor quality of direct epitaxial growth of N-polar GaN transistor structure materials, and improve the N-polar The overall performance of the transistor.
  • FIG. 1 is a block diagram of steps of a method for preparing an N-polarity GaN transistor structure provided in an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of a semiconductor structure provided in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an enhanced semiconductor structure provided in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of an integrated structure of a semiconductor structure provided by an embodiment of the present application and other devices.
  • Icon 100-semiconductor structure; 110-supporting substrate; 111-bonding layer; 130-epitaxial functional layer; 131-channel layer; 133-barrier layer; 135-isolating layer; 137-insulating layer; 139-p type doped layer; 150-etching stop barrier layer; 160a-source; 160b-drain; 160c-gate; 170-buffer layer; 180-structural substrate.
  • the directly grown Ga-polar GaN material has good overall quality, which is usually better than the directly grown N-polar GaN material, that is, the GaN material obtained by Ga-polar growth has low surface roughness, good crystal quality, low impurity concentration, and low background Electron concentration is low.
  • N-polar GaN materials are usually grown directly on sapphire or SiC substrates by metal-organic vapor phase epitaxy or molecular beam epitaxy.
  • the GaN materials obtained by this method have high surface roughness, poor crystal quality, High impurity concentration and high background electron concentration are required to manufacture high-resistance insulating layers and steep heterojunction interfaces required for N-polar high electron mobility transistors, making it difficult to fully utilize the advantages of N-polar GaN materials in device applications .
  • the present application provides a method for preparing an N-polarity GaN transistor structure and a semiconductor structure, which can obtain a heterojunction N-polarity GaN high electron mobility transistor with a high-resistance GaN insulating layer and a steep interface, and improve device performance. It should be noted that, in the case of no conflict, the features in the embodiments of the present application may be combined with each other.
  • this embodiment provides a method for preparing an N-polarity GaN transistor structure.
  • the Ga-polarity epitaxial structure is first grown, and then the method of bonding and removing the substrate and buffer layer 170 is used to obtain an inverted N-polarity GaN transistor structure.
  • Polar devices, and make N-polar semiconductor devices have better material quality.
  • the method for preparing an N-polarity GaN transistor structure is used to prepare and form a semiconductor structure 100, and the semiconductor structure 100 is suitable for an N-polarity GaN-based high electron mobility transistor (HEMT, High Electron Mobility Transistor) device.
  • the semiconductor structure 100 may be an enhanced N-polarity GaN-based HEMT structure, or a depletion-type N-polarity GaN-based HEMT structure.
  • HEMT High Electron Mobility Transistor
  • its structure can refer to the HEMT device of the related art.
  • S1 Deposit and form a buffer layer 170 on one side of the structural substrate 180 .
  • the structural substrate 180 may be one or a combination of Si, Sapphire, SiC, GaN, or any other material capable of growing III-nitrides.
  • the deposition method of the structural substrate 180 can be CVD (Chemical Vapor Deposition, chemical vapor deposition), VPE (Vapor Phase Epitaxy, vapor phase epitaxy), MOVPE (Metal-organic Vapor Phase Epitaxy, metal-organic vapor epitaxy), LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition), PLD (Pulsed Laser Deposition, pulsed laser deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy, molecular beam epitaxy), sputtering, evaporation, etc.
  • CVD Chemical Vapor Deposition, chemical vapor deposition
  • VPE Vapor Phase Epitaxy
  • MOVPE Metal-organic Vapor
  • the structural substrate 180 is preferably made of Si (111) material, so as to facilitate the realization of substrate peeling in subsequent manufacturing processes.
  • the buffer layer 170 serves as a transition layer between the subsequent GaN epitaxial structure and the structural substrate 180 during growth, and solves problems such as lattice mismatch and thermal expansion coefficient mismatch between the GaN thin film and the structural substrate 180 materials.
  • the buffer layer 170 may use at least one material among GaN, AlN, InAlN, AlGaN, InAlGaN or other semiconductor materials.
  • the buffer layer 170 can be made of at least one of AlGaN or AlN.
  • S2 Deposit and form an etching stop barrier layer 150 on a side of the buffer layer 170 away from the structural substrate 180 .
  • the etch-stop barrier layer 150 mainly functions as a barrier in the subsequent etching process to form a natural barrier layer to block etching.
  • the etch barrier layer 150 may preferably use Al x Ga 1-x N, where x is the composition of Al, and 0 ⁇ x ⁇ 1.
  • the etching barrier layer 150 needs to be heterogeneous with the buffer layer 170 on the side close to the barrier layer, so that the etching barrier layer 150 can be used as an etching stop layer when the buffer layer 170 is etched, and the etching
  • the selection of materials for the etch-stop barrier layer 150 is only for illustration and does not play a limiting role, but any material that can achieve the effect of etching stop here is within the scope of protection of the present application.
  • the thickness of the barrier layer of etching 150 is relatively thin. Specifically, the thickness of the etching stop barrier layer 150 is at least 1 nm, preferably 2 nm.
  • the epitaxial functional layer 130 of an upside-down N-polarity transistor is deposited on the etch barrier layer 150 by using a conventional deposition method.
  • the epitaxial functional layer 130 may include a channel layer 131 , a barrier layer 133 , an isolation layer 135 , an insulating layer 137 and a p-type doped layer 139 deposited in sequence.
  • the buffer layer 170 and the etch barrier layer 150 are also grown in Ga polarity, and the side of the epitaxial functional layer 130 away from the structural substrate 180 is Ga polar.
  • the side of the epitaxial functional layer 130 away from the support substrate 110 is the N polarity side.
  • the epitaxial structures such as the buffer layer 170 , the etching stop barrier layer 150 , and the epitaxial functional layer 130 are directly and sequentially grown by MOVPE or MBE methods.
  • step S3 may specifically include the following sub-steps:
  • the channel layer 131 is used to provide a channel for two-dimensional electron gas (2DEG) movement, and the preparation material of the channel layer 131 includes nitride, for example, GaN, AlN, InAlN, AlGaN, InAlGaN or other semiconductor materials. At least one material, preferably, the channel layer 131 may be GaN or AlGaN material with low Al composition.
  • 2DEG two-dimensional electron gas
  • S32 depositing and forming a Ga-polarity barrier layer 133 on the channel layer 131 .
  • the barrier layer 133 covers the channel layer 131 for forming a heterojunction with the channel layer 131, and the preparation material of the barrier layer 133 includes ternary nitride, for example, includes AlN, InAlN, AlGaN, At least one of InAlGaN or other semiconductor materials.
  • the barrier layer 133 has a wider energy gap than the channel layer 131, so as to form a high-concentration, high-electron-mobility two-dimensional Electron gas; for example, when the material of the channel layer 131 is GaN, the barrier layer 133 can be InAlN, AlGaN or AlN.
  • the isolation layer 135 is used to isolate the barrier layer 133 from the subsequently deposited insulating layer 137 , which may be a GaN material grown without intentional doping.
  • the insulating layer 137 has a high resistance characteristic, which can be achieved through self-doping of carbon or intentional doping of iron during the growth of GaN material.
  • the p-type doped layer 139 can be made of conventional p-GaN material, which can improve the vertical high voltage withstand capability of the device.
  • the p-type doped layer 139 is the outermost structure of the epitaxial functional layer 130.
  • step S45 can also be omitted, thereby eliminating the p-type doped layer 139.
  • the insulating layer 137 is used as the outermost structure of the epitaxial functional layer 130 .
  • the p-type doped layer 139 is the outermost layer structure of the epitaxial functional layer 130 .
  • the p-type doped layer 139 is exposed to facilitate annealing activation after doping.
  • the p-type doped layer 139 is Mg-doped Ga(Al)N, it must be exposed to high temperature for annealing to realize p-type conduction.
  • the p-type doped layer 139 of N polarity is grown directly on the substrate as usual and then the epitaxial functional layer 130 of the N-polar transistor is grown, the p-type doped layer 139 is buried under the epitaxial functional layer 130, so that the annealing It is difficult to activate the dopant source to achieve p-type conduction.
  • steps S41 to S45 all use MOVPE or MBE methods to directly grow a Ga polar epitaxial layer structure, wherein the Ga polar direction is from the structural substrate 180 to the p-type doped layer 139 .
  • a bonding layer 111 is deposited on the epitaxial functional layer 130 to form a bonding layer 111 , and the supporting substrate 110 is bonded to the bonding layer 111 . That is, the bonding layer 111 [10] is deposited on the surface of the p-type doped layer 139 away from the structural substrate 180, and the epitaxial functional layer 130 is bonded to the supporting substrate 110 by direct bonding or adhesive bonding. .
  • the material of the supporting substrate 110 may be Si, SOI, silicon carbide, diamond, and the like. Meanwhile, the selection of the material of the bonding layer 111 is related to the bonding process. For example, when direct bonding with the SOI substrate is selected, the bonding layer 111 may be made of silicon oxide or silicon nitride.
  • the bonding method here can be combined with materials with high thermal conductivity (SiC, diamond, etc.), thereby improving the heat dissipation capability and thermal reliability of the device.
  • other devices such as Si-based CMOS devices can be prepared in advance on the SOI substrate.
  • the combination of Si and SOI substrates can be realized through the bonding method, and Si-based CMOS devices can also be integrated on the SOI substrate. And other devices, thus realizing the integration of different devices.
  • the device is turned upside down, and the structural substrate 180 is peeled off.
  • the N polarity direction is from the supporting substrate 110 to the etching stop barrier layer 150 .
  • the peeling method of the structural substrate 180 is related to the selected material. remove.
  • other conventional substrate lift-off methods such as laser lift-off, can also be used here.
  • the buffer layer 170 is etched and removed first, thereby exposing the etching barrier to obtain an N-polarity GaN-based HEMT device structure, where the etching barrier layer 150 can realize a self-terminated etching process .
  • the etching stop barrier layer 150 may be removed or partially removed, or may not be removed.
  • FIG. 8 shows the case where the etch stop barrier layer 150 is partially removed. When a portion of the etch stop barrier layer 150 is removed, only a portion of the gate region remains.
  • S7 Fabricate the source 160a, the drain 160b and the gate 160c on the side of the epitaxial functional layer 130 away from the support substrate 110 .
  • the source 160a, the drain 160b and the gate 160c are fabricated according to a conventional process on the surface of the channel layer 131 away from the support substrate 110, wherein The gate 160c is located between the source 160a and the drain 160b.
  • the source 160 a , the drain 160 b and the gate 160 c are formed on the surface of the etching barrier layer 150 .
  • a gate 160 c is formed on the surface of the etching barrier layer 150
  • a source 160 a and a drain 160 b are formed on the surface of the channel layer 131 .
  • an N-polar N-polar GaN-based HEMT structure is obtained, which can form an enhanced N-polar GaN-based HEMT structure or a depletion-type N-pole according to the difference in the fabrication of the metal electrode.
  • permanent GaN-based HEMT structure When forming a depleted N-polar GaN-based HEMT structure, it is preferred to remove the etching barrier layer 150; when forming an enhanced N-polar GaN-based HEMT structure, it is necessary to first partially remove the etching barrier layer 150, Only part of the gate region is reserved, and the thickness and Al composition of the channel layer 131 and barrier layer 133 are adjusted accordingly to deplete the two-dimensional electronic gas.
  • this layer can also serve as a barrier layer for reducing device leakage when forming the source 160a, the drain 160b and the gate 160c.
  • this embodiment also provides a semiconductor structure 100, which is fabricated by using the aforementioned method for preparing an N-polarity GaN transistor structure.
  • the semiconductor structure 100 may include an etching barrier layer 150, located Etching the epitaxial functional layer 130 on the side of the barrier layer 150, the supporting substrate 110 located on the side of the Ga polar surface of the epitaxial functional layer 130, the source electrode 160a located on the side of the N polar surface of the epitaxial functional layer 130, The drain 160b and the gate 160c, wherein the side of the epitaxial functional layer 130 close to the etching barrier layer 150 is an N polarity plane, and the side of the epitaxial functional layer 130 away from the etching barrier layer 150 is a Ga polarity noodle.
  • the semiconductor structure 100 in this embodiment is an N-polarity GaN-based HEMT structure, wherein the N-polarity direction is from the support substrate 110 to the epitaxial functional layer 130.
  • the epitaxial functional layer 130 includes a channel layer 131, a barrier layer 133, an isolation layer 135, an insulating layer 137 and a p-type doped layer 139, wherein the p-type doped layer 139 is bonded to the supporting substrate 110
  • a bonding layer 111 is formed between the p-type doped layer 139 and the supporting substrate 110 to achieve bonding.
  • the insulating layer 137 is located on the side of the p-type doped layer 139 away from the supporting substrate 110
  • the isolation layer 135 is located on the side of the insulating layer 137 away from the supporting substrate 110
  • the barrier layer 133 is located on the side of the insulating layer 135 away from the supporting substrate 110.
  • the channel layer 131 is located on the side of the barrier layer 133 away from the support substrate 110 .
  • the specific deposition method of the epitaxial functional layer 130 can refer to the foregoing description.
  • the etch barrier layer 150 may also be removed, that is, the semiconductor structure 100 includes an epitaxial functional layer 130, a supporting substrate 110 located on the side of the Ga polar surface of the epitaxial functional layer 130,
  • the source 160 a , the drain 160 b and the gate 160 c are located on the N polarity side of the epitaxial functional layer 130 . That is, the source electrode 160 a , the drain electrode 160 b and the gate electrode 160 c can be formed directly on the surface of the channel layer 131 .
  • the epitaxial functional layer 130 is bonded on the support substrate 110, and the support substrate 110 is also integrated with a Si-based CMOS device or a gate 160c driving circuit, so that the connection between different devices can be realized. integration.
  • this embodiment provides a method for fabricating an N-polarity GaN transistor structure and a semiconductor structure 100, forming a Ga-polarity epitaxial functional layer 130 by deposition, and bonding on the epitaxial functional layer 130 to form a supporting liner bottom 110, and then remove the structural substrate 180 and buffer layer 170 after inverting the epitaxial structure, and fabricate the source 160a, drain 160b and gate 160c on the side of the exposed epitaxial functional layer 130 away from the supporting substrate 110, so as to Form semiconductor devices.
  • Ga polar growth is used to form the epitaxial functional layer 130, and the overall quality of directly grown Ga polar GaN materials is usually better than that of directly grown N polar GaN materials, the direct growth of Ga polar epitaxial functional layer 130 , GaN materials with smooth surface, low impurity concentration, and high crystal quality can be obtained, and since the N polarity of the semiconductor structure 100 is opposite to the Ga polarity direction, the N The epitaxial functional layer 130 is formed on the polar surface, so as to obtain an N-polar epitaxial structure, and fabricate an N-polar semiconductor device.
  • a Ga polar epitaxial structure is first grown and then removed through bonding and substrate and buffer layer 170, so that the N polar semiconductor device has better material quality and device performance.
  • the present application provides a method for preparing an N-polarity GaN transistor structure and a semiconductor structure, which relate to the field of semiconductor technology.
  • a Ga-polarity epitaxial functional layer is formed by deposition, and a support substrate is formed by bonding on the epitaxial functional layer, and then the After the epitaxial structure is inverted, the structural substrate and buffer layer are removed, and the source, drain and gate are fabricated on the side of the exposed epitaxial functional layer away from the support substrate, so as to form an N-polarity GaN transistor structure.
  • the epitaxial structure of the N-polar GaN transistor is obtained by inverting the directly grown Ga-polar epitaxial layer upside down, and its material quality is higher than that of the N-polar material directly grown by epitaxial growth, and a high-resistance GaN insulating layer and a steep interface can be obtained.
  • the heterojunction can enhance the high-voltage resistance capability of the N-polar GaN transistor, reduce the conduction loss of the device, and improve the overall performance of the device.
  • the preparation method of the N-polar GaN transistor structure of this application can be reproduced by using the existing semiconductor process technology, and the N-polar GaN semiconductor structure provided by this application can be applied in various industrial fields, including radio frequency power amplifiers required in 5G communications components, high-power high-frequency switching devices required in power control and management, gas sensor devices, etc.

Abstract

本申请的实施例提供了一种N极性GaN晶体管结构的制备方法和半导体结构，涉及半导体技术领域，通过沉积形成Ga极性的外延功能层，并在外延功能层上键合形成支撑衬底，然后将该外延结构倒置后去除结构衬底和缓冲层，在暴露出的外延功能层远离支撑衬底的一侧制作源极、漏极和栅极，以形成N极性的GaN晶体管结构。其中，N极性GaN晶体管的外延结构由直接生长的Ga极性外延层上下倒置获得，其材料质量相比直接外延生长的N极性材料更高，能够得到高电阻的GaN绝缘层和陡峭界面的异质结，因而可增强N极性GaN晶体管的耐高压能力、减小器件导通损耗，提升器件整体性能。

Description

N极性GaN晶体管结构的制备方法和半导体结构
相关申请的交叉引用
本申请要求于2021年07月01日提交中国国家知识产权局的申请号为202110742866.X、名称为“N极性GaN晶体管结构的制备方法和半导体结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及GaN基电子器件领域，具体而言，涉及一种N极性GaN晶体管结构的制备方法和半导体结构。
背景技术
极性是三五族氮化物半导体材料非常重要的性质之一。传统GaN基电子及光电器件均基于Ga极性材料。然而，得益于与传统Ga极性材料相反的极化电场，基于N极性GaN材料的电子器件可具有更低的接触电阻、更强的耐高电压能力、更高的功率密度和效率、更灵活的结构设计优势和尺寸微缩优势。近年来，N极性Ga(Al)N晶体管在功率开关和射频放大领域的出色表现，逐渐引起学术界和产业界极大的兴趣。在功率开关方面，N极性HEMT器件展示了超低的动态导通电阻(～5％)和极高的击穿电压(>2000V)；在射频放大领域，N极性HEMT器件在94GHz频率下实现了超高的功率密度(8W/mm)和功率附加效率(27.8％)，远优于当前任何同类Ga极性器件。
高质量N极性GaN材料的制备是当前N极性器件的一大挑战。目前N极性GaN材料多基于在蓝宝石或者SiC衬底上采用金属有机气相外延或者分子束外延的方法直接生长得到，材料的表面粗糙度高、晶体质量差、杂质浓度高，难以得到具有陡峭界面的AlGaN/GaN异质结和高电阻的GaN绝缘层，导致N极性GaN高电子迁移率晶体管存在沟道电阻高、器件关态漏电大的问题。
发明内容
本申请提供了一种N极性GaN晶体管结构的制备方法和半导体结构，其能够得到具有高电阻GaN绝缘层和陡峭界面的异质结的N极性GaN高电子迁移率晶体管，提升器件性能。
本申请的一些实施方式提供了一种N极性GaN晶体管结构的制备方法，可以包括：
在结构衬底的一侧沉积形成缓冲层；
在所述缓冲层远离所述结构衬底的一侧沉积形成刻蚀阻挡势垒层；
在所述刻蚀阻挡势垒层远离所述结构衬底的一侧沉积形成上下倒置的N极性晶体管的外延功能层，以使所述外延功能层远离所述结构衬底的一侧为Ga极性面；
在所述外延功能层远离所述结构衬底的一侧键合形成支撑衬底；
去除所述结构衬底，并暴露出所述缓冲层；
去除所述缓冲层，并暴露出所述刻蚀阻挡势垒层；
在所述外延功能层远离所述支撑衬底的一侧制作源极、漏极和栅极，以形成N极性GaN晶体管。
在可选的实施方式中，去除所述缓冲层，并暴露出所述刻蚀阻挡势垒层的步骤，所述制备方法还可以包括：
去除所述刻蚀阻挡势垒层，并暴露出所述外延功能层。
在可选的实施方式中，在所述刻蚀阻挡势垒层远离所述结构衬底的一侧沉积形成上下倒置的N极性晶体管的外延功能层的步骤，可以包括：
在所述刻蚀阻挡势垒层上沉积形成Ga极性的沟道层；
在所述沟道层上沉积形成Ga极性的势垒层；
在所述势垒层上沉积形成Ga极性的隔离层；
在所述隔离层上沉积形成Ga极性的绝缘层。
在可选的实施方式中，所述沟道层的制备材料可以包括GaN、AlN、InAlN、AlGaN、InAlGaN中的至少一种材料；以及所述势垒层的制备材料可以包括AlN、InAlN、AlGaN、InAlGaN、AlScN中的至少一种材料。所述势垒层的禁带宽度大于所述沟道层的禁带宽度，在所述势垒层与所述沟道层靠近所述沟道层一侧的界面上形成高浓度、高电子迁移率的二维电子气。
在可选的实施方式中，在所述隔离层上沉积形成绝缘层的步骤之后，所述制备方法还可以包括：
在所述绝缘层上沉积形成p型掺杂层。
在可选的实施方式中，所述p型掺杂层采用p-GaN材料。
在可选的实施方式中，在所述外延功能层远离所述结构衬底的一侧键合形成支撑衬底的步骤，可以包括：
在所述外延功能层上沉积形成键合层；
将所述支撑衬底键合在所述键合层上。
在可选的实施方式中，可以在所述p型掺杂层远离所述结构衬底的一侧表面沉积形成所述键合层，以及可以通过直接键合或者胶接键合方法将所述外延功能层与所述支撑衬底键合。
在可选的实施方式中，所述刻蚀阻挡势垒层可以为Al xGa 1-xN，其中x为Al的组分，且0＜x≤1；所述刻蚀阻挡层中Al组分高于所述沟道层中的Al组分。
在可选的实施方式中，所述刻蚀阻挡势垒层的厚度可以为至少为1nm。
本申请的另一些实施方式提供了一种半导体结构，采用如前述一些实施方式中的任一实施方式所述的N极性GaN晶体管结构的制备方法制作而成，可以包括：
刻蚀阻挡势垒层；
位于所述刻蚀阻挡势垒层一侧的外延功能层，其中所述外延功能层的靠近所述刻蚀阻挡势垒层的一侧为N极性面，所述外延功能层远离所述刻蚀阻挡势垒层的一侧为Ga极性面；
位于所述外延功能层的Ga极性面一侧的支撑衬底；
位于所述外延功能层的N极性面一侧的源极、漏极和栅极；
其中，所述外延功能层包括在所述刻蚀阻挡势垒层上沉积形成的沟道层、在所述沟道层上沉积形成的势垒层、在所述势垒层上沉积形成的隔离层以及在所述隔离层上沉积形成的绝缘层。
在可选的实施方式中，所述外延功能层还可以包括位于所述绝缘层上的p型掺杂层。
在可选的实施方式中，所述p型掺杂层键合在所述支撑衬底上，其中，所述p型掺杂层与所述支撑衬底之间形成有键合层。
在可选的实施方式中，所述刻蚀阻挡层在栅极两侧区域部分或全部去除。
在可选的实施方式中，所述栅极制作在所述刻蚀阻挡层上，所述源极和所述漏极制作在所述栅极两侧的沟道层上。
本申请实施例的有益效果至少可以包括，例如：
本申请实施例提供的N极性GaN晶体管结构的制备方法，通过沉积形成Ga极性的外延功能层，并在外延功能层上键合形成支撑衬底，然后将该外延结构倒置后去除结构衬底和缓冲层，在暴露出的外延功能层远离支撑衬底的一侧制作源极、漏极和栅极，以形成N极性GaN晶体管。其中，由于N极性GaN晶体管的外延结构由直接生长的Ga极性外延层上下倒置获得，其材料质量相比直接外延生长的N极性材料更高，能够得到高电阻的GaN绝缘层和陡峭界面的异质结，因而可增强N极性GaN晶体管的耐高压能力、减小器件导通损耗。相较于相关技术，本申请采用先生长Ga极性外延结构再通过键合和衬底及缓冲层去除的方法，可解决直接外延生长N极性GaN晶体管结构材料质量差的难题，提升N极性晶体管的整体工作性能。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这 些附图获得其他相关的附图。
图1为本申请实施例提供的N极性GaN晶体管结构的制备方法的步骤框图；
图2至图6为本申请实施例提供的N极性GaN晶体管结构的制备方法的工艺流程图；
图7为本申请实施例提供的半导体结构的结构示意图；
图8为本申请实施例提供的增强型半导体结构的结构示意图；
图9为本申请实施例提供的半导体结构与其他器件的集成结构示意图。
图标：100-半导体结构；110-支撑衬底；111-键合层；130-外延功能层；131-沟道层；133-势垒层；135-隔离层；137-绝缘层；139-p型掺杂层；150-刻蚀阻挡势垒层；160a-源极；160b-漏极；160c-栅极；170-缓冲层；180-结构衬底。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本申请的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该申请产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，若出现术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
正如背景技术中所公开的，得益于与传统Ga极性材料相反的极化电场，基于N极性材料的电子器件可具有更低的接触电阻、更强的耐高电压能力、更高的功率密度和效率、更灵活的结构设计优势和尺寸微缩优势。而直接生长的Ga极性GaN材料综合质量好，通常优于直接生长的N极性GaN材料，即采用Ga极性生长得到的GaN材料的表面粗糙度低、晶体质量好、杂质浓度低、背景电子浓度低。
相关技术中，N极性GaN材料通常是基于在蓝宝石或者SiC衬底上采用金属有机气相外延或者分子束外延的方法直接生长得到，这种方法得到的GaN材料表面粗糙度高、晶体 质量差、杂质浓度高、背景电子浓度高，以制造N极性高电子迁移率晶体管所需要的高电阻绝缘层和陡峭的异质结界面，导致N极性的GaN材料优势难以在器件应用中完全发挥出来。
为了解决上述问题，本申请提供了一种N极性GaN晶体管结构的制备方法和半导体结构，能够得到具有高电阻GaN绝缘层和陡峭界面的异质结N极性GaN高电子迁移率晶体管，提升器件性能。需要说明的是，在不冲突的情况下，本申请的实施例中的特征可以相互结合。
具体实施例
参见图1，本实施例提供了一种N极性GaN晶体管结构的制备方法，采用先生长Ga极性外延结构，再通过键合和衬底及缓冲层170去除的方法，得到倒置后的N极性器件，并且使得N极性半导体器件具有更好的材料质量。
本实施例提供的N极性GaN晶体管结构的制备方法，用于制备形成半导体结构100，该半导体结构100适用于N极性GaN基高电子迁移率晶体管(HEMT，High Electron Mobility Transistor)器件。其中，基于该半导体结构100可以是增强型N极性GaN基HEMT结构，也可以是耗尽型N极性GaN基HEMT结构。其中，基于该半导体结构100制备形成的HEMT器件，其结构可参考相关技术的HEMT器件。
本实施例提供的N极性GaN晶体管结构的制备方法，可以包括以下步骤：
S1：在结构衬底180的一侧沉积形成缓冲层170。
结合参见图2，其中，结构衬底180可以是Si、Sapphire、SiC、GaN中的一种或多种的组合，或任何其他能够生长III族氮化物的材料。结构衬底180的沉积方法可以采用CVD(Chemical Vapor Deposition，化学气相沉积)、VPE(Vapour Phase Epitaxy，气相外延)、MOVPE(Metal-organic Vapor Phase Epitaxy，金属有机物气象外延生长)、LPCVD(Low Pressure Chemical Vapor Deposition，低压力化学气相沉积)、PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)、PLD(Pulsed Laser Deposition，脉冲激光沉积)、原子层外延、MBE(Molecular Beam Epitaxy，分子束外延)、溅射、蒸发等。
在本实施例中，结构衬底180优选采用Si(111)材料，从而方便后续制程中实现衬底剥离。
在本实施例中，缓冲层170在生长中作为后续GaN外延结构与结构衬底180之间的过渡层，解决GaN薄膜与结构衬底180材料间的晶格失配和热膨胀系数失配等问题。此处缓冲层170可以采用GaN、AlN、InAlN、AlGaN、InAlGaN或其它半导体材料中的至少一种材料。优选地，在结构衬底180采用Si(111)材料的基础上，缓冲层170可以采用AlGaN 或AlN中的至少一种。
S2：在缓冲层170远离结构衬底180的一侧沉积形成刻蚀阻挡势垒层150。
在本实施例中，刻蚀阻挡势垒层150主要由于在后续刻蚀制程中起到阻挡作用，以形成自然阻挡层，以阻挡刻蚀。刻蚀阻挡势垒层150可以优选采用Al xGa 1-xN，其中x为Al的组分，且0＜x≤1。当然，此处刻蚀阻挡势垒层150需要与缓冲层170靠近势垒层一侧的材料异质，以实现刻蚀缓冲层170时刻蚀阻挡势垒层150能够作为刻蚀停止层，且刻蚀阻挡势垒层150的材料选用仅仅是举例说明，并不起到限定作用，但凡是在此处能够实现刻蚀停止的作用的材料，均在本申请的保护范围之内。
需要说明是，为了避免刻蚀阻挡势垒层150影响后续的金属电极的制作，此处刻蚀阻挡势垒层150的厚度较薄。具体地，刻蚀阻挡势垒层150的厚度为至少1nm，优选为2nm。
S3：在刻蚀阻挡势垒层150远离结构衬底180的一侧沉积形成上下倒置的N极性晶体管的外延功能层130。
结合参见图3，具体地，利用常规的沉积方法，在刻蚀阻挡势垒层150上沉积形成上下倒置的N极性晶体管的外延功能层130。其中，外延功能层130可以包括依次沉积的沟道层131、势垒层133、隔离层135、绝缘层137和p型掺杂层139。同时，为了保证整个结构沉积过程中的统一性，缓冲层170和刻蚀阻挡势垒层150也均为Ga极性生长方式，且外延功能层130远离结构衬底180的一侧为Ga极性面，外延功能层130远离支撑衬底110的一侧为N极性面。
需要说明的是，本实施例中均采用MOVPE或MBE的方法直接依次生长出缓冲层170、刻蚀阻挡势垒层150和外延功能层130等外延结构。
在本实施例中，步骤S3具体可以包括以下子步骤：
S31：在刻蚀阻挡势垒层150上沉积形成Ga极性的沟道层131。
具体地，沟道层131用于提供二维电子气(2DEG)运动的沟道，沟道层131的制备材料包括氮化物，例如，包括GaN、AlN、InAlN、AlGaN、InAlGaN或其它半导体材料中的至少一种材料，优选地，沟道层131可以是GaN或者低Al组分的AlGaN材料。
S32：在沟道层131上沉积形成Ga极性的势垒层133。
具体地，势垒层133覆盖在沟道层131上，用于与沟道层131形成异质结，且势垒层133的制备材料包括三元氮化物，例如，包括AlN、InAlN、AlGaN、InAlGaN或其它半导体材料中的至少一种材料。此处势垒层133具有比沟道层131更宽的能隙，以在势垒层133和沟道层131的界面处靠近沟道层131一侧形成高浓度、高电子迁移率的二维电子气；例如当沟道层131材料为GaN时，势垒层133可以选择InAlN、AlGaN或AlN。
S33：在势垒层133上沉积形成Ga极性的隔离层135。
具体地，隔离层135用于隔离势垒层133和后续沉积的绝缘层137，其可以是非故意掺杂生长的GaN材料。
S34：在隔离层135上沉积形成Ga极性的绝缘层137。
具体地，绝缘层137具有高电阻特性，可通过在GaN材料生长中碳的自掺杂或者铁的故意掺杂来实现。
需要说明的是，常规直接在衬底上生长的N极性GaN材料，由于背景电子浓度高，采用碳的自掺杂或铁的故意掺杂通常难以实现具有较高电阻的绝缘层。
S35：在绝缘层137上沉积形成p型掺杂层139。
具体地，p型掺杂层139可以采用常规的p-GaN材料，可以提高器件的纵向耐高压能力。
需要说明的是，此处p型掺杂层139为外延功能层130的最外层结构，在其他较佳的实施例中，也可以省去步骤S45，从而省去p型掺杂层139，使得绝缘层137作为外延功能层130的最外层结构。
在本实施例中，在倒置器件后，p型掺杂层139为外延功能层130的最外层结构，此时p型掺杂层139暴露在外，能够方便掺杂后的退火激活。例如，当p型掺杂层139为Mg掺杂的Ga(Al)N时，必须要暴露在高温下进行退火才能实现p型导电。如果按常规的直接在衬底上先生长N极性的p型掺杂层139再生长N极性晶体管的外延功能层130，则p型掺杂层139埋在外延功能层130下，使得退火难以激活掺杂源实现p型导电。
还需要说明的是，本实施例中步骤S41至步骤S45均采用MOVPE或MBE的方法直接生长出Ga极性的外延层结构，其中Ga极性方向由结构衬底180朝向p型掺杂层139。
S4：在外延功能层130远离结构衬底180的一侧键合形成支撑衬底110。
结合参见图4，具体而言，在外延功能层130上沉积形成键合层111，将支撑衬底110键合在键合层111上。即在p型掺杂层139远离结构衬底180的一侧表面沉积形成键合层111[10]，通过直接键合或者胶接键合等方法将外延功能层130与支撑衬底110键合。支撑衬底110的材料可以为Si、SOI、碳化硅、金刚石等。同时，键合层111的材料的选择与键合工艺相关。例如当选择与SOI衬底直接键合时，键合层111可以采用氧化硅或者氮化硅材料。
需要说明的是，此处通过键合的方法，可以与导热性较高的材料(SiC、金刚石等)结合，从而提高了器件的散热能力和热学可靠性。此外，SOI衬底上还可以提前制备Si基CMOS器件等其他器件，本实施例中通过键合的方法，可实现Si的SOI衬底相结合，在SOI衬底上还可以集成Si基CMOS器件等其他器件，从而实现了不同器件的集成。
S5：去除结构衬底180，并暴露出缓冲层170。
结合参见图5，具体而言，在完成支撑衬底110的制作后，将器件倒置，并剥离结构衬底180。此时N极性方向由支撑衬底110朝向刻蚀阻挡势垒层150。通过剥离结构衬底180，暴露出缓冲层170的N极性面，结构衬底180的剥离方法与所选用的材料相关，例如结构衬底180采用Si(111)，可直接通过化学腐蚀的方法去除。当然，此处也可以采用其他常规的衬底剥离方法，例如激光剥离。
S6：去除缓冲层170，并暴露出刻蚀阻挡势垒层150。
结合参见图6，具体而言，首先刻蚀去除缓冲层170，从而暴露出刻蚀阻挡，得到N极性GaN基HEMT器件结构，此处刻蚀阻挡势垒层150可以实现自终止刻蚀工艺。
需要说明的是，此处刻蚀阻挡势垒层150可以去除或者部分去除，也可以不去除。在图8中示出了刻蚀阻挡势垒层150部分去除的情况。当刻蚀阻挡势垒层150的一部分被去除时，仅留下栅极区域的部分。
S7：在外延功能层130远离支撑衬底110的一侧制作源极160a、漏极160b和栅极160c。
结合参见图7，具体地，当刻蚀阻挡势垒层150去除后，在沟道层131远离支撑衬底110的一侧表面按照常规工艺制作源极160a、漏极160b和栅极160c，其中栅极160c位于源极160a和漏极160b之间。当刻蚀阻挡势垒层150未去除时，则在刻蚀阻挡势垒层150的表面制作源极160a、漏极160b和栅极160c。当刻蚀阻挡势垒层150部分去除时，则在刻蚀阻挡势垒层150表面制作栅极160c，在沟道层131的表面制作源极160a和漏极160b。
需要说明的是，制作完成金属电极后，即得到N极性的N极性GaN基HEMT结构，其可以根据金属电极的制作差别而形成增强型N极性GaN基HEMT结构或耗尽型N极性GaN基HEMT结构。当形成耗尽型N极性GaN基HEMT结构时，优选需去除刻蚀阻挡势垒层150；当形成增强型N极性GaN基HEMT结构时，优先需要部分去除刻蚀阻挡势垒层150，仅保留栅极区域的部分，并相应地调整沟道层131和势垒层133的厚度和Al组分，以耗尽栅极160c下方的沟道层131和势垒层133界面处的二维电子气。
还需要说明的是，当此处未去除刻蚀阻挡势垒层150时，该层还可以作为制作源极160a、漏极160b和栅极160c时减小器件漏电的势垒层。
请继续参见图7，本实施例还提供了一种半导体结构100，采用如前述的N极性GaN晶体管结构的制备方法制作而成，该半导体结构100可以包括刻蚀阻挡势垒层150、位于刻蚀阻挡势垒层150一侧的外延功能层130、位于外延功能层130的Ga极性面一侧的支撑衬底110、位于外延功能层130的N极性面一侧的源极160a、漏极160b和栅极160c，其中外延功能层130的靠近刻蚀阻挡势垒层150的一侧为N极性面，外延功能层130远离刻蚀阻挡势垒层150的一侧为Ga极性面。
具体地，本实施例中的半导体结构100为N极性GaN基HEMT结构，其中N极性方 向由支撑衬底110朝向外延功能层130。
在本实施例中，外延功能层130包括沟道层131、势垒层133、隔离层135、绝缘层137和p型掺杂层139，其中p型掺杂层139键合在支撑衬底110上，p型掺杂层139与支撑衬底110之间还形成有键合层111，以实现键合。绝缘层137位于p型掺杂层139远离支撑衬底110的一侧，隔离层135位于绝缘层137远离支撑衬底110的一侧，势垒层133位于隔离层135远离支撑衬底110的一侧，沟道层131位于势垒层133远离支撑衬底110的一侧。此处外延功能层130的具体沉积方法可参考前述说明。
在本实施例其他实施例中，也可以将刻蚀阻挡势垒层150去除，即该半导体结构100包括外延功能层130、位于外延功能层130的Ga极性面一侧的支撑衬底110、位于外延功能层130的N极性面一侧的源极160a、漏极160b和栅极160c。即能够直接在沟道层131的表面制备形成源极160a、漏极160b和栅极160c。
参见图9，在本实施例中，外延功能层130键合在支撑衬底110上，同时支撑衬底110上还集成有Si基CMOS器件或栅极160c驱动电路，从而能够实现不同器件之间的集成。
综上所述，本实施例提供了一种N极性GaN晶体管结构的制备方法和半导体结构100，通过沉积形成Ga极性的外延功能层130，并在外延功能层130上键合形成支撑衬底110，然后将该外延结构倒置后去除结构衬底180和缓冲层170，在暴露出的外延功能层130远离支撑衬底110的一侧制作源极160a、漏极160b和栅极160c，以形成半导体器件。其中，由于采用了Ga极性生长形成外延功能层130，而直接生长的Ga极性GaN材料综合质量通常优于直接生长的N极性GaN材料，故通过直接生长Ga极性的外延功能层130，能够得到表面光滑、低杂质浓度、高晶体质量的GaN材料，而由于半导体结构100的N极性与Ga极性方向相反，通过倒置后去除结构衬底180和缓冲层170的方式，得到N极性面的外延功能层130，从而得到N极性的外延结构，并制作形成N极性的半导体器件。本实施例采用先生长Ga极性外延结构再通过键合和衬底及缓冲层170去除的方法，使得N极性半导体器件具有更好的材料质量和器件性能。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请提供了一种N极性GaN晶体管结构的制备方法和半导体结构，涉及半导体技术领域，通过沉积形成Ga极性的外延功能层，并在外延功能层上键合形成支撑衬底，然后将该外延结构倒置后去除结构衬底和缓冲层，在暴露出的外延功能层远离支撑衬底的一侧制 作源极、漏极和栅极，以形成N极性的GaN晶体管结构。其中，N极性GaN晶体管的外延结构由直接生长的Ga极性外延层上下倒置获得，其材料质量相比直接外延生长的N极性材料更高，能够得到高电阻的GaN绝缘层和陡峭界面的异质结，因而可增强N极性GaN晶体管的耐高压能力、减小器件导通损耗，提升器件整体性能。
本申请的N极性GaN晶体管结构的制备方法可利用现有半导体制程技术重现，本申请提供的N极性GaN半导体结构可应用在多种工业领域，包括5G通讯中所需的射频功率放大器件、电源控制和管理中所需的高功率高频开关器件、气体传感器件等。

Claims (12)

  1. 一种N极性GaN晶体管结构的制备方法，其特征在于，包括：
    在结构衬底的一侧沉积形成缓冲层；
    在所述缓冲层远离所述结构衬底的一侧沉积形成刻蚀阻挡势垒层；
    在所述刻蚀阻挡势垒层远离所述结构衬底的一侧沉积形成上下倒置的N极性晶体管的外延功能层，以使所述外延功能层远离所述结构衬底的一侧为Ga极性面；
    在所述外延功能层远离所述结构衬底的一侧键合形成支撑衬底；
    去除所述结构衬底，并暴露出所述缓冲层；
    去除所述缓冲层，并暴露出所述刻蚀阻挡势垒层；
    在所述外延功能层远离所述支撑衬底的一侧制作源极、漏极和栅极，以形成N极性GaN晶体管。
  2. 根据权利要求1所述的N极性GaN晶体管结构的制备方法，其特征在于，去除所述缓冲层，并暴露出所述刻蚀阻挡势垒层的步骤之后，所述制备方法还包括：
    去除所述刻蚀阻挡势垒层，并暴露出所述外延功能层。
  3. 根据权利要求1或2所述的N极性GaN晶体管结构的制备方法，其特征在于，在所述刻蚀阻挡势垒层远离所述结构衬底的一侧沉积形成上下倒置的N极性晶体管的外延功能层的步骤，包括：
    在所述刻蚀阻挡势垒层上沉积形成Ga极性的沟道层；
    在所述沟道层上沉积形成Ga极性的势垒层；
    在所述势垒层上沉积形成Ga极性的隔离层；
    在所述隔离层上沉积形成Ga极性的绝缘层。
  4. 根据权利要求3所述的N极性GaN晶体管结构的制备方法，其特征在于，所述沟道层的制备材料包括GaN、AlN、InAlN、AlGaN、InAlGaN中的至少一种材料；以及所述势垒层的制备材料包括AlN、InAlN、AlGaN、InAlGaN、AlScN中的至少一种材料；所述势垒层的禁带宽度大于所述沟道层的禁带宽度，在所述势垒层与所述沟道层靠近所述沟道层一侧的界面上形成高浓度、高电子迁移率的二维电子气。
  5. 根据权利要求3或4所述的N极性GaN晶体管结构的制备方法，其特征在于，在所述隔离层上沉积形成绝缘层的步骤之后，所述制备方法还包括：
    在所述绝缘层上沉积形成p型掺杂层，所述p型掺杂层采用p-GaN材料。
  6. 根据权利要求1至5中任一项所述的N极性GaN晶体管结构的制备方法，其特征在于，在所述外延功能层远离所述结构衬底的一侧沉积键合介质，通过直接键合或者胶接键 合方法将所述外延功能层与所述支撑衬底键合。
  7. 根据权利要求1至8中任一项所述的N极性GaN晶体管结构的制备方法，其特征在于，所述刻蚀阻挡势垒层为Al xGa 1-xN，其中x为Al的组分，且0＜x组分；所述刻蚀阻挡层中Al组分高于所述沟道层中的Al组分。
  8. 根据权利要求7所述的N极性GaN晶体管结构的制备方法，其特征在于，所述刻蚀阻挡势垒层的厚度为至少为1nm。
  9. 一种半导体结构，采用根据权利要求1至8中任一项所述的N极性GaN晶体管结构的制备方法制作而成，其特征在于，包括：
    刻蚀阻挡势垒层；
    位于所述刻蚀阻挡势垒层一侧的外延功能层，其中所述外延功能层的靠近所述刻蚀阻挡势垒层的一侧为N极性面，所述外延功能层远离所述刻蚀阻挡势垒层的一侧为Ga极性面；
    位于所述外延功能层的Ga极性面一侧的支撑衬底；
    位于所述外延功能层的N极性面一侧的源极、漏极和栅极；
    其中，所述外延功能层包括在所述刻蚀阻挡势垒层上沉积形成的沟道层、在所述沟道层上沉积形成的势垒层、在所述势垒层上沉积形成的隔离层以及在所述隔离层上沉积形成的绝缘层。
  10. 根据权利要求9所述的半导体结构，其特征在于，所述外延功能层还包括位于所述绝缘层上的p型掺杂层。
  11. 根据权利要求9所述的半导体结构，其特征在于，所述刻蚀阻挡层在栅极两侧区域部分或全部去除。
  12. 根据权利要求9或11所述的半导体结构，其特征在于，所述栅极制作在所述刻蚀阻挡层上，所述源极和所述漏极制作在所述栅极两侧的沟道层上。
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