WO2022041674A1 - 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法 - Google Patents

低热阻硅基氮化镓微波毫米波器件材料结构及制备方法 Download PDF

Info

Publication number
WO2022041674A1
WO2022041674A1 PCT/CN2021/079283 CN2021079283W WO2022041674A1 WO 2022041674 A1 WO2022041674 A1 WO 2022041674A1 CN 2021079283 W CN2021079283 W CN 2021079283W WO 2022041674 A1 WO2022041674 A1 WO 2022041674A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
silicon
thermal conductivity
high thermal
gallium nitride
Prior art date
Application number
PCT/CN2021/079283
Other languages
English (en)
French (fr)
Inventor
张进成
郝璐
刘志宏
刘俊伟
宋昆璐
张雅超
张苇杭
郝跃
Original Assignee
西安电子科技大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 西安电子科技大学 filed Critical 西安电子科技大学
Priority to US17/282,190 priority Critical patent/US20220310796A1/en
Publication of WO2022041674A1 publication Critical patent/WO2022041674A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the invention belongs to the technical field of semiconductor devices, and in particular relates to a low thermal resistance silicon-based gallium nitride microwave millimeter-wave device material structure and a preparation method.
  • gallium nitride have larger band gap, higher critical breakdown electric field, higher electron saturation drift speed, stable chemical performance, as well as physical properties such as high temperature resistance and radiation resistance
  • the use of gallium nitride materials to make electronic devices can further reduce chip area, increase operating frequency, increase operating temperature, reduce on-resistance and improve breakdown voltage, etc.
  • GaN materials are used in There is great potential in the preparation of microwave and millimeter-wave devices.
  • the heterostructure can form a two-dimensional electron gas, and can obtain electron mobility above 1500 cm 2 /V ⁇ s, saturation electron velocity up to 1.5 ⁇ 10 cm 7 /s, and high electron mobility above 1 ⁇ 10 13 cm -2 at room temperature. Two-dimensional electron gas concentration, so that high-speed Schottky Barrier Diode (SBD) and High Electron Mobility Transistor (HEMT) devices based on gallium nitride materials can have lower conductivity. on-resistance and higher output current.
  • SBD Schottky Barrier Diode
  • HEMT High Electron Mobility Transistor
  • the higher critical breakdown electric field strength of the gallium nitride material can make the electronic device have a higher breakdown voltage, so that the device can work at a higher working voltage, so that the device has a higher microwave output power density .
  • gallium nitride devices Compared with silicon or gallium arsenide microwave electronic devices of the same output power, gallium nitride devices have higher power added efficiency and thus lower energy loss.
  • GaN-based materials are mainly deposited on foreign substrates. So far, the substrates used for the growth of gallium nitride materials are mainly silicon carbide and silicon.
  • SiC-based GaN devices benefit from the smaller lattice mismatch between SiC and GaN, the higher thermal conductivity of SiC, lower thermal resistance and higher output power density. R & D comparison Earlier, the technology was relatively mature. SiC-based GaN microwave devices have been widely used in military radar, satellite, communication base stations and other fields.
  • silicon carbide-based gallium nitride device due to the relatively high price and small size of the silicon carbide substrate, the cost of the silicon carbide-based gallium nitride device is relatively high.
  • silicon-based GaN devices due to the large size and low cost of silicon substrate wafers, and the large-scale production advantages of silicon production lines, silicon-based GaN devices have relatively low cost and high cost performance. Silicon-based GaN microwave and millimeter-wave devices are expected to be widely used in mobile communication terminals such as 5G communication base stations and mobile phones in the future.
  • GaN-on-SiC devices Compared with GaN-on-SiC devices, an important disadvantage of GaN-on-Si devices is that the thermal resistance is relatively high, resulting in poor heat dissipation performance, thus limiting the output power of GaN-on-Si microwave and millimeter-wave devices. density and efficiency.
  • the thermal conductivity of the silicon substrate is relatively poor.
  • the room temperature thermal conductivity value of a typical silicon carbide substrate is 4.0W/cm ⁇ K, while the silicon substrate is only 1.5W/cm ⁇ K.
  • the epitaxial delay of GaN-based materials is performed on the silicon substrate. Due to the relatively large lattice mismatch between silicon and GaN crystal materials, it is necessary to insert between the active structure of the GaN device and the silicon substrate.
  • nucleation layer and transition layer such as AlGaN material with graded Al composition or AlN/GaN superlattice material
  • the crystal material quality of such nucleation layer and transition layer is relatively poor, and the defects are relatively high Many
  • the thermal conductivity is also very poor.
  • the heat generated by the device itself cannot be dissipated by the buffer layer, the nucleation layer, the transition layer and the substrate in time, resulting in the accumulation of heat in the channel into an obvious self-heating effect. Whether the self-heating effect of GaN-on-Si microwave and millimeter-wave devices is serious depends on two aspects. The first is the thermal conductivity of the GaN channel and buffer layer materials and the following nucleation layers, transition layers and substrate layers.
  • the second is the interface thermal resistance between the layers.
  • the interface thermal resistance mainly describes the thermal conduction process that occurs between the material interfaces, and its value is the reciprocal of the thermal boundary conductivity. Different thermal conductivities of interface materials lead to thermal coupling.
  • the phonon propagation efficiency at the interface determines the interface thermal resistance (TBR). Meanwhile, the lattice mismatch and defects at the interface will increase the TBR.
  • the self-heating effect caused by the larger TBR will be more obvious, which is an important factor limiting the heat dissipation performance of the device, so it must be minimized to obtain the optimal performance.
  • the silicon substrate should be thinned as much as possible, and then the device after the thinned substrate is diced and transferred to a heat sink with high thermal conductivity.
  • most of the products of GaN-on-silicon microwave and millimeter-wave devices are to thin the silicon substrate to 100 ⁇ m, and the technology under development is to thin the silicon substrate to 50 ⁇ m.
  • “A.Pantellini, A.Nanni, C.Lanzieri, "Thermal behavior of AlGaN/GaN HEMT on silicon Microstrip technology," 6th European Microwave Integrated Circuit Conference, Oct. 2011” proposed a method by thinning the silicon lining
  • the method for improving the heat dissipation performance of the device at the bottom has the disadvantage that the process operation after the thinning of the silicon substrate is more difficult, thereby reducing the yield of the device.
  • the present invention provides a material structure and a preparation method of a low thermal resistance silicon-based gallium nitride microwave millimeter wave device.
  • the technical problem to be solved by the present invention is realized by the following technical solutions:
  • the embodiment of the present invention provides a low thermal resistance silicon-based gallium nitride microwave millimeter-wave device material structure, including:
  • a high thermal conductivity medium layer located on the upper surface of the silicon substrate layer, and forming a first patterned interface with unevenness with the silicon substrate layer;
  • a buffer layer located on the upper surface of the high thermal conductivity medium layer, and forming a second patterned interface with unevenness with the high thermal conductivity medium layer;
  • a channel layer located on the upper surface of the buffer layer
  • the composite barrier layer is located on the upper surface of the channel layer.
  • the material of the high thermal conductivity medium layer includes aluminum nitride, boron nitride, silicon carbide or diamond, and the thickness is 20-20000 nm.
  • both the first patterned interface and the second patterned interface include an interface formed with a plurality of grooves, and the area ratio of the plurality of grooves is 1% to 99%.
  • a plurality of the grooves are regularly arranged, and the shapes of the plurality of the grooves include one or more of rectangles, triangles, and trapezoids.
  • the shape of each of the grooves is a rectangle
  • the depth of the rectangle is 10 nm ⁇ 2000 nm
  • the width of the rectangle is 10 nm to 2000 nm. 10 nm to 10 ⁇ m.
  • the material of the buffer layer includes gallium nitride, aluminum gallium nitride or aluminum nitride, and the thickness is 100-5000 nm; the material of the channel layer is gallium nitride, and the thickness is 10-5000 nm. 1000nm.
  • the composite barrier layer includes an isolation layer, a core barrier layer and a cap layer, wherein,
  • the isolation layer is located on the upper surface of the channel layer
  • the core barrier layer is located on the upper surface of the isolation layer
  • the cap layer is located on the upper surface of the core barrier layer.
  • the composite barrier layer includes an isolation layer and a core barrier layer, wherein,
  • the isolation layer is located on the upper surface of the channel layer
  • the core barrier layer is located on the upper surface of the isolation layer.
  • the composite barrier layer includes a core barrier layer and a cap layer, wherein,
  • the core barrier layer is located on the upper surface of the channel layer
  • the cap layer is located on the upper surface of the core barrier layer.
  • Another embodiment of the present invention provides a preparation method of a low thermal resistance gallium nitride on silicon microwave millimeter wave device material structure, comprising the steps of:
  • the material of the initial substrate is a silicon substrate substrate with a target crystal orientation
  • the first part of the high thermal conductivity medium layer is bonded to the second part of the high thermal conductivity medium layer by using wafer bonding technology to form the high thermal conductivity medium layer, and the high thermal conductivity medium layer is bonded to the second part of the high thermal conductivity medium layer.
  • a first patterned interface with unevenness is formed between the silicon substrate layers, and a second patterned interface with unevenness is formed between the silicon substrate layer and the buffer layer;
  • the transition substrate is removed.
  • an uneven patterned interface is formed between the high thermal conductivity dielectric layer, the silicon substrate layer and the buffer layer, which increases the contact area of the interface , reducing the interface thermal resistance (TBR), thereby reducing the thermal resistance of the device and improving the heat dissipation performance of the device.
  • TBR interface thermal resistance
  • the low thermal resistance silicon-based gallium nitride microwave and millimeter wave device material structure of the present invention forms a patterned interface at the interface between the high thermal conductivity dielectric layer, the buffer layer and the silicon substrate, which reduces the inter-lattice interface compared with the planar interface.
  • the compressive stress improves the material quality of the high thermal conductivity dielectric layer, thereby improving the quality of the device.
  • a high thermal conductivity dielectric layer is used to realize the bonding between the silicon substrate layer and the buffer layer, maintaining high bonding strength, high mechanical strength and high stability It is compatible with existing production lines and has the advantages of high yield and high reliability.
  • FIG. 1 is a schematic structural diagram of a material structure of a low thermal resistance GaN-on-silicon microwave millimeter-wave device provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a material structure of another low thermal resistance GaN-on-silicon microwave millimeter-wave device provided by an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of another low thermal resistance GaN-on-silicon microwave millimeter-wave device material structure provided by an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a material structure of another low thermal resistance GaN-on-silicon microwave millimeter-wave device provided by an embodiment of the present invention.
  • FIG. 5 is a schematic flowchart of a method for preparing a low thermal resistance gallium nitride on silicon microwave millimeter wave device material structure provided by an embodiment of the present invention
  • 6a-6t are schematic process diagrams of a method for preparing a material structure of a low thermal resistance gallium nitride on silicon microwave millimeter-wave device material structure provided by an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a material structure of a low thermal resistance gallium nitride on silicon microwave millimeter wave device provided by an embodiment of the present invention.
  • the material structure of the low thermal resistance silicon-based gallium nitride microwave and millimeter wave device includes:
  • the interface shapes of the first patterned interface and the second patterned interface may be the same or different, as long as they satisfy the uneven state.
  • both the first patterned interface and the second patterned interface include interfaces formed with a plurality of grooves G; the plurality of grooves G may be arranged regularly or irregularly; the shape of each groove G It can be regular, such as rectangle, triangle, trapezoid, etc., or irregular shape; in plan view, the ratio of the area of several grooves G to the area of the patterned interface is 1% to 99%.
  • the upper surface of the silicon substrate layer 1 is provided with regularly arranged or irregularly arranged grooves G to form a patterned interface with the high thermal conductivity medium layer 2; the lower surface of the buffer layer 3 is provided with regularly arranged or irregularly arranged grooves G.
  • the grooves G are regularly arranged to form a patterned interface with the high thermal conductivity medium layer 2 .
  • each groove G is a rectangle. From a plan view, stripe-shaped grooves are formed on the surface of the device. More specifically, when the groove G is rectangular, the depth of the groove G may be 10 nm ⁇ 2000 nm, and the width of the groove G may be 10 nm ⁇ 10 ⁇ m.
  • the silicon substrate layer 1 is high-resistance silicon, the doping type is n-type or p-type, the resistivity is 3000-30000 ⁇ cm, and the crystal orientation of the silicon substrate layer 1 is [111].
  • the resistivity of the silicon substrate layer 1 is 5000 ⁇ cm.
  • the material of the high thermal conductivity medium layer 2 may include aluminum nitride, boron nitride, silicon carbide or diamond, and its thickness is 20-20000 nm.
  • the material of the high thermal conductivity medium layer 2 is aluminum nitride, and the thickness is 1000 nm.
  • the material of the buffer layer 3 includes gallium nitride, aluminum gallium nitride or aluminum nitride, and its thickness is 100-5000 nm.
  • the material of the buffer layer 3 is gallium nitride, and the thickness is 1000 nm.
  • the material of the channel layer 4 is gallium nitride, and the thickness is 10-1000 nm. Preferably, the thickness of the channel layer 4 is 300 nm.
  • the material structure of conventional GaN-on-silicon microwave and millimeter-wave devices due to the large lattice constant mismatch between the silicon substrate layer and the buffer layer, it is necessary to introduce an aluminum nitride nucleation layer and a transition layer.
  • the layers may be aluminum gallium nitride or aluminum nitride/gallium nitride superlattices.
  • the crystal quality of the nucleation layer and the transition layer is very poor, the dislocation density is high, and the thermal conductivity is relatively poor, which seriously affects the heat dissipation performance of the silicon-based GaN microwave and millimeter wave power devices.
  • the high thermal conductivity dielectric layer 2 is used to realize the bonding between the silicon substrate layer 1 and the buffer layer 3, which not only maintains the high bonding strength, high mechanical strength and high stability of the device, but also reduces the thermal resistance of the device , thereby improving the heat dissipation performance of the silicon-based gallium nitride microwave and millimeter wave device, reducing the operating channel temperature of the device, and improving the performance of the device.
  • striped grooves are respectively prepared between the high thermal conductivity medium layer, the buffer layer, and the silicon substrate layer to form a patterned interface.
  • the striped groove not only reduces the compressive stress between the lattices, but also increases the interface contact area of the high thermal conductivity dielectric layer/buffer layer and the high thermal conductivity dielectric layer/silicon substrate layer, which reduces the thermal interface resistance (TBR), thereby The thermal resistance of the device is reduced, the operating channel temperature of the device is lowered, and the heat dissipation performance of the silicon-based gallium nitride microwave and millimeter wave power device is improved.
  • TBR thermal interface resistance
  • FIG. 2 is a schematic structural diagram of another low thermal resistance GaN-on-Si microwave millimeter-wave device material structure provided by an embodiment of the present invention.
  • the device material structure includes: silicon substrate layer 1, high thermal conductivity medium layer 2, buffer layer 3, channel layer 4 and composite barrier layer 5, wherein silicon substrate layer 1, high thermal conductivity medium layer 2, buffer layer 3 .
  • the structure of the channel layer 4 is shown in FIG. 1 , which will not be repeated here.
  • the composite barrier layer 5 includes an isolation layer 51 and a core barrier layer 52 , wherein the isolation layer 51 is located on the upper surface of the channel layer 4 ; the core barrier layer 52 is located on the upper surface of the isolation layer 51 .
  • the material of the isolation layer 51 is aluminum nitride, and the thickness is 0.5-1.5 nm. Preferably, the thickness of the isolation layer 51 is 1 nm.
  • the material of the core barrier layer 52 is AlGaN, wherein the composition content of aluminum is 0.2-0.4, and the thickness is 10-30 nm; or it is InAlN, wherein the composition content of indium is 0.1-0.2, and the thickness is 5 nm ⁇ 30nm; or AlN with a thickness of 2 ⁇ 10nm.
  • the material of the core barrier layer 52 is AlGaN, wherein the composition content of aluminum is 0.25, and the thickness is 20 nm.
  • FIG. 3 is a schematic structural diagram of a material structure of another low thermal resistance gallium nitride on silicon microwave millimeter wave device provided by an embodiment of the present invention.
  • the device material structure includes: silicon substrate layer 1, high thermal conductivity medium layer 2, buffer layer 3, channel layer 4 and composite barrier layer 5, wherein silicon substrate layer 1, high thermal conductivity medium layer 2, buffer layer 3 .
  • the structure of the channel layer 4 is shown in FIG. 1 , which will not be repeated here.
  • the composite barrier layer 5 includes a core barrier layer 52 and a cap layer 53 , wherein the core barrier layer 52 is located on the upper surface of the channel layer 4 ; the cap layer 53 is located on the upper surface of the core barrier layer 52 .
  • the material and thickness of the core barrier layer 52 please refer to the material and thickness of the core barrier layer 52 in FIG. 2, which will not be repeated here.
  • the material of the cap layer 53 is gallium nitride with a thickness of 1-3 nm; or silicon nitride with a thickness of 1-10 nm.
  • the material of the cap layer 53 is gallium nitride, and the thickness is 3 nm.
  • FIG. 4 is a schematic structural diagram of a material structure of another low thermal resistance gallium nitride on silicon microwave millimeter wave device provided by an embodiment of the present invention.
  • the device material structure includes: silicon substrate layer 1, high thermal conductivity medium layer 2, buffer layer 3, channel layer 4 and composite barrier layer 5, wherein silicon substrate layer 1, high thermal conductivity medium layer 2, buffer layer 3 .
  • the structure of the channel layer 4 is shown in FIG. 1 , which will not be repeated here.
  • the composite barrier layer 5 includes an isolation layer 51, a core barrier layer 52 and a cap layer 53, wherein the isolation layer 51 is located on the upper surface of the channel layer 4; the core barrier layer 52 is located on the upper surface of the isolation layer 51; the cap layer 53 on the upper surface of the core barrier layer 52 .
  • the materials and thicknesses of the isolation layer 51 , the core barrier layer 52 and the cap layer 53 please refer to the materials and thicknesses in FIG. 2 and FIG. 3 , which will not be repeated here.
  • the material structure of the GaN-on-silicon microwave and millimeter-wave device forms a patterned interface with the buffer layer and the interface of the silicon substrate through the high thermal conductivity dielectric layer, which reduces the thermal resistance of the device and improves the thermal conductivity of the device , the channel layer is fabricated on the upper surface of the buffer layer to provide a conductive channel for the device, the composite barrier layer is fabricated on the upper surface of the channel layer, and two-dimensional electrons are formed at the interface between the composite barrier layer and the channel layer.
  • the gas acts as the conductive channel of the device, and further improves the electrical characteristics of the device through the isolation layer or cap layer.
  • the low thermal resistance silicon-based gallium nitride microwave and millimeter wave device material structure provided in this embodiment can effectively reduce the thermal resistance of the device, improve the heat dissipation performance of the device, and improve the maximum output power and efficiency of the device. and other performance indicators, and has good electrical characteristics; at the same time, it also has the advantages of compatibility with existing production lines, high yield and high reliability, and can be used in radio frequency, microwave, millimeter wave chips and systems and other fields.
  • this embodiment provides a preparation method of a low thermal resistance silicon-based gallium nitride microwave millimeter wave device material structure.
  • FIG. 5 is a schematic flowchart of a method for fabricating a low thermal resistance GaN-on-silicon microwave millimeter-wave device material structure provided by an embodiment of the present invention
  • FIGS. 6a-6t are an embodiment of the present invention.
  • Provided is a process schematic diagram of a preparation method of a low thermal resistance silicon-based gallium nitride microwave millimeter wave device material structure. The preparation method includes the steps:
  • the material of the initial substrate 11 is a silicon substrate substrate with a target crystal orientation, as shown in FIG. 6a.
  • a silicon substrate substrate with a target crystal orientation is selected as the initial substrate 11, and the silicon substrate substrate is a high-resistance silicon substrate.
  • the silicon substrate has a resistivity of 5000 ⁇ cm, a crystal orientation of [111], a size of 8 inches, and a thickness of 725 ⁇ m.
  • the nucleation layer 12 and the transition layer 13 are sequentially prepared on the initial substrate 11 .
  • the nucleation layer 12 and the transition layer 13 need to be prepared on the initial substrate to facilitate the subsequent preparation of the buffer layer 3 .
  • the nucleation layer 12 is epitaxially grown on the initial substrate 11 by using Metal-Organic Chemical Vapor Deposition (Metal-Organic Chemical Vapor Deposition, MOCVD for short) equipment and technology, wherein the material of the nucleation layer 12 can be nitrogen Aluminum alloy material, its thickness can be 200nm, as shown in Figure 6b.
  • Metal-Organic Chemical Vapor Deposition Metal-Organic Chemical Vapor Deposition, MOCVD for short
  • transition layer 13 on the nucleation layer 12, wherein the material of the transition layer 13 can be aluminum nitride/gallium nitride superlattice material, and the thickness can be 1000nm, as shown in FIG. 6c Show.
  • the buffer layer 3 is epitaxially grown on the transition layer 13 prepared in step S2 by using MOCVD equipment and technology, wherein the buffer layer 3 can be an Fe-doped buffer layer 3 with a dislocation density of 1e9cm ⁇ 2 and a resistivity of 1e9cm ⁇ 2 . 1 M ⁇ cm, as shown in Fig. 6d.
  • a channel layer 4 is prepared on the buffer layer 3 .
  • a channel layer 4 is epitaxially grown on the buffer layer 3, wherein the channel layer 4 can be an unintentionally doped GaN channel layer 4, and its thickness can be 300 nm, as shown in Figure 6e shown.
  • a composite barrier layer 5 is prepared on the channel layer 4 .
  • the composite barrier layer 5 can have several structures. One is to include an isolation layer 51 and a core barrier layer 52; the other is to include a core barrier layer 52 and a cap layer 53; layer 52 and cap layer 53 .
  • the preparation method of the composite barrier layer 5 including the isolation layer 51 , the core barrier layer 52 and the cap layer 53 is taken as an example to describe the preparation method, and the preparation methods of the other two structures are similar.
  • an isolation layer 51 is epitaxially grown on the channel layer 4 by using MOCVD equipment and technology; wherein, the isolation layer 51 may be made of aluminum nitride and the thickness may be 1 nm, as shown in FIG. 6f .
  • a core barrier layer 52 is epitaxially grown on the isolation layer 51; wherein, the core barrier layer 52 may be AlGaN with an aluminum composition of 0.25, and its thickness may be 20 nm, as shown in FIG. 6g.
  • the cap layer 53 is epitaxially grown on the core barrier layer 52 to form the composite barrier layer 5, wherein the material of the cap layer 53 can be gallium nitride, and the thickness can be 3nm;
  • the first wafer 10 is shown in FIG. 6h.
  • the nucleation layer, the transition layer, the buffer layer, the channel layer and the composite barrier layer are sequentially prepared on the silicon substrate.
  • the The conventional GaN-on-Si epitaxial wafers of bottom, nucleation layer, transition layer, buffer layer, channel layer and composite barrier layer are directly subjected to the subsequent preparation process.
  • the sample is turned over, and a transition substrate is prepared on the lower surface of the overturned composite barrier layer 5 by using the wafer bonding technology.
  • step S41 using plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD for short) equipment and technology to deposit 250nm thick on the upper surface of the first wafer 10 obtained in step S3, that is, the surface of the composite barrier layer 5
  • PECVD plasma enhanced chemical vapor deposition
  • the first silicon dioxide layer 21 is fabricated to form a second wafer 20, as shown in FIG. 6i.
  • a silicon wafer is prepared as a transition substrate.
  • a silicon wafer 31 with a target crystal orientation is selected; wherein, the resistivity of the silicon wafer 31 can be 10 ⁇ cm, the crystal orientation is [100], the size is 8 inches, and the thickness is 725 ⁇ m.
  • a second silicon dioxide layer 32 with a thickness of 250 nm is deposited on the upper surface of the silicon wafer 31 to form a third wafer 30, as shown in FIG. 6j.
  • step S43 invert the sample obtained in step S42, and bond the surfaces of the first silicon dioxide layer 21 fabricated in step S31 and the second silicon dioxide layer 32 fabricated in step S42 together by wafer bonding technology to A transition substrate is formed under the composite barrier layer to form a fourth wafer 40, as shown in FIG. 6k.
  • the initial substrate 11 , the nucleation layer 12 and the transition layer 13 are sequentially removed by using a wet chemical etching technique or a plasma etching technique, so that the buffer layer 3 is exposed on the surface of the sample.
  • the initial substrate 11 in the fourth wafer 40 produced in step S43 is removed to form a fifth wafer 50, as shown in FIG. 61 .
  • the nucleation layer 12 in the fifth wafer 50 produced above is removed to form a sixth wafer 60, as shown in FIG. 6m.
  • the transition layer 13 in the sixth wafer 60 obtained above is removed to form a seventh wafer 70, as shown in FIG. 6n.
  • the surface of the buffer layer 3 on the upper surface of the seventh wafer 70 obtained in step S5 is patterned and prepared by using a photolithography process and an etching process, so as to form a second patterned surface with unevenness, and the eighth wafer is fabricated and formed. Circle 80, as shown in Figure 6o.
  • the uneven second patterned surface can be a patterned surface with an array of grooves G
  • the grooves G can be arranged regularly or irregularly, and its shape can be any regular shape such as rectangle, triangle, trapezoid, etc. It can be irregular shape; when it is a rectangle, the depth of the groove G array can be 10nm-2000nm, the width of the groove G can be 10nm-10 ⁇ m, and the area ratio of the groove G is 1%-99%, preferably, the groove G The depth of G is 500 nm, the width of groove G is 1 ⁇ m, and the area ratio of groove G is 50%.
  • a high thermal conductivity material is deposited on the second patterned surface of the buffer layer 3 in the eighth wafer 80 obtained in step S6 to form the second patterned surface of the high thermal conductivity dielectric layer 2 A part 91; wherein, the thickness of the high thermal conductivity medium layer 2 may be 20-20000 nm, and a ninth wafer 90 is fabricated to form, as shown in FIG. 6p.
  • the material of the high thermal conductivity medium layer 2 is aluminum nitride, and the thickness is 1 ⁇ m.
  • the size of the silicon substrate layer 1 is 8 inches, the thickness is 725 ⁇ m, the resistivity is 5000 ⁇ cm, and the crystal orientation is [111].
  • a photolithography process and an etching process are used to pattern the upper surface of the silicon substrate layer 1 to form a first patterned surface with an array of grooves, and a tenth wafer 100 is fabricated, as shown in FIG. 6q . Show.
  • the uneven first patterned surface may be a patterned surface with an array of grooves G
  • the grooves G may be arranged regularly or irregularly, and the shape may be any regular shape such as a rectangle, a triangle, a trapezoid, etc., or It can be irregular shape; when it is a rectangle, the depth of the groove G array can be 10nm-2000nm, the width of the groove G can be 10nm-10 ⁇ m, and the area ratio of the groove G is 1%-99%, preferably, the groove G The depth of G is 500 nm, the width of groove G is 1 ⁇ m, and the area ratio of groove G is 50%.
  • a high thermal conductivity material is deposited on the first patterned surface of the silicon substrate layer in the tenth wafer 100 obtained in step S8 to form the first patterned surface of the high thermal conductivity medium layer 2
  • an eleventh wafer 110 is formed, as shown in FIG. 6r.
  • the thickness of the high thermal conductivity medium layer 2 may be 20 to 20000 nm.
  • the material of the high thermal conductivity medium layer 2 is aluminum nitride, and the thickness is 1 ⁇ m.
  • the first patterned surface of the silicon substrate layer 1 corresponds to the first patterned interface between the high thermal conductivity medium layer 2 and the silicon substrate layer 1
  • the second patterned surface of the buffer layer 3 corresponds to the high thermal conductivity.
  • the second patterned interface between the rate dielectric layer 2 and the buffer layer 3 is formed.
  • the first part 91 of the high thermal conductivity medium layer 2 in the ninth wafer 90 produced in step S7 and the high thermal conductivity medium layer 2 in the eleventh wafer 110 produced in step S9 are combined.
  • the second parts 101 of the two are bonded together to form a high thermal conductivity dielectric layer with a double-sided patterned interface between the buffer layer 3 and the silicon substrate layer 1 to form a twelfth wafer 120 , as shown in FIG. 6s .
  • wet chemical etching technology or plasma etching technology is used to sequentially remove the silicon wafer 31, the second silicon dioxide layer 21 and the first silicon dioxide layer 32 produced in step S4, and finally silicon-based nitridation is obtained.
  • the silicon wafer 31 in the eleventh wafer 110 produced is removed to form a thirteenth wafer 130, as shown in FIG. 6t.
  • the high thermal conductivity medium layer 2 includes a first part 91 and a second part 101 .
  • the lower surface of the buffer layer and the upper surface of the silicon substrate are patterned and prepared by a photolithography process and an etching process to form striped grooves, and then magnetron sputtering and wafer bonding are used to prepare
  • the high thermal conductivity dielectric layer material is deposited by the method, and a patterned interface is formed with the interface of the buffer layer and the silicon substrate respectively.
  • the striped groove not only reduces the compressive stress between the lattices, but also increases the The interface contact area of the high thermal conductivity dielectric layer/buffer layer and the high thermal conductivity dielectric layer/silicon substrate layer reduces the thermal interface resistance (TBR), thereby reducing the thermal resistance of the device and reducing the operating channel temperature of the device.
  • TBR thermal interface resistance
  • the heat dissipation performance of the silicon-based gallium nitride microwave and millimeter wave power device is improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

一种低热阻硅基氮化镓微波毫米波器件材料结构及制备方法，该器件材料结构包括：硅衬底层(1)；高热导率介质层(2)，位于所述硅衬底层(1)的上表面，且与所述硅衬底层(1)之间形成凹凸不平的第一图案化界面；缓冲层(3)，位于所述高热导率介质层(2)的上表面，且与所述高热导率介质层(2)之间形成凹凸不平的第二图案化界面；沟道层(4)，位于所述缓冲层(3)的上表面；复合势垒层(5)，位于所述沟道层(4)的上表面。该低热阻硅基氮化镓微波毫米波器件材料结构中，高热导率介质层与硅衬底层以及缓冲层之间均形成凹凸不平的图案化界面，增大了界面的接触面积，降低了界面热阻，从而减小了器件的热阻，提高了器件的散热性能。

Description

低热阻硅基氮化镓微波毫米波器件材料结构及制备方法 技术领域
本发明属于半导体器件技术领域，具体涉及一种低热阻硅基氮化镓微波毫米波器件材料结构及制备方法。
背景技术
随着微电子技术的发展，以氮化镓为代表的第三代宽禁带半导体材料有更大的禁带宽度、更高的临界击穿电场和较高的电子饱和漂移速度、稳定的化学性能、以及耐高温和抗辐射等物理性质，用氮化镓材料制作电子器件可以进一步减少芯片面积、提高工作频率、提高工作温度、降低导通电阻以及提高击穿电压等，氮化镓材料在制备微波毫米波器件方面有巨大的潜力。
氮化镓以及与氮化镓同一材料体系的铝镓氮、铟铝氮等具有很高的极化系数，氮化镓与比氮化镓禁带宽度大的铝镓氮或铟铝氮形成的异质结构能够形成二维电子气，在室温下可以获得高于1500cm 2/V·s的电子迁移率、高达1.5×10cm 7/s的饱和电子速度和高于1×10 13cm -2的二维电子气浓度，由此基于氮化镓材料研制的高速肖特基二极管(Schottky Barrier Diode，简称SBD)和高电子迁移率晶体管(High Electron Mobility Transistor，简称HEMT)器件能够具有更低的导通电阻和更高的输出电流。另外，氮化镓材料的较高的临界击穿电场强度可以使电子器件具有更高的击穿电压，从而使器件能够在更高的工作电压下工作，使器件拥有更高的微波输出功率密度。跟同等输出功率的硅或者砷化镓微波电子器件相比，氮化镓器件具有更高的功率附加效率，从而具有更低的能量损耗。
由于氮化镓自支撑衬底技术的不成熟，目前氮化镓微波毫米波器件中，氮化镓基的材料主要淀积在异质衬底上。目前为止用于氮化镓材料生长的衬底主要有碳化硅和硅。碳化硅基氮化镓的器件得益于碳化硅与氮化镓的较小的晶格失配、碳化硅较高的导热性能，具有较低的热阻和较高的输出功率密度，研发比较早，技术也比较成熟。碳化硅基氮化镓的微波器件已经广泛应用于军事雷达、卫星、通信基站等领域。但是，受限于价格比较高、尺寸比较小的碳化硅衬底，碳化硅基氮化镓器件的成本比较高。而硅基氮化镓器件由于硅衬底晶圆的大尺寸、低成本、和硅生产线的规模生产优势，其成本比较低，性价比比较高。硅基氮化镓微波毫米波器件以后有望大规模应用于5G通信基站和手机等移动通信终端。
但是，与碳化硅基氮化镓器件相比，硅基氮化镓器件的一个重要缺点是热阻比较高，从而散热性能比较差，因此限制了硅基氮化镓微波毫米波器件的输出功率密度和效率。首先，硅衬底的热导率比较差，典型碳化硅衬底的室温热导率值为4.0W/cm·K，而硅衬底只有1.5W/cm·K。其次，在硅衬底上进行氮化镓基的材料外延时，由于硅与氮化镓晶体材料的晶格失配比较大，需要在氮化镓器件有源结构与硅衬底之间插入很厚的成核层和过渡层，例如渐变铝组分的铝镓氮材料或者氮化铝/氮化镓超晶格材料，这种成核层和过渡层的晶体材料质量比较差，缺陷比较多，热导率也很差。器件自身产生的热量不能及时的被缓冲层、成核层、过渡层以及衬底耗散掉，从而导致热量在沟道里累积成明显的自热效应。决定硅基氮化镓微波毫米波器件自热效应严重与否取决于两个方面，第一是GaN沟道与缓冲层材料及以下成核层、过渡层以及衬底各层的热导率，第二便是各 层之间的界面热阻。界面热阻主要描述了发生于材料界面之间的热传导过程，其值为热边界传导率的倒数。界面材料的不同热导率导致了热耦合，声子在界面传播效率决定了界面热阻(TBR)的大小，同时界面的晶格失配与缺陷会使TBR增大。较大的TBR所引起的自热效应将更加明显，是限制器件散热性能的重要因素，因此必须将其降至最小，以得到最优的性能。
目前提高硅基氮化镓微波毫米波器件散热性能的方法主要有几种技术路线：
1、器件裸芯工艺完成后，尽量减薄硅衬底，然后将减薄衬底后的器件划片后转移到一个具有高热导率的热沉上。目前硅基氮化镓微波毫米波器件的产品大部分是将硅衬底减薄到100μm，处于开发状态的技术是将硅衬底减薄到50μm。比如，“A.Pantellini,A.Nanni,C.Lanzieri,“Thermal behavior of AlGaN/GaN HEMT on silicon Microstrip technology,”6th European Microwave Integrated Circuit Conference,Oct.2011”，提出了一种通过减薄硅衬底提高器件散热性能的方法，这种方法的缺点是硅衬底减薄后的工艺操作难度加大，从而导致器件的成品率降低。
2、在硅基氮化镓微波毫米波器件的表面上淀积一层高热导率介质材料，比如，“N.Tsurumi,H.Ueno,T.Murata,H.Ishida,Y.Uemoto,T.Ueda,K.Inoue,T.Tanaka,“AlN Passivation Over AlGaN/GaN HFETs for Surface Heat Spreading”,IEEE Transactions on Electron Devices,Vol.57,No.5,pp.980-985,May 2010”提出了在氮化镓微波毫米波器件的表面上淀积一层氮化铝、“Z.Lin,C.Liu,C.Zhou,Y.Chai,M.Zhou and Y.Pei,"Improved performance of HEMTs with BN as heat dissipation,"2016 IEEE International Nanoelectronics Conference(INEC),Chengdu,2016,pp.1-2.”提出了在硅基氮化镓微波毫米波器件的表面上淀积一层氮化硼、“Marko J.Tadjer,Travis J.Anderson,Karl D.Hobart,Tatyana I.Feygelson,Joshua D.Caldwell,Charles R.Eddy,Jr.,Fritz J.Kub,James E.Butler,Bradford Pate,and John Melngailis,“Reduced self-heating in AlGaN/GaN HEMTs using nanocrystalline diamond Heat-spreading films”,IEEE electron device letters,Vol.33.No.1,pp.23-25,Jan.2012”提出了在氮化镓微波毫米波器件的表面上淀积一层纳米晶粒金刚石等，这类在氮化镓微波毫米波器件的表面上淀积高热导率介质材料的方法存在的缺点是：这些高热导率材料往往会带来额外的应力，影响器件的性能，或者造成器件长期可靠性的降低。
3、优化硅基氮化镓微波毫米波器件的版图设计，比如“K.Belkacemi and R.Hocine,“Efficient 3D-TLM Modeling and Simulation for theThermal Management of Microwave AlGaN/GaN HEMT Used in High Power Amplifiers SSPA,”Journal of Low Power Electronics and Applications,Vol.8,No.23,1-19,2018”提出了增加栅指间距，减少栅极密度，以减小发热源密度的方法，这种方法的缺点是会增加器件的面积，另外散热的效果也不高。
综上，如何提高硅基氮化镓微波毫米波器件的散热性能仍是目前亟待解决的问题。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种低热阻硅基氮化镓微波毫米波器件材料结构及制备方法。本发明要解决的技术问题通过以下技术方案实现：
本发明实施例提供了一种低热阻硅基氮化镓微波毫米波器件材料结构，包括：
硅衬底层；
高热导率介质层，位于所述硅衬底层的上表面，且与所述硅衬底层之间形成凹凸不平的第一图案化界面；
缓冲层，位于所述高热导率介质层的上表面，且与所述高热导率介质层之间形成凹凸不平的第二图案化界面；
沟道层，位于所述缓冲层的上表面；
复合势垒层，位于所述沟道层的上表面。
在本发明的一个实施例中，所述高热导率介质层的材料包括氮化铝、氮化硼、碳化硅或金刚石，厚度为20～20000nm。
在本发明的一个实施例中，所述第一图案化界面和所述第二图案化界面均包括形成有若干凹槽的界面，若干所述凹槽的面积占比为1％～99％。
在本发明的一个实施例中，若干所述凹槽规则排列，且若干所述凹槽的形状包括矩形、三角形、梯形中的一种或多种。
在本发明的一个实施例中，当所述若干所述凹槽的形状均为矩形时，每个所述凹槽的形状为矩形，所述矩形的深度为10nm～2000nm，所述矩形的宽度为10nm～10μm。
在本发明的一个实施例中，所述缓冲层的材料包括氮化镓、铝镓氮或氮化铝，厚度为100～5000nm；所述沟道层的材料为氮化镓，厚度为10～1000nm。
在本发明的一个实施例中，所述复合势垒层包括隔离层、核心势垒层和帽层，其中，
所述隔离层位于所述沟道层的上表面；
所述核心势垒层位于所述隔离层的上表面；
所述帽层位于所述核心势垒层的上表面。
在本发明的一个实施例中，所述复合势垒层包括隔离层和核心势垒层，其中，
所述隔离层位于所述沟道层的上表面；
所述核心势垒层位于所述隔离层的上表面。
在本发明的一个实施例中，所述复合势垒层包括核心势垒层和帽层，其中，
所述核心势垒层位于所述沟道层的上表面；
所述帽层位于所述核心势垒层的上表面。
本发明的另一个实施例提供了一种低热阻硅基氮化镓微波毫米波器件材料结构的制备方法，包括步骤：
获取初始衬底，所述初始衬底的材料为具有目标晶向的硅衬底基片；
在所述初始衬底上依次制备成核层和过渡层；
在所述过渡层上依次制备缓冲层、沟道层以及复合势垒层；
将样品翻转，并采用晶圆键合技术在翻转后的所述复合势垒层下表面制备过渡衬底；
去除所述初始衬底、所述成核层以及所述过渡层，以露出所述缓冲层；
对所述缓冲层表面进行刻蚀以形成第二图案化表面；
在所述缓冲层的所述第二图案化表面上淀积高热导率材料以形成高热导率介质层的第一部分；
对另一具有目标晶向的硅衬底层表面进行刻蚀以形成第一图案化表面；
在所述硅衬底层的所述第一图案化表面上淀积所述高热导率材料以形成所述高热 导率介质层的第二部分；
采用晶圆键合技术将所述高热导率介质层的第一部分与所述高热导率介质层的第二部分键合，形成所述高热导率介质层，所述高热导率介质层与所述硅衬底层之间形成凹凸不平的第一图案化界面且与所述缓冲层之间形成凹凸不平的第二图案化界面；
去除所述过渡衬底。
与现有技术相比，本发明的有益效果：
1、本发明的低热阻硅基氮化镓微波毫米波器件材料结构中，高热导率介质层与硅衬底层以及缓冲层之间均形成凹凸不平的图案化界面，增大了界面的接触面积，降低了界面热阻(TBR)，从而减小了器件的热阻，提高了器件的散热性能。
2、本发明的低热阻硅基氮化镓微波毫米波器件材料结构在高热导率介质层与缓冲层以及硅衬底界面形成图案化界面，相比平面化界面，减小了晶格间的压应力，提高了高热导率介质层的材料质量，从而提高了器件质量。
3、本发明的低热阻硅基氮化镓微波毫米波器件材料结构中采用高热导率介质层来实现硅衬底层与缓冲层之间的键合，保持了高键合强度、高机械强度、高稳定性，可以与现有生产线兼容，具有良率高和可靠性高的优点。
附图说明
图1是本发明实施例提供的一种低热阻硅基氮化镓微波毫米波器件材料结构的结构示意图；
图2是本发明实施例提供的另一种低热阻硅基氮化镓微波毫米波器件材料结构的结构示意图；
图3是本发明实施例提供的再一种低热阻硅基氮化镓微波毫米波器件材料结构的结构示意图；
图4是本发明实施例提供的又一种低热阻硅基氮化镓微波毫米波器件材料结构的结构示意图；
图5是本发明实施例提供的一种低热阻硅基氮化镓微波毫米波器件材料结构的制备方法的流程示意图；
图6a～6t是本发明实施例提供的一种低热阻硅基氮化镓微波毫米波器件材料结构的制备方法的过程示意图。
具体实施方式
下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。
实施例一
请参见图1，图1是本发明实施例提供的一种低热阻硅基氮化镓微波毫米波器件材料结构的结构示意图。该低热阻硅基氮化镓微波毫米波器件材料结构包括：
硅衬底层1；高热导率介质层2，位于硅衬底层1的上表面，且与硅衬底层1之间形成凹凸不平的第一图案化界面；缓冲层3，位于高热导率介质层2的上表面，且与高热导率介质层2形成凹凸不平的第二图案化界面；沟道层4，位于缓冲层3的上表面；复合势垒层5，位于沟道层4的上表面，从而构成低热阻硅基氮化镓微波毫米波器件材料结构。
在上述器件材料结构中，第一图案化界面和第二图案化界面的界面形状可以相同，也可以不同，只要满足凹凸不平的状态即可。
在一个具体实施例中，第一图案化界面和第二图案化界面均包括形成有若干凹槽G的界面；若干凹槽G可以规则排列，也可以不规则排列；每个凹槽G的形状可以为规则的，例如矩形、三角形、梯形等，也可以为不规则形状；在俯视图上，若干凹槽G的面积与图案化界面的面积比为1％～99％。可以理解的是，硅衬底层1的上表面设有规则排列或者不规则排列的凹槽G，以与高热导率介质层2形成图案化界面；缓冲层3的下表面设有规则排列或者不规则排列的凹槽G，以与高热导率介质层2形成图案化界面。
具体地，若干凹槽G规则排列，且每个凹槽G的形状为矩形，从俯视图上看，器件表面形成条纹状凹槽。更为具体地，当凹槽G为矩形时，凹槽G的深度可以为10nm～2000nm，凹槽G的宽度可以为10nm～10μm。
在一个具体实施例中，硅衬底层1为高阻硅，掺杂类型为n型或p型，电阻率为3000～30000Ω·cm，硅衬底层1的晶向为[111]。优选地，硅衬底层1电阻率为5000Ω·cm。
在一个具体实施例中，高热导率介质层2的材料可以包括氮化铝、氮化硼、碳化硅或金刚石，其厚度为20～20000nm。优选地，高热导率介质层2的材料为氮化铝，厚度为1000nm。
在一个具体实施例中，缓冲层3的材料包括氮化镓、铝镓氮或氮化铝，其厚度为100～5000nm。优选地，缓冲层3的材料为氮化镓，厚度为1000nm。
在一个具体实施例中，沟道层4的材料为氮化镓，厚度为10～1000nm。优选地，沟道层4的厚度为300nm。
在常规硅基氮化镓微波毫米波器件材料结构中，由于硅衬底层与缓冲层之间存在较大的晶格常数失配，因此需要引入一氮化铝成核层和一过渡层，过渡层可以是铝镓氮或氮化铝/氮化镓超晶格。但是成核层和过渡层的晶体质量很差，位错密度很高，热导率比较差，严重影响了硅基氮化镓微波毫米波功率器件的散热性能。同时，由于硅衬底层与氮化镓缓冲层之间存在较大的晶格失配，使得两种材料很难直接键合，形成稳定的硅基氮化镓微波毫米波器件材料结构。本实施例采用高热导率介质层2来实现硅衬底层1与缓冲层3之间的键合，既保持了器件的高键合强度、高机械强度、高稳定性，又减小了器件的热阻，从而提高了硅基氮化镓微波毫米波器件的散热性能，降低了器件工作的沟道温度，提高了器件的性能。
本实施例提供的硅基氮化镓微波毫米波器件材料结构在高热导率介质层与缓冲层、硅衬底层之间分别制备条纹状凹槽，形成图案化界面，与平面化界面相比，条纹槽不仅减小了晶格间的压应力，而且增大了高热导率介质层/缓冲层、高热导率介质层/硅衬底层的界面接触面积，使界面热阻(TBR)降低，从而减小了器件的热阻，降低了器件工作的沟道温度，提高了硅基氮化镓微波毫米波功率器件的散热性能。
请参见图2，图2是本发明实施例提供的另一种低热阻硅基氮化镓微波毫米波器件材料结构的结构示意图。该器件材料结构包括：硅衬底层1、高热导率介质层2、缓冲层3、沟道层4和复合势垒层5，其中，硅衬底层1、高热导率介质层2、缓冲层3、沟道层4的结构请参见图1，此处不再赘述。
复合势垒层5包括隔离层51和核心势垒层52，其中，隔离层51位于沟道层4的上表面；核心势垒层52位于隔离层51的上表面。
具体地，隔离层51的材料为氮化铝，厚度为0.5～1.5nm。优选地，隔离层51的厚度 为1nm。
具体地，核心势垒层52的材料为AlGaN，其中，铝的组分含量为0.2～0.4，厚度为10～30nm；或者为InAlN，其中，铟的组分含量为0.1～0.2，厚度为5～30nm；或者为AlN，厚度为2～10nm。优选地，核心势垒层52的材料为AlGaN，其中，铝的组分含量为0.25，厚度为20nm。
请参见图3，图3是本发明实施例提供的再一种低热阻硅基氮化镓微波毫米波器件材料结构的结构示意图。该器件材料结构包括：硅衬底层1、高热导率介质层2、缓冲层3、沟道层4和复合势垒层5，其中，硅衬底层1、高热导率介质层2、缓冲层3、沟道层4的结构请参见图1，此处不再赘述。
复合势垒层5包括核心势垒层52和帽层53，其中，核心势垒层52位于沟道层4的上表面；帽层53位于核心势垒层52的上表面。
具体地，核心势垒层52的材料及厚度请参见图2中的核心势垒层52的材料及厚度，此处不再赘述。
具体地，帽层53的材料为氮化镓，厚度为1～3nm；或者为氮化硅，厚度为1～10nm。优选地，帽层53的材料为氮化镓，厚度为3nm。
请参见图4，图4是本发明实施例提供的又一种低热阻硅基氮化镓微波毫米波器件材料结构的结构示意图。该器件材料结构包括：硅衬底层1、高热导率介质层2、缓冲层3、沟道层4和复合势垒层5，其中，硅衬底层1、高热导率介质层2、缓冲层3、沟道层4的结构请参见图1，此处不再赘述。
复合势垒层5包括隔离层51、核心势垒层52和帽层53，其中，隔离层51位于沟道层4的上表面；核心势垒层52位于隔离层51的上表面；帽层53位于核心势垒层52的上表面。
隔离层51、核心势垒层52和帽层53的材料及厚度请参见图2和图3中的材料及厚度，此处不再赘述。
本实施例提供的硅基氮化镓微波毫米波器件材料结构通过高热导率介质层分别与缓冲层、硅衬底界面形成图案化界面，减小了器件的热阻，提高了器件的导热率，沟道层制作在缓冲层的上表面，为器件提供了导电沟道，复合势垒层制作在沟道层的上表面，复合势垒层与沟道层之间的界面处形成二维电子气，作为器件的导电沟道，且通过隔离层或帽层进一步提高了器件的电学特性。
综上，本实施例提供的低热阻硅基氮化镓微波毫米波器件材料结构制备微波毫米波功率器件，能够有效减小器件热阻，提高器件散热性能，从而提高器件的最高输出功率和效率等性能指标，且具有良好的电学特性；同时，还具有与现有生产线兼容、良率高和可靠性高的优点，可应用于射频、微波、毫米波的芯片和系统等领域。
实施例二
在实施例一的基础上，本实施例提供了一种低热阻硅基氮化镓微波毫米波器件材料结构的制备方法。
请参见图5和图6a～6t，图5是本发明实施例提供的一种低热阻硅基氮化镓微波毫米波器件材料结构的制备方法的流程示意图，图6a～6t是本发明实施例提供的一种低热阻硅基氮化镓微波毫米波器件材料结构的制备方法的过程示意图。该制备方法包括步骤：
S1、获取初始衬底11，初始衬底11的材料为具有目标晶向的硅衬底基片，如图6a 所示。
本实施例选取具有目标晶向的硅衬底基片作为初始衬底11，该硅衬底基片为高阻硅衬底。具体地，该硅衬底基片的电阻率为5000Ω·cm，晶向为[111]，尺寸为8寸，厚度为725μm。
S2、在初始衬底11上依次制备成核层12和过渡层13。
本实施例中需要在初始衬底上制备成核层12和过渡层13，以方便后续制备缓冲层3。
具体地，首先采用金属有机化合物化学气相淀积(Metal-Organic Chemical Vapor Deposition，简称MOCVD)设备与技术在初始衬底11上外延生长成核层12，其中，成核层12的材料可以是氮化铝材料，其厚度可以为200nm，如图6b所示。
然后，继续采用MOCVD设备与技术在成核层12上外延生长过渡层13，其中，过渡层13的材料可以是氮化铝/氮化镓超晶格材料，厚度可以为1000nm，如图6c所示。
S3、在过渡层上依次制备缓冲层、沟道层以及复合势垒层。
S31、在过渡层13上制备缓冲层3。
采用MOCVD设备与技术在步骤S2制备的过渡层13上外延生长缓冲层3，其中，缓冲层3可以是进行了Fe掺杂的缓冲层3，其位错密度为1e9cm -2，其电阻率为1MΩ·cm，如图6d所示。
S32、在缓冲层3上制备沟道层4。
具体地，采用MOCVD设备与技术，在缓冲层3上外延生长沟道层4，其中，沟道层4可以为非故意掺杂氮化镓沟道层4，其厚度可以为300nm，如图6e所示。
S33、在沟道层4上制备复合势垒层5。
具体地，复合势垒层5可以有几种结构，一是包括隔离层51和核心势垒层52；二是包括核心势垒层52和帽层53；三是包括隔离层51、核心势垒层52和帽层53。本实施例以复合势垒层5包括隔离层51、核心势垒层52和帽层53为例进行制备方法说明，其余两种结构制备方法类似。
首先，采用MOCVD设备与技术，在沟道层4上外延生长隔离层51；其中，隔离层51的材料可以为氮化铝，厚度可以为1nm，如图6f所示。
然后，采用MOCVD设备与技术，在隔离层51上外延生长核心势垒层52；其中，核心势垒层52可以是铝组分为0.25的AlGaN，其厚度可以为20nm，如图6g所示。
最后，采用MOCVD设备与技术，在核心势垒层52上外延生长帽层53，以形成复合势垒层5，其中，帽层53的材料可以是氮化镓，厚度可以为3nm；从而制作形成第一晶圆10，如图6h所示。
本实施例是通过在硅衬底上依次制备成核层、过渡层、缓冲层、沟道层以及复合势垒层的，在实际制备过程中，为了节约时间和成本，也可以选取包括硅衬底、成核层、过渡层、缓冲层、沟道层以及复合势垒层的常规硅基氮化镓外延片直接进行后续制备工艺。
S4、将样品翻转，并采用晶圆键合技术在翻转后的复合势垒层5下表面制备过渡衬底。
S41、采用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor  Deposition，简称PECVD)的设备和技术在步骤S3得到的第一晶圆10的上表面，即复合势垒层5的表面淀积250nm厚的第一二氧化硅层21，制作形成第二晶圆20，如图6i所示。
S42、制备硅晶圆作为过渡衬底。
选取具有目标晶向的硅晶圆31；其中，该硅晶圆31的电阻率可以为10Ω·cm，晶向为[100]，尺寸为8寸，厚度为725μm。
采用PECVD设备和技术，在硅晶圆31上表面淀积一层厚度为250nm的第二二氧化硅层32，制作形成第三晶圆30，如图6j所示。
S43、将步骤S42所得的样品翻转，并通过晶圆键合技术将步骤S31中制作的第一二氧化硅层21与步骤S42中制作的第二二氧化硅层32表面键合在一起，以在复合势垒层下面形成过渡衬底，制作形成第四晶圆40，如图6k所示。
S5、去除初始衬底11、成核层12以及过渡层13，以露出缓冲层3。
具体地，采用湿法化学腐蚀技术或等离子体刻蚀技术依次去除初始衬底11、成核层12以及过渡层13，以使缓冲层3暴露在样品表面。
首先，采用湿法化学腐蚀技术或等离子体刻蚀技术，将步骤S43制作的第四晶圆40中初始衬底11去除，制作形成第五晶圆50，如图6l所示。
然后，采用湿法化学腐蚀技术或等离子体刻蚀技术，将上述制作得到的第五晶圆50中成核层12去除，制作形成第六晶圆60，如图6m所示。
最后，采用湿法化学腐蚀技术或等离子体刻蚀技术，将上述制作得到的第六晶圆60中的过渡层13去除，制作形成第七晶圆70，如图6n所示。
S6、对缓冲层3表面进行刻蚀以形成第二图案化表面。
具体地，采用光刻工艺和刻蚀工艺，对步骤S5得到的第七晶圆70上表面的缓冲层3表面进行图案化制备，以形成凹凸不平的第二图案化表面，制作形成第八晶圆80，如图6o所示。
其中，凹凸不平的第二图案化表面可以为具有凹槽G阵列的图案化表面，凹槽G可以规则排列，也可以不规则排列，其形状可以为矩形、三角形、梯形等任意规则形状，也可以为不规则形状；当为矩形时，凹槽G阵列深度可以为10nm～2000nm，凹槽G宽度为10nm～10μm，凹槽G的面积占比为1％～99％，优选地，凹槽G的深度为500nm，凹槽G宽度为1μm，凹槽G的面积占比为50％。
S7、在缓冲层3的第二图案化表面上淀积高热导率材料以形成高热导率介质层2的第一部分。
具体地，采用磁控溅射技术与设备，在步骤S6得到的第八晶圆80中缓冲层3的第二图案化表面上淀积高热导率材料，以形成高热导率介质层2的第一部分91；其中，高热导率介质层2的厚度可以为20～20000nm，制作形成第九晶圆90，如图6p所示。
优选地，高热导率介质层2的材料为氮化铝，厚度为1μm。
S8、对另一具有目标晶向的硅衬底层1表面进行刻蚀以形成第一图案化表面。
具体地，硅衬底层1的尺寸为8寸，厚度为725μm，电阻率为5000Ω·cm，晶向为[111]。
具体地，采用光刻工艺和刻蚀工艺，对硅衬底层1的上表面进行图案化制备，以形成具有凹槽阵列的第一图案化表面，制作形成第十晶圆100，如图6q所示。
其中，凹凸不平的第一图案化表面可以为具有凹槽G阵列的图案化表面，凹槽G可以规则排列，也可以不规则排列，其形状可以为矩形、三角形、梯形等任意规则形状，也可以为不规则形状；当为矩形时，凹槽G阵列深度可以为10nm～2000nm，凹槽G宽度为10nm～10μm，凹槽G的面积占比为1％～99％，优选地，凹槽G的深度为500nm，凹槽G宽度为1μm，凹槽G的面积占比为50％。
S9、在硅衬底层1的第一图案化表面上淀积高热导率材料以形成高热导率介质层2的第二部分101。
具体地，采用磁控溅射技术与设备，在步骤S8得到的第十晶圆100中硅衬底层的第一图案化表面上淀积高热导率材料，以形成高热导率介质层2的第二部分101，制作形成第十一晶圆110，如图6r所示。
其中，高热导率介质层2的厚度可以为20～20000nm。优选地，高热导率介质层2的材料为氮化铝，厚度为1μm。
本实施例中，硅衬底层1的第一图案化表面对应形成高热导率介质层2与硅衬底层1之间的第一图案化界面，缓冲层3的第二图案化表面对应形成高热导率介质层2与缓冲层3之间的第二图案化界面。
S10、采用晶圆键合技术将高热导率介质层2的第一部分91与高热导率介质层2的第二部分101键合，形成高热导率介质层2，高热导率介质层2与硅衬底层1之间形成凹凸不平的第一图案化界面且与缓冲层3之间形成凹凸不平的第二图案化界面。
具体地，采用晶圆化学键键合技术，将步骤S7制作的第九晶圆90中高热导率介质层2的第一部分91与步骤S9制作的第十一晶圆110中高热导率介质层2的第二部分101键合在一起，以在缓冲层3与硅衬底层1之间制备双面图案化界面的高热导率介质层，制作形成第十二晶圆120，如图6s所示。
其中，第一图案化界面和第二图案化界面的具体状态请参见实施例一，本实施例不再赘述。
S11、去除过渡衬底。
具体地，采用湿法化学腐蚀技术或等离子体刻蚀技术，依次去除步骤S4中制作的硅晶圆31、第二二氧化硅层21和第一二氧化硅层32，最终得到硅基氮化镓微波毫米波器件材料结构。
首先，采用湿法化学腐蚀技术或等离子体刻蚀技术，将制作得到的第十一晶圆110中的硅晶圆31去除，制作形成第十三晶圆130，如图6t所示。
然后，采用湿法化学腐蚀技术或等离子体刻蚀技术，将制作的第十三晶圆130中的第二二氧化硅层32和第一二氧化硅层21去除，最终形成本实施例的硅基氮化镓微波毫米波器件材料结构，如图4所示。其中，高热导率介质层2包括第一部分91和第二部分101。
至此，完成硅基氮化镓微波毫米波器件材料结构的制备。
本实施例提供的制备方法通过光刻工艺和刻蚀工艺对缓冲层下表面与硅衬底上表面进行图案化制备，以形成条纹状凹槽，再使用磁控溅射和晶圆键合的方法淀积高热导率介质层材料，与缓冲层以及硅衬底界面分别形成了图案化界面，与平面化界面相比，条纹凹槽不仅减小了晶格间的压应力，而且增大了高热导率介质层/缓冲层、高热导率介 质层/硅衬底层的界面接触面积，使界面热阻(TBR)降低，从而减小了器件的热阻，降低了器件工作的沟道温度，提高了硅基氮化镓微波毫米波功率器件的散热性能。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种低热阻硅基氮化镓微波毫米波器件材料结构，其特征在于，包括：
    硅衬底层(1)；
    高热导率介质层(2)，位于所述硅衬底层(1)的上表面，且与所述硅衬底层(1)之间形成凹凸不平的第一图案化界面；
    缓冲层(3)，位于所述高热导率介质层(2)的上表面，且与所述高热导率介质层(2)之间形成凹凸不平的第二图案化界面；
    沟道层(4)，位于所述缓冲层(3)的上表面；
    复合势垒层(5)，位于所述沟道层(4)的上表面。
  2. 如权利要求1所述的低热阻硅基氮化镓微波毫米波器件材料结构，其特征在于，所述高热导率介质层(2)的材料包括氮化铝、氮化硼、碳化硅或金刚石，厚度为20～20000nm。
  3. 如权利要求1所述的低热阻硅基氮化镓微波毫米波器件材料结构，其特征在于，所述第一图案化界面和所述第二图案化界面均包括形成有若干凹槽(G)的界面，若干所述凹槽(G)的面积占比为1％～99％。
  4. 如权利要求3所述的低热阻硅基氮化镓微波毫米波器件材料结构，其特征在于，若干所述凹槽(G)规则排列，且若干所述凹槽(G)的形状包括矩形、三角形、梯形中的一种或多种。
  5. 如权利要求4所述的低热阻硅基氮化镓微波毫米波器件材料结构，其特征在于，当若干所述凹槽(G)的形状均为矩形时，所述矩形的深度为10nm～2000nm，所述矩形的宽度为10nm～10μm。
  6. 如权利要求1所述的低热阻硅基氮化镓微波毫米波器件材料结构，其特征在于，所述缓冲层(3)的材料包括氮化镓、铝镓氮或氮化铝，厚度为100～5000nm；所述沟道层(4)的材料为氮化镓，厚度为10～1000nm。
  7. 如权利要求1所述的低热阻的硅基氮化镓微波毫米波器件材料结构，其特征在于，所述复合势垒层(5)包括隔离层(51)、核心势垒层(52)和帽层(53)，其中，
    所述隔离层(51)位于所述沟道层(4)的上表面；
    所述核心势垒层(52)位于所述隔离层(51)的上表面；
    所述帽层(53)位于所述核心势垒层(52)的上表面。
  8. 如权利要求1所述的低热阻硅基氮化镓微波毫米波器件材料结构，其特征在于，所述复合势垒层(5)包括隔离层(51)和核心势垒层(52)，其中，
    所述隔离层(51)位于所述沟道层(4)的上表面；
    所述核心势垒层(52)位于所述隔离层(51)的上表面。
  9. 如权利要求1所述的低热阻硅基氮化镓微波毫米波器件材料结构，其特征在于，所述复合势垒层(5)包括核心势垒层(52)和帽层(53)，其中，
    所述核心势垒层(52)位于所述沟道层(4)的上表面；
    所述帽层(53)位于所述核心势垒层(52)的上表面。
  10. 一种低热阻硅基氮化镓微波毫米波器件材料结构的制备方法，其特征在于，包括步骤：
    获取初始衬底，所述初始衬底的材料为具有目标晶向的硅衬底基片；
    在所述初始衬底上依次制备成核层和过渡层；
    在所述过渡层上依次制备缓冲层、沟道层以及复合势垒层；
    将样品翻转，并采用晶圆键合技术在翻转后的所述复合势垒层下表面制备过渡衬底；
    去除所述初始衬底、所述成核层以及所述过渡层，以露出所述缓冲层；
    对所述缓冲层表面进行刻蚀以形成第二图案化表面；
    在所述缓冲层的所述第二图案化表面上淀积高热导率材料以形成高热导率介质层的第一部分；
    对另一具有目标晶向的硅衬底层表面进行刻蚀以形成第一图案化表面；
    在所述硅衬底层的所述第一图案化表面上淀积所述高热导率材料以形成所述高热导率介质层的第二部分；
    采用晶圆键合技术将所述高热导率介质层的第一部分与所述高热导率介质层的第二部分键合，形成所述高热导率介质层，所述高热导率介质层与所述硅衬底层之间形成凹凸不平的第一图案化界面且与所述缓冲层之间形成凹凸不平的第二图案化界面；
    去除所述过渡衬底。
PCT/CN2021/079283 2020-08-25 2021-03-05 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法 WO2022041674A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/282,190 US20220310796A1 (en) 2020-08-25 2021-03-05 Material structure for low thermal resistance silicon-based gallium nitride microwave and millimeter-wave devices and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010864740.5 2020-08-25
CN202010864740.5A CN112216739B (zh) 2020-08-25 2020-08-25 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法

Publications (1)

Publication Number Publication Date
WO2022041674A1 true WO2022041674A1 (zh) 2022-03-03

Family

ID=74059347

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/079283 WO2022041674A1 (zh) 2020-08-25 2021-03-05 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法

Country Status (3)

Country Link
US (1) US20220310796A1 (zh)
CN (1) CN112216739B (zh)
WO (1) WO2022041674A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112216739B (zh) * 2020-08-25 2022-08-12 西安电子科技大学 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法
CN113380876A (zh) * 2021-06-10 2021-09-10 四川美阔电子科技有限公司 一种氮化镓功率器件结构及制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN200969729Y (zh) * 2006-10-13 2007-10-31 郭金湖 散热体的接合结构及以该散热体制成的散热器
CN104201202A (zh) * 2014-09-17 2014-12-10 电子科技大学 一种具有复合势垒层的氮化镓基异质结场效应管
WO2019136864A1 (zh) * 2018-01-12 2019-07-18 中国科学院苏州纳米技术与纳米仿生研究所 基于复合势垒层结构的iii族氮化物增强型hemt及其制作方法
CN112216739A (zh) * 2020-08-25 2021-01-12 西安电子科技大学 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5729052A (en) * 1996-06-20 1998-03-17 International Business Machines Corporation Integrated ULSI heatsink
US6281573B1 (en) * 1998-03-31 2001-08-28 International Business Machines Corporation Thermal enhancement approach using solder compositions in the liquid state
US8545629B2 (en) * 2001-12-24 2013-10-01 Crystal Is, Inc. Method and apparatus for producing large, single-crystals of aluminum nitride
JP4221697B2 (ja) * 2002-06-17 2009-02-12 日本電気株式会社 半導体装置
US7170111B2 (en) * 2004-02-05 2007-01-30 Cree, Inc. Nitride heterojunction transistors having charge-transfer induced energy barriers and methods of fabricating the same
US20060209516A1 (en) * 2005-03-17 2006-09-21 Chengalva Suresh K Electronic assembly with integral thermal transient suppression
US20060226442A1 (en) * 2005-04-07 2006-10-12 An-Ping Zhang GaN-based high electron mobility transistor and method for making the same
US7388236B2 (en) * 2006-03-29 2008-06-17 Cree, Inc. High efficiency and/or high power density wide bandgap transistors
US20080073070A1 (en) * 2006-09-26 2008-03-27 Chin-Hu Kuo Highly efficient heat dissipating composite material and a heat dissipating device made of such material
JP5891650B2 (ja) * 2011-08-18 2016-03-23 富士通株式会社 化合物半導体装置及びその製造方法
JP5883331B2 (ja) * 2012-01-25 2016-03-15 住友化学株式会社 窒化物半導体エピタキシャルウェハの製造方法及び電界効果型窒化物トランジスタの製造方法
CN105140122B (zh) * 2015-08-10 2018-07-20 中国电子科技集团公司第五十五研究所 一种改善GaN HEMT器件散热性能的方法
KR102424402B1 (ko) * 2015-08-13 2022-07-25 삼성전자주식회사 반도체 패키지 및 그 제조방법
CN207068868U (zh) * 2017-06-23 2018-03-02 同辉电子科技股份有限公司 一种硅基氮化镓功率器件
JP2019125737A (ja) * 2018-01-18 2019-07-25 株式会社サイオクス 窒化物半導体エピタキシャル基板
US20200194333A1 (en) * 2018-12-13 2020-06-18 Board Of Trustees Of The University Of Arkansas Apparatus And Method To Reduce The Thermal Resistance Of Semiconductor Substrates

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN200969729Y (zh) * 2006-10-13 2007-10-31 郭金湖 散热体的接合结构及以该散热体制成的散热器
CN104201202A (zh) * 2014-09-17 2014-12-10 电子科技大学 一种具有复合势垒层的氮化镓基异质结场效应管
WO2019136864A1 (zh) * 2018-01-12 2019-07-18 中国科学院苏州纳米技术与纳米仿生研究所 基于复合势垒层结构的iii族氮化物增强型hemt及其制作方法
CN112216739A (zh) * 2020-08-25 2021-01-12 西安电子科技大学 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法

Also Published As

Publication number Publication date
US20220310796A1 (en) 2022-09-29
CN112216739A (zh) 2021-01-12
CN112216739B (zh) 2022-08-12

Similar Documents

Publication Publication Date Title
US11239348B2 (en) Wafer bonded GaN monolithic integrated circuits and methods of manufacture of wafer bonded GaN monolithic integrated circuits
CN100511706C (zh) 基于组份渐变GaN MISFET的GaN器件及制备方法
CN110112215B (zh) 兼具栅介质与刻蚀阻挡功能结构的功率器件及制备方法
CN109037066B (zh) 半导体器件及其制造方法
US20130200387A1 (en) Nitride based heterojunction semiconductor device and manufacturing method thereof
US20230402525A1 (en) Manufacturing method for n-polar gan transistor structure and semiconductor structure
WO2022041674A1 (zh) 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法
WO2022199309A1 (zh) 具有p-GaN盖帽层的HEMT器件及制备方法
CN116314349B (zh) 具有P型二维材料插层的GaN基功率肖特基二极管及制备工艺
CN111863957A (zh) 一种常闭型高电子迁移率晶体管及其制造方法
CN111653473B (zh) 一种散热增强的硅基氮化镓微波器件材料结构
CN110931547A (zh) 一种hemt器件及其制备方法
CN111211161A (zh) 一种双向散热的纵向氮化镓功率晶体管及其制备方法
CN115763533A (zh) 凹槽填充介质隔离漏电的同质外延GaN HEMT器件及其制作方法
CN213212169U (zh) 一种半导体器件的外延结构及半导体器件
CN111952175B (zh) 晶体管的凹槽制作方法及晶体管
RU2534442C1 (ru) Способ изготовления мощного свч-транзистора
KR20210082523A (ko) 화합물 반도체 장치, 화합물 반도체 기판, 및 화합물 반도체 장치의 제조방법
CN114497193B (zh) 一种resfet器件及其制备方法
CN114497192B (zh) 一种resfet器件及其制备方法
CN220233200U (zh) 一种氮化镓外延结构
CN114497185B (zh) 一种碳掺杂绝缘层的制备方法、hemt器件及其制备方法
WO2022151202A1 (zh) 半导体结构及其制备方法、电子设备
TWI797751B (zh) 半導體結構及其製作方法
CN116936645B (zh) 一种p沟道肖特基势垒二极管及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21859523

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21859523

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 21859523

Country of ref document: EP

Kind code of ref document: A1