CN110931547A - 一种hemt器件及其制备方法 - Google Patents

一种hemt器件及其制备方法 Download PDF

Info

Publication number
CN110931547A
CN110931547A CN201911018210.2A CN201911018210A CN110931547A CN 110931547 A CN110931547 A CN 110931547A CN 201911018210 A CN201911018210 A CN 201911018210A CN 110931547 A CN110931547 A CN 110931547A
Authority
CN
China
Prior art keywords
layer
protective layer
gallium nitride
hemt device
algan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911018210.2A
Other languages
English (en)
Inventor
刘新科
邓煊华
利键
陈勇
王佳乐
胡聪
贺威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen University
Original Assignee
Shenzhen University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen University filed Critical Shenzhen University
Priority to CN201911018210.2A priority Critical patent/CN110931547A/zh
Publication of CN110931547A publication Critical patent/CN110931547A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

本发明的目的是提供一种HEMT器件及其制备方法,与现有技术相比,本发明的HEMT器件具备高电阻率、高电子迁移率,通过氧离子注入形成高阻氮化镓和Al2O3。比传统器件具有良好的电流密度和低泄漏电流,更高的器件击穿电压,具有良好导热性使器件能在较高温条件下工作。而且通过自支撑衬底材料,解决了现有的外延层晶格失配大,缺陷密度大的问题,改善了界面性能,进一步的提升了HEMT器件的性能、良品率。

Description

一种HEMT器件及其制备方法
技术领域
本发明属于半导体技术中的器件制造领域,具体的涉及一种HEMT器件及其制备方法。
背景技术
GaN基材料具有禁带宽度大、击穿场强高、极化系数高、电子迁移率和电子饱和漂移速度高等一系列材料性能优势,是制备新一代高性能电力电子器件的优选材料,具有重要的应用前景。GaN基材料对于光电子器件和微电子器件都有着极大的吸引力。GaN基材料具有禁带宽、击穿电压高、电子饱和漂移速度高以及热稳定性好等特点,而且同AlGaN合金材料能构成理想的异质结,其异质界面上大的导带偏移以及GaN基材料自身高的压电极化和自发极化强度可产生高密度的二维电子气,电子气密度比AlGaAs/GaAs异质结高约一个数量级,因而适于制作高温、高频、大功率电子器件。
目前,AlGaN/GaN异质结HEMT器件由于其电子饱和速度高、击穿场强高、截止频率高、饱和电流高等特点,十分适合高频高功率的工作场合,但面临着两个问题:散热性能不佳与饱和电子速率受限。目前最广泛应用的生长GaN材料的衬底是蓝宝石衬底,具有成本低、技术成熟、稳定性好、机械强度高等优点。
现阶段,由于异质结界面处的二维电子气存在,在实际应用中需要相对复杂的栅驱动电路,以及不满足失效安全要求。因此,在GaN基功率电子器件应用中,增强型GaN基HEMT成为了重要的技术目标。
但是传统的AlGaN/GaN异质结HEMT器件散热性能不好,不能在较高温条件下工作。同类产品大多使用非自支撑氮化镓衬底材料,造成外延层晶格失配大,缺陷密度大,材料生长工艺复杂。
因此合理的设计一种HEMT器件以及配套的可实施的制备方法来克服现有技术的不足是十分有必要的。
发明内容
本发明的目的是提供一种HEMT器件,以解决现有的HEMT器件散热性能不好,不能在较高温条件下工作、外延层晶格失配大,缺陷密度大的技术问题。
本发明另一目的是提供一种HEMT器件的制备方法,以解决现有的HEMT器件的制备方法工艺复杂,且制备出来的器件散热性能差,界面性能不佳的技术问题。
为了实现上述发明目的,本发明的一方面,提供了一种HEMT器件,包括:
AlGaN层,所述AlGaN层结合于所述衬底的一表面;
源极和漏极,分别欧姆接触设置于所述AlGaN层的彼此间隔两部分的表面上;
缓冲层,所述缓冲层包括第一保护层、AlN层、第二保护层;所述第一保护层与第二保护层分别贴合设置于所述AlN层的两侧,且所述第一保护层的一端与所述源极的一端紧贴设置,所述第二保护层的一端与所述漏极的一端紧贴设置;所述缓冲层层叠结合于所述AlGaN层背离所述衬底的表面;
P型GaN层,层叠结合于所述AlN层背离所述AlGaN层的表面;所述P型GaN层的两侧贴合有第一高阻氮化镓层,第二高阻氮化镓层,且所述第一高阻氮化镓层的一端与所述源极的一端紧贴设置,所述第二高阻氮化镓层的一端与所述漏极的一端紧贴设置;所述第一高阻氮化镓层,第二高阻氮化镓层分别层叠结合于所述第一保护层与第二保护层背离所述AlGaN层的表面;
栅极,层叠结合于所述P型GaN层背离所述AlN层的表面;
钝化保护层,覆盖于所述源极、漏极、第一高阻氮化镓层,第二高阻氮化镓层、栅极所形成的表面,且所述源极、漏极、栅极的上表面有部分裸露。
优选地,所述衬底的材料为碳化硅、蓝宝石、硅片中的任意一种。
优选地,所述第一保护层和第二保护层的材料为Al2O3。
优选地,所述钝化保护层的材料为SiN。
优选地,所述的HEMT器件,其特征在于:
所述AlGaN层的厚度为12nm;
所述第一保护层、AlN层、第二保护层的厚度为2nm:
所述第一高阻氮化镓层,第二高阻氮化镓层、p型掺杂GaN层的厚度为70-100nm;
所述钝化保护层的厚度为20nm。
本发明另一方面提供了所述的HEMT器件的制备方法,其特征在于,包括如下步骤:
在衬底一表面生长AlGaN层;
利用光刻胶遮挡住所述AlGaN层的中部,在所述AlGaN层两端采用蒸镀方式制备源极和漏极;
沿衬底一表面向外延伸的方向,在所述AlGaN层上,源极和漏极之间依次生长缓冲层和p型掺杂GaN层;
在所述p型掺杂GaN层中部蒸镀栅极;
在所述p型掺杂GaN层和缓冲层未被栅极覆盖的两侧注入氧离子;
在器件表面生长一层钝化保护层,且在源极、漏极、栅极上表面通过提前遮挡留下部分裸露。
优选地,所述AlGaN层通过高温MOCVD外延法生长。
进一步优选地,所述AlGaN层生长采用三甲基镓作为镓源,三甲基铝作为铝源,氨气作为氮源。
优选地,所述p型掺杂GaN层采用金属有机物化学气相沉积法制备。
进一步优选地,所述p型掺杂GaN层采用尿素为氮源,液态金属镓为镓源,环戊二烯基镁可以用作p型掺杂剂。
与现有技术相比,本发明的HEMT器件具备高电阻率、高电子迁移率,通过氧离子注入形成高阻氮化镓和Al2O3。比传统器件具有良好的电流密度和低泄漏电流,更高的器件击穿电压,具有良好导热性使器件能在较高温条件下工作。而且通过自支撑衬底材料,解决了现有的外延层晶格失配大,缺陷密度大的问题,改善了界面性能,进一步的提升了HEMT器件的性能,良品率。
本发明的HEMT器件的制备方法采用支撑衬底材料作为衬底,一方面简化了生长工艺,自源性的衬底还能明显改善界面性能。同时由于生长工艺简化,加上界面性能的改善,能在提升器件性能的同时大大提升良品率。
附图说明
图1为本发明实施例所述HEMT器件的结构示意图
具体实施方式
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白,以下结合实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
本发明实施例中,对下文名词作出如下说明。
HEMT器件:High Electron Mobility Transistor,高电子迁移率晶体管。
MOCVD法:MOCVD是以Ⅲ族、Ⅱ族元素的有机化合物和V、Ⅵ族元素的氢化物等作为晶体生长源材料,以热分解反应方式在衬底上进行气相外延,生长各种Ⅲ-V主族、Ⅱ-Ⅵ副族化合物半导体以及它们的多元固溶体的薄层单晶材料。
一方面本发明实施例提供了一种HEMT器件,包括:
衬底1;在优选实施例中,所述衬底1的材料为碳化硅、蓝宝石、硅片中的任意一种。这些都是常用的衬底,制备工艺成熟,性能很好;目前最广泛应用的生长GaN材料的衬底是蓝宝石衬底,具有成本低、技术成熟、稳定性好、机械强度高等优点。
AlGaN层2,所述AlGaN层2结合于所述衬底1的一表面;在一优选实施例中,所述AlGaN层2的厚度为12nm;
源极3和漏极4,分别欧姆接触设置于所述AlGaN层2的彼此间隔两部分的表面上;
缓冲层5,所述缓冲层包括第一保护层5a、AlN层5c、第二保护层5b;所述第一保护层5a与第二保护层5b分别贴合设置于所述AlN层5c的两侧,且所述第一保护层5a的一端与所述源极3的一端紧贴设置,所述第二保护层5b的一端与所述漏极4的一端紧贴设置;所述缓冲层5层叠结合于所述AlGaN2层背离所述衬底1的表面;在一优选实施例中,所述第一保护层5a和第二保护层5b的材料为Al2O3。在另一优选实施例中,所述第一保护层5a、AlN层5c、第二保护层5b的厚度为2nm:
P型GaN层6c,层叠结合于所述AlN层背离所述AlGaN层5c的表面;所述第一高阻氮化镓层6a,第二高阻氮化镓层6b分别贴合设置于所述P型GaN层6c的两侧,且所述第一高阻氮化镓层6a的左侧与所述源极3的右侧紧贴设置,所述第二高阻氮化镓层6b的一端与所述漏极4的一端紧贴设置;所述第一高阻氮化镓层6a,第二高阻氮化镓层6b分别层叠结合于所述第一保护层5a与第二保护层5b背离所述AlGaN层2的表面;在优选实施例中,所述第一高阻氮化镓层6a,第二高阻氮化镓层6b、p型掺杂GaN层6c的厚度为70-100nm;
栅极7,层叠结合于所述P型GaN层6c背离所述AlN层5c的表面;
钝化保护层8,覆盖于所述源极3、漏极4、第一高阻氮化镓层6a,第二高阻氮化镓层6b、栅极7所形成的表面,且所述源极3、漏极4、栅极7的上表面有部分裸露。在优选实施例中,所述钝化保护层8的材料为SiN。在另一优选实施例中,所述钝化保护层8的厚度为20nm。
本发明另一方面提供了所述的HEMT器件的制备方法,其特征在于,包括如下步骤:
S01:在衬底一表面生长AlGaN层;
S02:利用光刻胶遮挡住所述AlGaN层的中部,在所述AlGaN层两端采用蒸镀方式制备源极和漏极;
S03:沿衬底一表面向外延伸的方向,在所述AlGaN层上,源极和漏极之间依次生长缓冲层和p型掺杂GaN层;
S04:在所述p型掺杂GaN层中部蒸镀栅极;
S05:在所述p型掺杂GaN层和缓冲层未被栅极覆盖的两侧注入氧离子;
S06:在器件表面生长一层钝化保护层,且在源极、漏极、栅极上表面通过提前遮挡留下部分裸露。
具体的在所述步骤S01中,所述AlGaN层通过高温MOCVD外延法生长。由于Al原子的迁移率较低,因此采用高温MOCVD外延的方法提高Al原子迁移率,降低缺陷密度,提高材料质量。
更具体的在所述步骤S01中,所述AlGaN层生长采用三甲基镓作为镓源,三甲基铝作为铝源,氨气作为氮源。
更具体的,所述步骤S02中,所述源极和漏极的制备方法是利用光刻技术,利用光刻胶遮挡中部薄膜部分及顶部电极,然后通过真空蒸发或者电子束蒸发制备欧姆接触金属电极,此时金属为Ti(15nm)/Al(150-200nm)/Ti(15nm)/Au(150-200nm)形成欧姆结构,最后用退火系统在氮气气氛中875℃退火35s,制作出源极和漏极,
具体的在所述步骤S03中,所述p型掺杂GaN层采用金属有机物化学气相沉积法制备。
更具体的在所述步骤S03中,所述p型掺杂GaN层采用尿素为氮源,液态金属镓为镓源,环戊二烯基镁可以用作p型掺杂剂。
本发明实施例利用氧离子注入的方法形成高阻氮化镓钝化层,提高了器件的性能。与传统的蚀刻工艺相比,HR-HEMT具有良好的电流密度和低泄漏电流。Al2O3层也有效的提高了HEMT的输出电流,起到保护的作用,提高了器件的击穿电压。另外,本发明实施例采用自支撑氮化镓衬底,这使得同质外延的器件材料缺陷低,质量高,有利于增大器件的输出电流。最后通过层结构的生长条件的优选,进一步提升了制备效率,并提升了所制备的器件的性能。

Claims (10)

1.一种HEMT器件,其特征在于,包括:
衬底;
AlGaN层,所述AlGaN层结合于所述衬底的一表面;
源极和漏极,分别欧姆接触设置于所述AlGaN层的彼此间隔两部分的表面上;
缓冲层,所述缓冲层包括第一保护层、AlN层、第二保护层;所述第一保护层与第二保护层分别贴合设置于所述AlN层的两侧,且所述第一保护层的一端与所述源极的一端紧贴设置,所述第二保护层的一端与所述漏极的一端紧贴设置;所述缓冲层层叠结合于所述AlGaN层背离所述衬底的表面;
P型GaN层,层叠结合于所述AlN层背离所述AlGaN层的表面;所述P型GaN层的两侧贴合有第一高阻氮化镓层,第二高阻氮化镓层,且所述第一高阻氮化镓层的一端与所述源极的一端紧贴设置,所述第二高阻氮化镓层的一端与所述漏极的一端紧贴设置;所述第一高阻氮化镓层,第二高阻氮化镓层分别层叠结合于所述第一保护层与第二保护层背离所述AlGaN层的表面;
栅极,层叠结合于所述P型GaN层背离所述AlN层的表面;
钝化保护层,覆盖于所述源极、漏极、第一高阻氮化镓层,第二高阻氮化镓层、栅极所形成的表面,且所述源极、漏极、栅极的上表面有部分裸露。
2.如权利要求1所述的HEMT器件,其特征在于:所述衬底的材料为碳化硅、蓝宝石、硅片中的任意一种。
3.如权利要求1所述的HEMT器件,其特征在于:所述第一保护层和第二保护层的材料为Al2O。
4.如权利要求1所述的HEMT器件,其特征在于:所述钝化保护层的材料为SiN。
5.如权利要求1所述的HEMT器件,其特征在于:
所述AlGaN层的厚度为12nm;
所述第一保护层、AlN层、第二保护层的厚度为2nm:
所述第一高阻氮化镓层,第二高阻氮化镓层、p型掺杂GaN层的厚度为70-100nm;
所述钝化保护层的厚度为20nm。
6.如其权利要求1-5任一所述的HEMT器件的制备方法,其特征在于,包括如下步骤:
在衬底一表面生长AlGaN层;
利用光刻胶遮挡住所述AlGaN层的中部,在所述AlGaN层两端采用蒸镀方式制备源极和漏极;
沿衬底一表面向外延伸的方向,在所述AlGaN层上,源极和漏极之间依次生长缓冲层和p型掺杂GaN层;
在所述p型掺杂GaN层中部蒸镀栅极;
在所述p型掺杂GaN层和缓冲层未被栅极覆盖的两侧注入氧离子;
在器件表面生长一层钝化保护层,且在源极、漏极、栅极上表面通过提前遮挡留下部分裸露。
7.如权利要求6所述的HEMT器件的制备方法,其特征在于:所述AlGaN层通过高温MOCVD外延法生长。
8.如权利要求7所述的HEMT器件的制备方法,其特征在于:所述AlGaN层生长采用三甲基镓作为镓源,三甲基铝作为铝源,氨气作为氮源。
9.如权利要求6所述的HEMT器件的制备方法,其特征在于:所述p型掺杂GaN层采用金属有机物化学气相沉积法制备。
10.如权利要求9所述的HEMT器件的制备方法,其特征在于:所述p型掺杂GaN层采用尿素为氮源,液态金属镓为镓源,环戊二烯基镁可以用作p型掺杂剂。
CN201911018210.2A 2019-10-24 2019-10-24 一种hemt器件及其制备方法 Pending CN110931547A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911018210.2A CN110931547A (zh) 2019-10-24 2019-10-24 一种hemt器件及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911018210.2A CN110931547A (zh) 2019-10-24 2019-10-24 一种hemt器件及其制备方法

Publications (1)

Publication Number Publication Date
CN110931547A true CN110931547A (zh) 2020-03-27

Family

ID=69849384

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911018210.2A Pending CN110931547A (zh) 2019-10-24 2019-10-24 一种hemt器件及其制备方法

Country Status (1)

Country Link
CN (1) CN110931547A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022061590A1 (zh) * 2020-09-23 2022-03-31 苏州晶湛半导体有限公司 半导体结构的制作方法
CN117690793A (zh) * 2024-02-02 2024-03-12 深圳天狼芯半导体有限公司 耐压的氮化镓功率器件的结构、芯片及电子设备

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022061590A1 (zh) * 2020-09-23 2022-03-31 苏州晶湛半导体有限公司 半导体结构的制作方法
CN117690793A (zh) * 2024-02-02 2024-03-12 深圳天狼芯半导体有限公司 耐压的氮化镓功率器件的结构、芯片及电子设备
CN117690793B (zh) * 2024-02-02 2024-06-11 深圳天狼芯半导体有限公司 耐压的氮化镓功率器件的结构、芯片及电子设备

Similar Documents

Publication Publication Date Title
US8835988B2 (en) Hybrid monolithic integration
Xing et al. Gallium nitride based transistors
CN108417627B (zh) 一种用于制备GaN基高频微波器件的方法
CN109873034B (zh) 沉积多晶AlN的常关型HEMT功率器件及其制备方法
CN114582972B (zh) 一种gaafet器件及其制备方法
US20230207661A1 (en) Semiconductor Device and Method of Manufacturing the Same
JP2005005657A (ja) 電界効果トランジスタの結晶層構造
CN111739931A (zh) 一种再生长GaN肖特基二极管及其制造方法
CN110931547A (zh) 一种hemt器件及其制备方法
WO2022041674A1 (zh) 低热阻硅基氮化镓微波毫米波器件材料结构及制备方法
CN111063726A (zh) 一种Si基氮化镓器件的外延结构
CN113937155A (zh) 一种组份渐变复合势垒层hemt器件及其制备方法
CN110634747A (zh) 利用MBE再生长p-GaN的单栅结构GaN-JFET器件的方法
CN109300974B (zh) 一种非极性InAlN/GaN高电子迁移率晶体管及制备方法
KR20150000753A (ko) 질화물 반도체 소자 및 그 제조 방법
CN213212169U (zh) 一种半导体器件的外延结构及半导体器件
CN115394833A (zh) 一种基于异质外延衬底的完全垂直型GaN功率二极管的器件结构及其制备方法
CN114497185B (zh) 一种碳掺杂绝缘层的制备方法、hemt器件及其制备方法
WO2022208868A1 (ja) 半導体装置およびその製造方法
CN114883406A (zh) 一种增强型GaN功率器件及其制备方法
JP2004200188A (ja) ヘテロエピタキシャルウエーハおよびその製造方法
JP2007042936A (ja) Iii−v族化合物半導体エピタキシャルウェハ
CN110634943B (zh) 利用MBE再生长的横向结构GaN基JFET器件及其制备方法
CN114497192B (zh) 一种resfet器件及其制备方法
CN114497193B (zh) 一种resfet器件及其制备方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20200327