CN114497185B - 一种碳掺杂绝缘层的制备方法、hemt器件及其制备方法 - Google Patents

一种碳掺杂绝缘层的制备方法、hemt器件及其制备方法 Download PDF

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CN114497185B
CN114497185B CN202111638718.XA CN202111638718A CN114497185B CN 114497185 B CN114497185 B CN 114497185B CN 202111638718 A CN202111638718 A CN 202111638718A CN 114497185 B CN114497185 B CN 114497185B
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刘新科
林峰
李博
黄双武
宋利军
黎晓华
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Red And Blue Microelectronics Shanghai Co ltd
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Abstract

本发明的目的是提供一种碳掺杂绝缘层的制备方法、HEMT器件及其制备方法,与现有技术相比,本发明的碳掺杂绝缘层的制备方法简洁高效,实用。等离子增强的碳离子注入增加了C的活性和均匀性。由于C进入到氮化镓的能级,从而导致形成了一层高阻区域,能够有效阻断器件的漏电,使得制备出来的碳掺杂绝缘层的漏电流大幅度下降,极大的提升了器件性能。本发明的HEMT器件具备高电阻率、高电子迁移率,低漏电流。比传统器件具有良好的电流密度和低泄漏电流,更高的器件击穿电压,具有良好导热性使器件能在较高温条件下工作。而且通过自支撑衬底材料,解决了现有的外延层晶格失配大,缺陷密度大的问题,改善了界面性能,进一步的提升了HEMT器件的性能,良品率。

Description

一种碳掺杂绝缘层的制备方法、HEMT器件及其制备方法
技术领域
本发明属于半导体技术中的器件制造领域,具体的涉及一种HEMT器件及其制备方法。
背景技术
GaN基材料具有禁带宽度大、击穿场强高、极化系数高、电子迁移率和电子饱和漂移速度高等一系列材料性能优势,是制备新一代高性能电力电子器件的优选材料,具有重要的应用前景。GaN基材料对于光电子器件和微电子器件都有着极大的吸引力。GaN基材料具有禁带宽、击穿电压高、电子饱和漂移速度高以及热稳定性好等特点,而且同AlGaN合金材料能构成理想的异质结,其异质界面上大的导带偏移以及GaN基材料自身高的压电极化和自发极化强度可产生高密度的二维电子气,电子气密度比AlGaAs/GaAs异质结高约一个数量级,因而适于制作高温、高频、大功率电子器件。
目前,AlGaN/GaN异质结HEMT器件由于其电子饱和速度高、击穿场强高、截止频率高、饱和电流高等特点,十分适合高频高功率的工作场合,但面临着两个问题:散热性能不佳与饱和电子速率受限。目前最广泛应用的生长GaN材料的衬底是蓝宝石衬底,具有成本低、技术成熟、稳定性好、机械强度高等优点。
现阶段,由于异质结界面处的二维电子气存在,在实际应用中需要相对复杂的栅驱动电路,以及不满足失效安全要求。因此,在GaN基功率电子器件应用中,增强型GaN基HEMT成为了重要的技术目标。
由于GaN与AlGaN异质结界面处会形成二维电子气,二维电子气中具有极高的载流子浓度以及载流子迁移率,因此是制备HEMT器件的理想材料。现有技术的衬底都是基于硅,蓝宝石,碳化硅材料制备的,但是这些材料在作为基底时存在很多问题,其中异质外延可以降低器件成本,但由于会出现很大的晶格失配与热失配,直接在这些材料上面生长氮化镓时,很容易因为应力集中导致器件开裂,半绝缘的绝缘能力强弱会影响器件的漏电,同时由于氮化镓器件更多的应用在高温,高频环境对材料结构提出来更高的要求。严重影响商业化,另外不同衬底上面外延时,会发生很大的晶格失配和热失配。研究的主流是铁掺半绝缘衬底的HEMT材料的制备,但这种材料的工艺复杂,且铁掺的导热率很难提高,生产成本昂贵,不利于大规模生产。
因此合理的设计一种HEMT器件以及配套的可实施的制备方法来克服现有技术的不足是十分有必要的。
发明内容
本发明的目的是提供一种HEMT器件,以解决现有的HEMT器件散热性能不好,价格昂贵,不能在较高温条件下工作、外延层晶格失配大,缺陷密度大的技术问题。
本发明的另一目的是提供一种碳掺杂绝缘层的制备方法已解决现有的碳掺杂绝缘层漏电流较大的技术问题
本发明又一目的是提供一种HEMT器件的制备方法,以解决现有的HEMT器件的制备方法工艺复杂,且制备出来的器件散热性能差,界面性能不佳的技术问题。
为了实现上述发明目的,本发明的一方面,提供了一种HEMT器件,包括:
衬底;
GaN缓冲层,所述缓冲层结合于所述衬底的一表面;
碳掺杂绝缘层,所述碳掺杂绝缘层结合于所述GaN缓冲层离所述衬底的表面;
N型GaN外延层,所述N型GaN外延层结合于所述碳掺杂绝缘层背离所述缓冲层的表面;
AlGaN层,所述AlGaN层底面结合于所述N型GaN外延层背离所述碳掺杂绝缘层的表面,所述AlGaN层为两边薄中间厚的阶梯形;
源极和漏极,分别欧姆接触设置于所述AlGaN层的两边薄层上;
P型GaN层,层叠结合于所述AlGaN层背离所述GaN外延层的表面的中间厚层上;
栅极,层叠结合于所述P型GaN层背离所述AlGaN层的表面。
优选地,所述衬底的材料为碳化硅、蓝宝石、硅片中的任意一种。
优选地,所述衬底层厚度为400μm;
所述GaN缓冲层的厚度为2μm;
所述碳掺杂绝缘层的厚度为1-100nm;
所述N型GaN外延层的厚度为10μm;
所述AlGaN层的厚度为100nm;
所述P型GaN层的厚度为500nm。
进一步优选地,所述碳掺杂绝缘层的厚度为2-50nm。
优选地,还包括覆盖于所述HEMT器件表面的钝化层。
进一步优选地,所述钝化层的材料为SiO2、Al2O3、AlN中的至少一种,所述钝化层的厚度为从50nm-100nm。
本发明另一方面提供了一种碳掺杂绝缘层的制备方法,包括如下步骤:
氮气携带碳源使用电感耦合等离子体对待掺杂层表面进行等离子体处理。
优选地,所述等离子体处理的碳源等离子体处理的功率为5-20W,氮气流量为20-80sccm,时间为1-30min。
优选地,所述碳源为甲烷,硅烷中的任意一种。
本发明又一方面提供了所述的HEMT器件的制备方法,包括如下步骤:
在衬底一表面生长非掺杂的GaN缓冲层;
用所述的碳掺杂绝缘层的制备方法在非掺杂的GaN缓冲层背离衬底的表面上上进行等离子体处理,制备碳掺杂绝缘层;
沿衬底一表面向外延伸的方向,在所述碳掺杂绝缘层上依次生长N型GaN外延层、AlGa N层和p型掺杂GaN层;
刻蚀去掉p型掺杂GaN层的两端,以及AlGa N层两端的部分厚度形成;
在所述AlGa N层两端薄层上镀膜形成源极和漏极;
在所述p型掺杂GaN层镀膜形成栅极。
与现有技术相比,本发明的HEMT器件具备高电阻率、高电子迁移率,低漏电流。比传统器件具有良好的电流密度和低泄漏电流,更高的器件击穿电压,具有良好导热性使器件能在较高温条件下工作。而且通过自支撑衬底材料,解决了现有的外延层晶格失配大,缺陷密度大的问题,改善了界面性能,进一步的提升了HEMT器件的性能,良品率。
本发明的碳掺杂绝缘层的制备方法简洁高效,实用。等离子增强的碳离子注入增加了C的活性和均匀性。等离子增强处理后,由于C进入到氮化镓的能级,从而导致形成了一层高阻区域,能够有效阻断器件的漏电,使得制备出来的碳掺杂绝缘层的漏电流大幅度下降,极大的提升了器件性能。
本发明的HEMT器件的制备方法采用支撑衬底材料作为衬底,一方面简化了生长工艺,自源性的衬底还能明显改善界面性能。同时由于生长工艺简化,加上界面性能的改善,能在提升器件性能的同时大大提升良品率。
附图说明
图1为本发明实施例所述HEMT器件的结构示意图;
图2为为本发明实施例所述碳掺杂绝缘层输出特性曲线对比图。
具体实施方式
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白,以下结合实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
本发明实施例中,对下文名词作出如下说明。
HEMT器件:High Electron Mobility Transistor,高电子迁移率晶体管。
MOCVD法:MOCVD是以Ⅲ族、Ⅱ族元素的有机化合物和V、Ⅵ族元素的氢化物等作为晶体生长源材料,以热分解反应方式在衬底上进行气相外延,生长各种Ⅲ-V主族、Ⅱ-Ⅵ副族化合物半导体以及它们的多元固溶体的薄层单晶材料。
一方面本发明实施例提供了一种HEMT器件,如图1所示包括:
衬底1;在优选实施例中,所述衬底1的材料为碳化硅、蓝宝石、硅片中的任意一种。这些都是常用的衬底,制备工艺成熟,性能很好;目前最广泛应用的生长GaN材料的衬底是蓝宝石衬底,具有成本低、技术成熟、稳定性好、机械强度高等优点。在一实施例中所述衬底1的厚度为400μm。
GaN缓冲层2,所述缓冲层结合于所述衬底的一表面;在一实施例中所述GaN缓冲层2的厚度为2μm。
碳掺杂绝缘层3,所述碳掺杂绝缘层结合于所述GaN缓冲层2背离所述衬底的表面;在一优选实施例中,所述碳掺杂绝缘层的厚度为1-100nm;在更进一步的优选实施例中所述所述碳掺杂绝缘层的厚度为2-50nm。
N型GaN外延层4,所述N型GaN外延层结合4与所述碳掺杂绝缘层3背离所述缓冲层的表面;在一优选实施例中,所述N型GaN外延层4的厚度为10μm,载流子浓度约为8x1015cm-3;
AlGaN层5,所述AlGaN层5底面结合于所述N型GaN外延层4背离所述碳掺杂绝缘层3的表面,所述AlGaN层5为两边薄中间厚的阶梯形;在一优选实施例中,所述AlGaN层5的厚度为100nm;在一优选实施例中,所述AlGaN层5Al组分大于0,小于0.5。
源极7和漏极8,分别欧姆接触设置于所述AlGaN层5的两边薄层上;
P型GaN层6,层叠结合于所述AlGaN层5背离所述N型GaN外延层4的表面的中间厚层上;在一优选实施例中,所述P型GaN层6的厚度为500nm,载流子浓度约为2x1020cm-3。
栅极9,层叠结合于所述P型GaN层6背离所述AlGaN层的表面。
在一优选实施例中,还包括覆盖于所述HEMT器件表面的钝化层;在进一步优选实施例中,所述钝化层的材料为SiO2、Al2O3、AlN中的至少一种,所述钝化层的厚度为从50nm-100nm。
本发明实施例另一方面提供了一种碳掺杂绝缘层的制备方法,包括如下步骤:
氮气携带碳源使用电感耦合等离子体对待掺杂层表面进行等离子体处理。
在一优选实施例中,所述等离子体处理的碳源等离子体处理的功率为5-20W,氮气流量为20-80sccm,时间为1-30min。进一步优选地实施例中所述等离子体处理的碳源等离子体处理的功率为8-15W,氮气流量为30-60sccm,时间为1-30min。在一优选实施例中,所述碳源为甲烷,硅烷中的任意一种。等离子增强的碳离子注入增加了C的活性和均匀性,同时为后面MOCVD生长GaN提供缓冲层,碳是另一种较好的半绝缘氮化镓掺杂剂,因为碳在氮化镓中的活化能分别在1eV和0.6eV时大于铁在氮化氮化镓中的活化能,因此,碳掺杂的氮化镓比铁掺杂制备半绝缘氮化镓具有更广阔的应用前景。更具体的在一实施例中,如图2所示通过等离子处理后,在从-10V到0V的过程中,我们发现反向漏电流下降了接近两个数量级,同时器件的开关比也得到了有效的提升,反应出等离子增强扩散处理对器件性能的效果。原因是等离子增强处理后,由于C进入到氮化镓的能级,从而导致形成了一层高阻区域,能够有效阻断器件的漏电。
本发明又一方面提供了所述的HEMT器件的制备方法,其特征在于包括如下步骤:
S01:在衬底一表面生长非掺杂的GaN缓冲层;
S02:用所述的碳掺杂绝缘层的制备方法在非掺杂的GaN缓冲层背离衬底的表面上上进行等离子体处理,制备碳掺杂绝缘层;
S03:沿衬底一表面向外延伸的方向,在所述碳掺杂绝缘层上依次生长N型GaN外延层、AlGa N层和p型掺杂GaN层;
S04:刻蚀去掉p型掺杂GaN层的两端,以及AlGa N层两端的部分厚度形成;
S05:在所述AlGaN层两端薄层上镀膜形成源极和漏极;
S06:在所述p型掺杂GaN层镀膜形成栅极。
具体的在步骤S01之前还包括对衬底的打磨清洗,一般通过化学清洗去掉表面杂质。
具体的在步骤S01中所述非掺杂的GaN缓冲层生长方式为有机化学气相沉积(MOCVD)法。采用高温MOCVD外延的方法可以降低缺陷密度,提高材料质量。
具体的在在步骤S02中漏电流下降幅度很大,同时器件的开关比也得到了有效的提升,反应出等离子增强扩散处理对器件性能的效果。原因是等离子增强处理后,由于C进入到氮化镓的能级,从而导致形成了一层高阻区域,能够有效阻断器件的漏电。
具体的在步骤S03中所述N型GaN外延层通过有机化学气相沉积(MOCVD)法生长;所述N型GaN外延层和p型掺杂GaN层为外延生长法;所述p型掺杂GaN层可以使用二茂镁作为p型掺杂剂的供体,以在GaN材料界面处耗尽二维电子气。
具体的在步骤S04中刻蚀的方法包括光刻,ICP刻蚀法中的任意一种。
具体的在步骤S05中所述所述源极和漏极的制备方法是利用光刻技术,利用光刻胶遮挡中部薄膜部分及顶部电极,然后通过真空蒸发或者电子束蒸发制备欧姆接触金属电极,此时金属为Ti(15nm)/Al(150-200nm)/Ti(15nm)
/Au(150-200nm)形成欧姆结构,最后用退火系统在氮气气氛中875℃退火35s,制作出源极和漏极。
具体的在步骤S06中,利用套刻方法,在P-GaN上镀膜,制备栅极。
本发明实施例利用等离子体处理制备碳掺杂绝缘层使得器件的漏电流下降1到两个数量级,且等离子增强的碳离子注入增加了C的活性和均匀性。另外,本发明实施例采用自支撑氮化镓衬底,这使得同质外延的器件材料缺陷低,质量高,有利于增大器件的输出电流。最后通过层结构的生长条件的优选,进一步提升了制备效率,并提升了所制备的器件的性能。1、工艺更简单,实用性更强。生产成本低。因此,碳掺杂的氮化镓比铁掺杂制备半绝缘氮化镓具有更广阔的应用前景。

Claims (10)

1.一种HEMT器件,其特征在于,包括:
衬底;
GaN缓冲层,所述缓冲层结合于所述衬底的一表面;
碳掺杂绝缘层,厚度为1-100nm,所述碳掺杂绝缘层结合于所述GaN缓冲层离所述衬底的表面;所述碳掺杂绝缘层采用氮气携带碳源使用电感耦合等离子体对所述GaN缓冲层表面进行等离子体处理的方式制成;
N型GaN外延层,所述N型GaN外延层结合于所述碳掺杂绝缘层背离所述缓冲层的表面;
AlGaN层,所述AlGaN层底面结合于所述N型GaN外延层背离所述碳掺杂绝缘层的表面,所述AlGaN层为两边薄中间厚的阶梯形;
源极和漏极,分别欧姆接触设置于所述AlGaN层的两边薄层上;
P型GaN层,层叠结合于所述AlGaN层背离所述GaN外延层的表面的中间厚层上;
栅极,层叠结合于所述P型GaN层背离所述AlGaN层的表面。
2.如权利要求1所述的HEMT器件,其特征在于:所述衬底的材料为碳化硅、蓝宝石、硅中的任意一种。
3.如权利要求1所述的HEMT器件,其特征在于:所述衬底层厚度为400μm;
所述缓冲层的厚度为2μm;
所述N型GaN外延层的厚度为10μm;
所述AlGaN层的厚度为100nm;
所述P型GaN层的厚度为500nm。
4.如权利要求3所述的HEMT器件,其特征在于:所述碳掺杂绝缘层的厚度为2-50nm。
5. 如权利要求1所述的HEMT器件,其特征在于:还包括覆盖于所述HEMT器件表面的钝化层。
6.如权利要求5所述的HEMT器件,其特征在于:所述钝化层的材料为
SiO2、Al2O3、AlN中的至少一种,所述钝化层的厚度为从50nm-100nm。
7.一种碳掺杂绝缘层的制备方法,其特征在于,用于如权利要求1-6中任一项所述的HEMT器件中碳掺杂绝缘层的制备,包括如下步骤:
氮气携带碳源使用电感耦合等离子体对待掺杂层表面进行等离子体处理,制备1-100nm厚的碳掺杂绝缘层,所述待掺杂层为GaN缓冲层。
8.如权利要求7所述的碳掺杂绝缘层的制备方法,其特征在于,所述等离子体处理的碳源等离子体处理的功率为5-20W,氮气流量为20-80sccm,时间为1-30min。
9.如权利要求7所述的碳掺杂绝缘层的制备方法,其特征在于,所述碳源为甲烷。
10.如权利要求1-6任一所述的HEMT器件的制备方法,其特征在于包括如下步骤:
在衬底一表面生长非掺杂的GaN缓冲层;
用权利要求7-9所述的碳掺杂绝缘层的制备方法在非掺杂的GaN缓冲层背离衬底的表面上上进行等离子体处理,制备1-100nm厚的碳掺杂绝缘层;
沿衬底一表面向外延伸的方向,在所述碳掺杂绝缘层上依次生长N型GaN外延层、AlGaN层和p型掺杂GaN层;
刻蚀去掉p型掺杂GaN层的两端,以及AlGa N层两端的部分厚度形成;
在所述AlGa N层两端薄层上镀膜形成源极和漏极;
在所述p型掺杂GaN层镀膜形成栅极。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297713A (ja) * 1998-04-14 1999-10-29 Furukawa Electric Co Ltd:The 電界効果トランジスタ
JP2001291714A (ja) * 2000-04-07 2001-10-19 Ulvac Japan Ltd 絶縁膜の形成方法
US6544867B1 (en) * 1999-06-11 2003-04-08 National Research Council Of Canada Molecular beam epitaxy (MBE) growth of semi-insulating C-doped GaN
CN104752162A (zh) * 2013-12-31 2015-07-01 江西省昌大光电科技有限公司 一种半绝缘GaN薄膜及其制备方法
CN108122776A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 Finfef器件及其形成方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297713A (ja) * 1998-04-14 1999-10-29 Furukawa Electric Co Ltd:The 電界効果トランジスタ
US6544867B1 (en) * 1999-06-11 2003-04-08 National Research Council Of Canada Molecular beam epitaxy (MBE) growth of semi-insulating C-doped GaN
JP2001291714A (ja) * 2000-04-07 2001-10-19 Ulvac Japan Ltd 絶縁膜の形成方法
CN104752162A (zh) * 2013-12-31 2015-07-01 江西省昌大光电科技有限公司 一种半绝缘GaN薄膜及其制备方法
CN108122776A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 Finfef器件及其形成方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Normally-off p-GaN/AlGaN/GaN high electron mobility transistors using hydrogen plasma treatment;Ronghui Hao et al;《Applied Physics Letters》;20161014;第1页第2段-第4页第2段,附图1 *

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