WO2020228018A1 - 一种半导体结构的制备方法 - Google Patents

一种半导体结构的制备方法 Download PDF

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WO2020228018A1
WO2020228018A1 PCT/CN2019/087262 CN2019087262W WO2020228018A1 WO 2020228018 A1 WO2020228018 A1 WO 2020228018A1 CN 2019087262 W CN2019087262 W CN 2019087262W WO 2020228018 A1 WO2020228018 A1 WO 2020228018A1
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type semiconductor
layer
semiconductor layer
semiconductor structure
manufacturing
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PCT/CN2019/087262
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English (en)
French (fr)
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程凯
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苏州晶湛半导体有限公司
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Priority to CN201980096456.3A priority Critical patent/CN113826212B/zh
Priority to PCT/CN2019/087262 priority patent/WO2020228018A1/zh
Publication of WO2020228018A1 publication Critical patent/WO2020228018A1/zh
Priority to US17/526,321 priority patent/US20220102530A1/en

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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • H01L21/3006—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma of AIIIBV compounds
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
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Definitions

  • This application relates to the field of microelectronics technology, in particular to a method for preparing a semiconductor structure.
  • High Electron Mobility Transistor is a kind of heterojunction field effect transistor.
  • AlGaN/GaN heterostructure due to the strong two-dimensional electron gas in AlGaN/GaN heterostructure, Generally, AlGaN/GaN HEMTs are depletion-mode devices, making enhancement-mode devices difficult to implement.
  • the application of depletion-type devices has certain limitations. For example, in the application of power switching devices, enhanced (normally-off) switching devices are required.
  • Enhanced GaN switching devices are mainly used in high-frequency devices, power switching devices and digital circuits, and its research has very important significance.
  • the p-type semiconductor material is set in the gate area, and it is necessary to selectively etch the p-type semiconductor in other areas other than the gate.
  • the precise process control of the etching thickness in the epitaxial direction is very difficult, and it is very easy to over-etch the p-type semiconductor.
  • the semiconductor material etched below it, and the defects caused by the etching will cause serious current collapse effects, which will also affect the stability and reliability of the device.
  • the present invention provides a method for preparing a semiconductor structure to avoid current collapse effects and improve the stability and reliability of the device, including:
  • the channel layer, the barrier layer and the p-type semiconductor layer are sequentially prepared on the substrate;
  • the dielectric layer is removed, and a gate is prepared above the active region of the p-type semiconductor layer.
  • the method for preparing the semiconductor structure further includes: preparing a source electrode and a drain electrode on both sides of the gate region, wherein the source electrode and the drain electrode penetrate the n-type semiconductor layer and the p-type semiconductor layer.
  • the present invention does not limit the preparation sequence of the source, drain and gate.
  • the preparation method of the semiconductor structure provided by the present invention does not need to etch the n-type semiconductor layer and the p-type semiconductor layer, and avoids problems such as uncontrollable etching depth and surface damage of etching; Reduce gate leakage, maintain low resistance in the channel area, suppress current collapse, and improve device reliability and stability.
  • FIGS. 1-6 are respectively an exploded schematic diagram of the semiconductor structure provided by an embodiment of the application during the manufacturing process.
  • An embodiment of the present application provides a method for manufacturing a semiconductor structure. The specific steps are as follows.
  • Step 1 As shown in FIG. 1a, a channel layer 21, a barrier layer 22 and a p-type semiconductor layer 23 are sequentially prepared on the substrate 1.
  • the substrate 1 is preferably selected from sapphire, diamond, silicon carbide, silicon, lithium niobate, silicon on insulator (SOI), gallium nitride, or aluminum nitride.
  • the channel layer 21 and the barrier layer 22 may be semiconductor materials that can form two-dimensional electron gas.
  • the channel layer 21 and the barrier layer 22 may be, for example, a GaN-based material.
  • the so-called GaN-based material is a compound containing at least Ga atoms and N atoms.
  • the channel layer 21 may be GaN
  • the barrier layer 22 may be AlGaN
  • the channel layer 21 and the barrier layer 22 form a heterostructure to form a two-dimensional electron gas.
  • the p-type semiconductor layer 23 includes a GaN-based material, such as doping GaN with p-type impurities, such as Mg.
  • a nucleation layer 31 and a buffer layer 32 can also be sequentially grown on the substrate 1.
  • the nucleation layer 31 can reduce dislocation density and defect density, and improve crystal quality.
  • the nucleation layer 31 may be one or more of AlN, AlGaN and GaN.
  • the buffer layer 322 can buffer the stress in the epitaxial structure above the substrate and prevent the epitaxial structure from cracking.
  • the buffer layer 32 may include one or more of GaN, AlGaN, and AlInGaN.
  • the channel layer 21, the barrier layer 22, and the p-type semiconductor layer 23 can be grown in situ, or can be grown by atomic layer deposition (ALD, Atomic Layer Deposition), or Chemical Vapor Deposition (CVD, Chemical Vapor Deposition), or molecular Beam epitaxy (MBE, Molecular Beam Epitaxy), or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or metal organic compound chemical vapor deposition It is made by deposition (MOCVD, Metal-Organic Chemical Vapor Deposition) or a combination thereof.
  • ALD Atomic Layer Deposition
  • CVD Chemical Vapor Deposition
  • MBE molecular Beam epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • metal organic compound chemical vapor deposition It is made by deposition (MOCVD, Metal-Organic Chemical
  • Step: 2 As shown in FIG. 2, a dielectric layer 24 is prepared in the gate region above the p-type semiconductor layer 23.
  • a dielectric layer is formed on the p-type semiconductor layer 23, and the dielectric layer in the region other than the gate region above the p-type semiconductor 23 is etched so that the dielectric layer 24 is formed only on the gate region above the p-type semiconductor 23.
  • the layer 24 covers the p-type semiconductor layer 23 under the gate region.
  • Step 3 As shown in FIG. 3, an n-type semiconductor layer 25 is prepared in a region other than the gate region above the p-type semiconductor 23.
  • the n-type semiconductor layer 25 is selectively grown, and the n-type semiconductor layer 25 is formed only in regions other than the gate region above the p-type semiconductor 23, and the n-type semiconductor layer 25 covers the p-type semiconductor layer 23 in regions other than the gate region.
  • the n-type semiconductor layer includes an n-type GaN-based semiconductor layer, for example, n-type impurities are doped in GaN to form n-GaN.
  • Step 4 As shown in FIG. 4, the p-type impurities in the p-type semiconductor covered by the dielectric layer 24 are activated to form an active region 231.
  • the epitaxial structure may be annealed to form the active region.
  • the annealing includes performing in a hydrogen-free environment to selectively activate p-type impurities in the p-type semiconductor layer 23 covered by the dielectric layer 24 to form the active region 231 ; And the p-type semiconductor layer 23 covered by the n-type semiconductor layer 25, due to the blocking of the n-type semiconductor layer 25, H atoms cannot overflow, and the p-type impurities in the p-type semiconductor layer cannot be activated, forming an inactive region 232.
  • the active region 231 may be larger than the dielectric layer 24 covering the p-type semiconductor layer 23, may be smaller than the dielectric layer 24 covering the p-type semiconductor layer 23, or may be equal to the dielectric layer 24 covering the p-type semiconductor layer 23, In this case, the size of the activation area 231 is not limited.
  • the specific method for forming the active region 231 is that in a hydrogen-free annealing environment, hydrogen components in the p-type semiconductor layer 23 overflow through the dielectric layer 24 to activate the p-type impurities in the p-type semiconductor layer 23.
  • the p-type semiconductor layer 23 covered by the n-type semiconductor layer 25 is blocked by the n-type semiconductor layer 25, and H atoms cannot escape in the annealing environment and bond with the p-type impurities in the p-type semiconductor layer (such as Mg-H) ,
  • the p-type impurities in the p-type semiconductor layer cannot be activated, forming an inactive region 232.
  • the material type of the dielectric layer 24 only needs to meet the following requirements: in the process of activating the p-type impurities in the p-type semiconductor, the overflow of H atoms is ensured, specifically, the active region is formed After 231, the H content in the dielectric layer 24 may be, for example, not more than 10%.
  • the dielectric layer may be, for example, at least one of SiO 2 and Al 2 O 3 .
  • Step 5 As shown in FIG. 5, the dielectric layer 24 is removed, and a gate 43 is prepared above the active region 231 of the p-type semiconductor layer 23.
  • the dielectric layer 24 can be removed by wet etching, and a gate material is deposited on the position where the dielectric layer 24 is removed, that is, on the active region 231 to form the gate 43.
  • the preparation method of the semiconductor structure further includes step 6: as shown in FIG. 6, a source and a drain are prepared in the source region and the drain region, and the source and the drain penetrate the n-type semiconductor layer, the p Type semiconductor layer.
  • grooves can be etched on both sides of the gate, and the grooves penetrate through the inactive regions 232 of the n-type semiconductor layer 25 and the p-type semiconductor layer 23 and stop at the barrier layer 22; The source and drain form ohmic contacts.
  • the etching method of the groove may be dry etching.
  • step 5 and step 6 can be exchanged, that is, the order of preparation of the source, gate, and drain is not limited, as long as the gate, gate, and drain are formed on the epitaxial structure. The source and drain are sufficient.
  • the preparation method of the semiconductor structure provided by the present invention does not need to etch the n-type semiconductor layer and the p-type semiconductor layer, and avoids problems such as uncontrollable etching depth and surface damage of etching; Reduce gate leakage, maintain low resistance in the channel area, suppress current collapse, and improve device reliability and stability.

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Abstract

本申请公开了一种半导体结构的制备方法，通过选择性外延生长的方法，不需要对n型半导体层以及p型半导体层刻蚀，避免了刻蚀深度无法控制、刻蚀表面损伤等问题；有效减少栅极漏电，保持沟道区域低电阻，抑制电流崩塌，提高器件可靠性、稳定性。

Description

一种半导体结构的制备方法 技术领域
本申请涉及微电子技术领域，具体涉及一种半导体结构的制备方法。
背景技术
高电子迁移率晶体管(HEMT，High Electron Mobility Transistor)是一种异质结场效应晶体管，以AlGaN/GaN异质结构为例，由于AlGaN/GaN异质结构中存在较强的二维电子气，通常AlGaN/GaN HEMT是耗尽型器件，使得增强型器件不易实现。而在许多地方耗尽型器件的应用又具有一定的局限性，比如在功率开关器件的应用中，就需要增强型(常关型)开关器件。增强型氮化镓开关器件主要用于高频器件、功率开关器件和数字电路等，它的研究具有十分重要的意义。
实现增强型氮化镓开关器件，需要找到合适的方法来降低零栅压时栅极下方的沟道载流子浓度，例如通过在栅极区域设置p型半导体材料。但是发明人发现该方法至少有如下缺陷：
栅极区域设置p型半导体材料，需要选择性刻蚀栅极以外的其他区域的p型半导体，而在外延方向上刻蚀厚度的精确工艺控制是非常难的，非常容易对p型半导体过刻而刻蚀到其下方的半导体材料，而且刻蚀中带来的缺陷，会引起严重的电流崩塌效应，同样会影响到器件的稳定性和可靠性。
发明内容
有鉴于此，本发明提供一种半导体结构的制备方法，避免电流崩塌效应，提高器件的稳定性和可靠性，包括：
在衬底上依次制备沟道层、势垒层及p型半导体层；
在所述p型半导体层上方的栅极区域制备介质层；以及
在所述p型半导体上方的栅极区域以外的区域制备n型半导体层；
激活介质层覆盖的p型半导体中的p型杂质，形成激活区域；
去除介质层，在p型半导体层的激活区域的上方制备栅极。
所述的半导体结构的制备方法还包括：在所述栅极区域两侧制备源极、漏极，其中所述源极、漏极贯穿所述n型半导体层、p型半导体层。
可以理解的是，本发明对所述源极、漏极与栅极的制备顺序不限定。
本发明提供的半导体结构的制备方法，通过选择性外延生长的方法，不需要对n型半导体层以及p型半导体层进行刻蚀，避免了刻蚀深度无法控制、刻蚀表面损伤等问题；有效减少栅极漏电，保持沟道区域低电阻，抑制电流崩塌，提高器件可靠性、稳定性。
附图简要说明
图1-6分别为本申请一实施例提供的半导体结构在制备过程中的分解示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本申请进行详细描述。但这些实施方式并不限制本申请，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本申请的保护范围内。
此外，在不同的实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本申请，不代表所讨论的不同实施例和/或结构之间具有任何关联性。
本申请的一实施例中提供了一种半导体结构的制备方法，具体步骤如下。
步骤1：如图1a所示，在衬底1上依次制备沟道层21、势垒层22以及p型半导体层23。
衬底1优选自蓝宝石、金刚石、碳化硅、硅、铌酸锂、绝缘衬底硅(SOI)、氮化镓或氮化铝。
沟道层21和势垒层22为可形成二维电子气的半导体材料即可。沟道层 21和势垒层22可例如为GaN基材料，所谓GaN基材料即至少包含Ga原子和N原子的化合物。例如，沟道层21可采用GaN，势垒层22可采用AlGaN，沟道层21和势垒层22构成异质结构以形成二维电子气。
所述p型半导体层23包括GaN基材料，如在GaN中掺杂p型杂质，如Mg。
在本申请一实施例中，如图1b所示，在生长沟道层21之前，还可在衬底1上依次生长成核层31和缓冲层32。以GaN基半导体结构为例，成核层31可降低位错密度和缺陷密度，提升晶体质量。该成核层31可为AlN、AlGaN和GaN中的一种或多种。缓冲层322可缓冲衬底上方外延结构中的应力，避免外延结构开裂。该缓冲层32可包括GaN、AlGaN、AlInGaN中的一种或多种。
沟道层21、势垒层22以及p型半导体层23可以通过原位生长，也可以是通过原子层沉积(ALD,Atomic layer deposition)、或化学气相沉积(CVD，Chemical Vapor Deposition)、或分子束外延生长(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式制得。应该理解，这里描述形成沟道层21、势垒层22，本申请可以通过本领域的技术人员公知的任何方法形成沟道层、势垒层及半导体层。
步骤:2：如图2所示，在p型半导体层23上方的栅极区域制备介质层24。
在所述p型半导体层23上形成介质层，刻蚀p型半导体23上方的栅极区域以外区域的介质层，使得只在p型半导体23上方的栅极区域形成介质层24，所述介质层24覆盖栅极区域下方的p型半导体层23。
步骤3：如图3所示，在所述p型半导体23上方的栅极区域以外的区域制备n型半导体层25。
选择性生长n型半导体层25，只在p型半导体23上方的栅极区域以外的区域形成n型半导体层25，所述n型半导体层25覆盖栅极区域以外区域的p 型半导体层23。
进一步的，所述n型半导体层包括n型GaN基半导体层，如在GaN中掺杂n型杂质，形成n-GaN。
步骤4：如图4所示，激活介质层24覆盖的p型半导体中的p型杂质，形成激活区域231。
本实施例中，可以选择对外延结构进行退火来形成激活区域，所述退火包括在无氢环境进行，选择性激活介质层24覆盖的p型半导体层23中的p型杂质，形成激活区域231；而被n型半导体层25覆盖的p型半导体层23，由于n型半导体层25的阻挡，H原子无法溢出，p型半导体层中的p型杂质无法被激活，形成非激活区域232。可以理解的是，所述激活区域231可以大于覆盖p型半导体层23的介质层24，可以小于覆盖p型半导体层23的介质层24，也可以等于覆盖p型半导体层23的介质层24，本案中对所述激活区域231的大小不做限制。
本实施例中，形成激活区域231的具体方式为在无氢退火环境中，p型半导体层23中氢成分通过介质层24溢出，激活了p型半导体层23中的p型杂质。而被n型半导体层25覆盖的p型半导体层23，由于n型半导体层25的阻挡，H原子在退火环境无法溢出，与p型半导体层中的p型杂质键合(比如Mg-H)，p型半导体层中的p型杂质无法激活，形成非激活区域232。
本申请对于介质层的材料种类不做特别限制，所述介质层24的材料种类只需满足：在激活p型半导体中的p型杂质过程中，保证H原子的溢出，具体地，形成激活区域231之后，所述介质层24中的H含量可例如不大于10％。所述介质层可例如为SiO 2、Al 2O 3中的至少一种。
步骤5：如图5所示，去除介质层24，在p型半导体层23的激活区域231的上方制备栅极43。
所述介质层24可通过湿法刻蚀来去除，在介质层24去除的位置，即激活区域231上方沉积栅极材料形成栅极43。
进一步的，所述半导体结构的制备方法还包括步骤6：如图6所示，在源极区域和漏极区域制备源极、漏极，所述源极、漏极贯穿n型半导体层、p型半 导体层。
具体的，可在栅极两侧刻蚀凹槽，所述凹槽贯穿n型半导体层25、p型半导体层23的非激活区域232，停止于势垒层22；在凹槽中沉积金属制备源极、漏极，形成欧姆接触。
进一步的，所述凹槽的刻蚀方法可为干法刻蚀。
可以理解的是，所述步骤5与所述步骤6的顺序是可以调换的，即所述源极、栅极、漏极制备的先后顺序是不限定的，只要在外延结构上形成栅极、源极、漏极即可。
本发明提供的半导体结构的制备方法，通过选择性外延生长的方法，不需要对n型半导体层以及p型半导体层进行刻蚀，避免了刻蚀深度无法控制、刻蚀表面损伤等问题；有效减少栅极漏电，保持沟道区域低电阻，抑制电流崩塌，提高器件可靠性、稳定性。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本申请的可行性实施方式的具体说明，它们并非用以限制本申请的保护范围，凡未脱离本申请技艺精神所作的等效实施方式或变更均应包含在本申请的保护范围之内。

Claims (9)

  1. 一种半导体结构的制备方法，其特征在于，包括以下步骤：
    在衬底上依次制备沟道层、势垒层及p型半导体层；
    在所述p型半导体层上方的栅极区域制备介质层；以及
    在所述p型半导体上方的栅极区域以外的区域制备n型半导体层；
    激活介质层覆盖的p型半导体中的p型杂质，形成激活区域。
  2. 根据权利要求1所述的半导体结构的制备方法，其特征在于，还包括：去除介质层，在p型半导体层的激活区域的上方制备栅极。
  3. 根据权利要求2所述的半导体结构的制备方法，其特征在于：所述介质层通过湿法刻蚀的方法来去除。
  4. 根据权利要求1所述的半导体结构的制备方法，其特征在于，还包括：在源极区域和漏极区域制备源极、漏极，其中所述源极、漏极贯穿n型半导体层、p型半导体层。
  5. 根据权利要求1所述的半导体结构的制备方法，其特征在于，还包括：所述形成激活区域的方法包括对外延结构进行退火来。
  6. 根据权利要求5所述的半导体结构的制备方法，其特征在于，还包括：所述退火包括在无氢环境进行。
  7. 根据权利要求1所述的半导体结构的制备方法，其特征在于：所述介质层包括SiO 2、Al 2O 3中的至少一种。
  8. 根据权利要求1所述的半导体结构的制备方法，其特征在于：所述p型半导体层、n型半导体层为GaN基半导体。
  9. 根据权利要求1所述的半导体结构的制备方法，其特征在于：在形成所述 沟道层之前，依次在所述衬底形成成核层、缓冲层。
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