WO2016141762A1 - Iii族氮化物增强型hemt及其制备方法 - Google Patents

Iii族氮化物增强型hemt及其制备方法 Download PDF

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WO2016141762A1
WO2016141762A1 PCT/CN2015/099170 CN2015099170W WO2016141762A1 WO 2016141762 A1 WO2016141762 A1 WO 2016141762A1 CN 2015099170 W CN2015099170 W CN 2015099170W WO 2016141762 A1 WO2016141762 A1 WO 2016141762A1
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semiconductor
layer
nitride
preparing
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French (fr)
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孙钱
周宇
李水明
戴淑君
高宏伟
杨辉
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中国科学院苏州纳米技术与纳米仿生研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • the invention relates to a method for preparing a high electron mobility transistor (HEMT), in particular to a method for preparing a group III nitride enhanced HEMT, and belongs to the technical field of semiconductors.
  • HEMT high electron mobility transistor
  • AGaN/GaN heterojunction-based high electron mobility transistors Compared to conventional silicon-based MOSFETs, AGaN/GaN heterojunction-based high electron mobility transistors (HEMTs) have unique advantages such as low on-resistance, high breakdown voltage, and high switching frequency, enabling them to convert in various types of power.
  • As a core device in the system it has important application prospects in terms of energy saving and consumption reduction. Therefore, it has received great attention from academic and industrial circles.
  • the AlGaN/GaN heterojunction-based HEMTs are depleted (normally open), and this type of device is required for use in circuit-level systems.
  • a special negative polarity power supply circuit is designed to achieve switching control of the device, which greatly increases the complexity and cost of the circuit.
  • depletion devices have drawbacks in terms of fail-safe capabilities and, therefore, cannot be truly commercialized.
  • the conventional technology mainly includes a fluorine ion implantation technology and a recessed gate technology (Recessed Gate Technology), in which a former uses a fluorine-containing plasma (such as CF 4 ) to process a gate region of a device, and injects a negatively charged fluoride ion into the device.
  • the AlGaN barrier layer thereby depleting the two-dimensional electron gas under the gate, has high stability to the stability of the fluoride ion in the barrier layer, and requires a large current and a high voltage due to the HEMT device in the on state.
  • the local high temperature at the channel will cause the thermal movement of fluoride ions, affecting the spatial distribution of fluoride ions, resulting in a threshold voltage shift.
  • the fluoride ion implantation process will inevitably cause damage to the barrier layer, so it must be After the gate preparation is completed, low temperature annealing is performed to recover the damage.
  • the latter mainly uses the dry etching technique (mainly ICP, RIE) to thin the AlGaN barrier layer in the region where the gate is located, thereby depleting the two-dimensional electron gas under the gate.
  • ICP dry etching
  • RIE reactive ion etching
  • a Cascode structure based on a depletion HEMT which is a package integration of a depleted HEMT and an enhanced silicon MOSFET, and indirectly controls the HEMT gate by controlling the conduction of the silicon MOSET. (ground) and the potential difference between the source, thus achieving the "normally closed” HEMT, but it is not really
  • the enhanced HEMT and because of the Cascode structure requirements for integration with silicon MOSFETs, adds additional complexity and cost to the packaging process.
  • the p-type layer is epitaxially grown on the AlGaN barrier layer (unintentionally doped n-type), and selective etching is performed to realize p-type gate fabrication, thereby forming a pn junction and a space charge region.
  • the barrier layer and the channel layer effectively depleting the two-dimensional electron gas at the channel, as shown in FIG. Since the enhanced HEMT only requires electrons under the gate to be depleted, selective etching to prepare the p-type gate is necessary.
  • the p-gate technology requires precise controllable etch depth of the p-type layer in the non-gate region, which greatly increases the difficulty of the p-gate technology and makes the technique repeatable (slices and slices) Between), uniformity (between different areas within the film), stability (between different round processes) is difficult to guarantee, and is not suitable for mass production.
  • the selective etching of the p-type layer inevitably introduces additional surface states and defect states in the non-gate region, which makes the current collapse phenomenon of the device more serious, thereby seriously affecting the reliability of the device.
  • the main object of the present invention is to provide a Group III nitride-enhanced HEMT and a preparation method thereof, thereby overcoming the deficiencies in the prior art.
  • the technical solution adopted by the present invention includes:
  • a method for preparing a Group III nitride-enhanced HEMT comprising:
  • a p-type gate is provided on the p-type layer, and an ohmic contact or a Schottky contact is formed between the p-type gate and the p-type layer.
  • the second semiconductor has a band gap wider than that of the first semiconductor.
  • a high resistance layer is also disposed between the heterostructure and the substrate.
  • the high resistance layer acts to form a good insulation isolation between the active region channel and the substrate, thereby improving the breakdown voltage of the device.
  • the material of the high resistance layer may be selected from GaN, AlGaN, or a combination of both, but is not limited thereto.
  • the step (1) may further include: sequentially forming a nucleation layer, a stress control layer, a high resistance layer, and the heterostructure on the substrate.
  • the nucleation layer functions to grow the epitaxial material on the substrate with high quality.
  • the material of the nucleation layer may be selected from AlN, GaN, or a combination of both, but is not limited thereto.
  • the function of the stress control layer is to offset the stress generated by the lattice mismatch and the thermal expansion coefficient mismatch during the epitaxial growth of the material, thereby effectively suppressing the warpage and crack of the epitaxial wafer.
  • the material of the stress control layer may be selected from a single layer of AlGaN, a double layer or a double layer or more aluminum component, AlGaN, or the like, but is not limited thereto.
  • the heterostructure may further comprise an intervening layer distributed between the first and second semiconductors.
  • the insertion layer functions to obtain better spatial quantum confinement characteristics of the two-dimensional electron gas at the channel and reduce alloy scattering and improve electron mobility.
  • the material of the interposer layer may be selected from a material that forms a higher band difference with the channel layer, such as AlN, AlInN or AlInGaN, but is not limited thereto.
  • the step (3) may include: forming a photoresist layer on the mask layer, and photolithographically processing the p-type gate region of the photoresist layer to expose the mask layer, and then The photoresist layer acts as a mask to etch the gate region of the mask layer to expose the second semiconductor.
  • the etching method may preferably be a dry etching method such as RIE, ICP etching or the like. The wet etching process can also be used for mask layers grown under certain conditions (such as low temperatures, etc.).
  • the preparation method may further comprise:
  • the preparation method may further comprise:
  • the preparation method may further comprise:
  • the extraction electrodes electrically connected to the source and the drain, respectively, are disposed on the device obtained in the step (7).
  • the substrate includes a silicon, sapphire, silicon carbide, aluminum nitride or gallium nitride substrate, but is not limited thereto.
  • the material of the second semiconductor includes AlGaN, AlN, AInN or AlInGaN
  • the material of the first semiconductor includes GaN, but is not limited thereto.
  • the material of the mask layer includes any one or a combination of two or more of amorphous silicon nitride, amorphous silicon oxide, amorphous silicon oxynitride, and amorphous aluminum nitride, but is not limited thereto.
  • the material epitaxial growth process in the preparation method may be selected from the group consisting of MBE (Molecular Beam Epitaxy), MOCVD (Metal Organic Chemical Vapor Deposition), and the like, and is not limited thereto.
  • the deposition process of the mask layer/passivation layer in the preparation method may be selected from the group consisting of PECVD (Plasma Enhanced Chemical Vapor Deposition), MOCVD, LPCVD (Low Pressure Chemical Vapor Deposition). Deposition), ALD (Atom Layer Deposition), PLD (Pulsed Laser Deposition), etc., and are not limited thereto.
  • the material of the p-type layer includes any one or a combination of two or more of p-AlGaN, p-GaN, p-AlGaN, p-AlInN, p-InGaN, and p-AlInGaN, but is not limited thereto. .
  • a Group III nitride enhanced HEMT device prepared by any of the foregoing processes.
  • the active region structure of the HEMT may be not limited to the AlGaN/AlN/GaN heterojunction, but may also be applied to HEMTs having other active region structures, such as AlInN/AlN based on near lattice matching. /GaN, AlInGaN/AlN/GaN heterojunction HEMT, HEMT based on double channel heterojunction, and the like.
  • the process of the invention can effectively solve the reliability problem of the device and realize the enhanced HEMT in the true sense;
  • the process of the present invention adopts the selective epitaxial growth technique to directly solve the problem of the p-type gate in the epitaxial growth layer of the HEMT, thereby omitting the etching of the non-gate region.
  • the process steps of the layer greatly reduce the difficulty of implementing the p-gate technology, ensure the repeatability, uniformity and stability of the process, and are suitable for mass production.
  • the gate-source and gate-drain are avoided.
  • the etching between the regions reduces the possibility of introducing an additional surface state, and the etch mask layer is simultaneously used as a passivation layer, which perfectly protects the surface of the device and can effectively suppress current collapse.
  • FIG. 1 is a schematic diagram of a trench gate technology for fabricating an enhanced HEMT device
  • FIG. 2 is a schematic diagram of a p-type gate technology for fabricating an enhanced HEMT device
  • FIG. 3 is a schematic structural view of an enhanced HEMT device in an exemplary embodiment of the present invention.
  • FIG. 4 is a flow chart showing the fabrication process of an enhanced HEMT device in an exemplary embodiment of the present invention.
  • the conventional p-gate technology adopts a selective etching scheme, and the etching depth of the p-type layer in the non-gate region is required to be accurately controllable, so that it is difficult to implement, etc. defect.
  • the inventor of the present invention has proposed a technical solution of the present invention based on long-term research and a large number of practices, which is a novel p-type gate technology based on epitaxial growth of a selective region, which can directly solve the problem of positioning of a p-type gate in the epitaxial growth process of HEMT, thereby avoiding
  • the process step of etching the p-type layer of the non-gate region is performed, which greatly reduces the implementation difficulty of the p-type gate technology, ensures the repeatability, uniformity and stability of the process, and at the same time effectively suppresses current collapse, thereby Improve device reliability.
  • the following embodiment relates to a HEMT device based on a silicon substrate and an AlGaN/AlN/GaN heterojunction in which p-AlGaN is employed as a p-type layer.
  • the preparation process of the HEMT device may include:
  • S2 growing silicon nitride as a mask layer (passivation layer) by a PECVD process or the like on the HEMT epitaxial structure;
  • the preparation process of the HEMT device includes the following specific steps:
  • the AlGaN barrier layer has an Al composition x of 10% to 30%, a thickness of 10 to 25 nm, an AlN insertion layer of about 1 nm, and a GaN channel layer of 50 to 200 nm, and a complete silicon substrate-based HEMT epitaxial structure. This is shown in S1 in Fig. 4.
  • PECVD grows silicon nitride as a mask layer, and at the same time, silicon nitride acts as a passivation layer, which can effectively suppress the current collapse effect.
  • Growth conditions substrate temperature is 100-350 ° C, reaction chamber pressure is 1700 mtorr, SiH 4 flow is 13-45 sccm, NH 3 flow is 10-90 sccm, N 2 purge flow is 1000 sccm, RF power is 67 W, LF power It is 53W.
  • the thickness of the silicon nitride mask layer is 50 - 300 nm, as shown by S2 in FIG.
  • Lithographic p-type gate region Lithographic conditions: photoresist AZ5214 thickness 1.5 ⁇ m, exposure in hard contact mode 6.5s, JZX3038 development 45s, 110 ° C hard film 5min.
  • the p-type gate region has a size of 3 ⁇ m ⁇ 104 ⁇ m as shown by S3 in Fig. 4 . In this step of the process, lithography of the overprint mark is simultaneously performed.
  • RIE etches the gate region silicon nitride mask layer.
  • Etching conditions the substrate temperature was room temperature, the chamber pressure was 1500 mtorr, the reaction gas SF 6 flow rate was 8 sccm, the reaction gas CHF 3 flow rate was 10 sccm, the carrier gas He flow rate was 150 sccm, and the RF power was 200 W.
  • the silicon nitride mask layer etching of the engraved mark region is simultaneously performed.
  • MOCVD selected region epitaxially grown p-AlGaN. Growth conditions: growth temperature 500 ⁇ 1100 ° C, reaction chamber pressure 55 ⁇ 500 mbar, p-AlGaN magnesium doping concentration range of 1 ⁇ 10 17 ⁇ 5 ⁇ 20 cm -3 , growth thickness of 50 ⁇ 200nm. As shown in S5 in Fig. 4.
  • P-type gate ohmic contact preparation Preparation conditions: metal Pd / Pt / Au, thickness of 30nm / 30nm / 50nm, annealing conditions of 550 ° C, 90s, nitrogen atmosphere. As shown in Figure 4, S6
  • ICP etching is used to perform active region isolation, wherein RIE etches the silicon nitride mask layer (passivation layer) grown in the second step, and ICP etches to the high resistance layer GaN or AlGaN.
  • Etching conditions RIE etching conditions are the same as 4, to ensure that all silicon nitride is etched; ICP etching, substrate temperature is room temperature, chamber pressure is 6mtorr, reaction gas Cl 2 flow is 30sccm, reaction gas BCl 3 flow is 30sccm
  • the RF power is 100W and the ICP power is 300W. As shown in S7 of Figure 4.
  • RIE etching is used to perform source-drain ohmic contact opening.
  • the etching conditions are the same as 4, ensuring that all of the silicon nitride is etched, and the AlGaN barrier layer can be slightly etched ( ⁇ 1 nm).
  • Source and drain ohmic contact preparation Preparation conditions: metal Ti / Al / Ni / Au, thickness of 20nm / 130nm / 50nm / 150nm, annealing conditions of 890 ° C, 30s, nitrogen atmosphere. As shown in S8 in Fig. 4.
  • Lead electrode preparation Preparation conditions: metal Ni/Au, thickness 50 nm / 400 nm. As shown in S9 in Fig. 4.
  • the structure of the finished HEMT device is shown in Figure 3.
  • the reliability is greatly improved, compared with the existing p-gate technology.
  • the production cost is greatly reduced, the yield rate is significantly improved, and the current collapse phenomenon is less likely to occur during the work process, and the work can be stabilized for a long time.

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Abstract

一种III族氮化物增强型HEMT及其制备方法。所述制备方法包括：在衬底上生长形成主要由作为势垒层的第二半导体和作为沟道层的第一半导体组成的异质结构，其中所述第二半导体叠设在第一半导体上；在第二半导体上形成兼作钝化层的掩膜层；对掩膜层的栅极区进行刻蚀，至暴露出第二半导体；在所述掩膜层的栅极区内生长p型层，所述p型层与第二半导体组成PN结；在所述p型层上设置p型栅，且使所述p型栅与p型层之间形成欧姆接触或肖特基接触。本发明工艺极大降低了p型栅技术的实施难度，并有效解决增强型HEMT器件的可靠性问题，以及有效抑制电流崩塌效应，从而大幅提升HEMT器件的工作性能，实现真正意义上的增强型HEMT。

Description

III族氮化物增强型HEMT及其制备方法 技术领域
本发明涉及一种高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)的制备方法，特别涉及一种III族氮化物增强型HEMT的制备方法，属于半导体技术领域。
背景技术
相比于传统的硅基MOSFET，基于AGaN/GaN异质结的高电子迁移率晶体管(HEMT)具有低导通电阻、高击穿电压、高开关频率等独特优势，从而能够在各类电力转换系统中作为核心器件使用，在节能减耗方面有重要的应用前景，因此受到学术界、工业界的极大重视。然而，由于III族氮化物材料体系的极化效应，一般而言，基于AlGaN/GaN异质结的HEMT均是耗尽型(常开)，该类型的器件应用于电路级系统中时，需要设计专门的负极性电源供给电路，以实现对器件的开关控制，这极大增加了电路的复杂性与成本。此外，耗尽型器件在失效安全能力方面存在缺陷，因此，无法真正实现商业化应用。为解决该问题，几种技术方案被提出以制备增强型(常关)器件。目前，常规技术主要包括氟离子注入技术、槽栅技术(Recessed Gate Technology)，其中前者利用含氟的等离子体(如CF4)对器件栅极区域进行处理，将带负电荷的氟离子注入至AlGaN势垒层，从而耗尽栅极下方的二维电子气，其对氟离子在势垒层中的稳定性有很高要求，并且由于HEMT器件在导通状态时要求大电流、高电压，沟道处的局部高温将会导致氟离子的热移动，影响氟离子的空间分布，从而导致阈值电压偏移，此外氟离子注入过程中，不可避免地会对势垒层造成损伤，故而必须在完成栅极制备后进行低温退火以对损伤进行恢复。后者主要通过干法刻蚀技术(主要是ICP、RIE)将栅极所在区域的AlGaN势垒层刻薄，从而耗尽栅极下方的二维电子气，参阅图1，因过刻蚀或者欠刻蚀均无法实现增强型HEMT制备，故需要对刻蚀深度实现精确控制(一般在15nm左右)，此外刻蚀过程中不可避免会对势垒层表面造成损伤从而影响肖特基势垒，并且刻蚀过程中，在势垒层中引入的杂质、缺陷会加剧器件的栅极漏电(事实上，薄势垒层本身就会引起较大的栅极漏电)。因此，上述两种技术的缺点在于无法保证增强型HEMT的可靠性，无法实现商业化应用。
出于可靠性的考虑，目前大部分市售产品采用基于耗尽型HEMT的Cascode结构，即将耗尽型HEMT与增强型硅MOSFET进行封装集成，通过控制硅MOSET的导通，间接控制HEMT栅极(接地)与源极之间的电势差，从而实现“赝常关型”HEMT，但其并非真正意义上 的增强型HEMT，并且由于Cascode结构要求与硅MOSFET进行集成，因此额外增加了封装工艺的复杂性与成本。
最近出现了基于p型栅的增强型HEMT制备技术，其有望实现真正意义上的增强型HEMT。该技术在传统HEMT外延结构基础上，在AlGaN势垒层(非故意掺杂n型)上外延生长p型层，并进行选区刻蚀实现p型栅制备，从而形成pn结，空间电荷区(主要存在于势垒层与沟道层中)对沟道处二维电子气进行有效耗尽，如图2所示。由于增强型HEMT仅要求栅极下方的电子被耗尽，选区刻蚀制备p型栅是必需的。但在进行选区刻蚀过程中，过刻蚀或者欠刻蚀均会导致器件栅源、栅漏之间区域的二维电子气浓度降低，从而严重影响器件在工作时的导通电阻。因此，该p型栅技术要求对非栅极区域的p型层的刻蚀深度精确可控，这也极大增加了p型栅技术的难度，并使得该技术的重复性(片与片之间)、均匀性(片内不同区域之间)、稳定性(不同轮工艺之间)难以保证，不适用于大规模生产。此外，选区刻蚀p型层会在非栅极区域不可避免地引入额外的表面态、缺陷态，使得器件的电流崩塌现象更为严重，从而严重影响器件的可靠性。
发明内容
本发明的主要目的在于提供一种III族氮化物增强型HEMT及其制备方法，从而克服现有技术中的不足。
为实现前述发明目的，本发明采用的技术方案包括：
一种III族氮化物增强型HEMT的制备方法，包括：
(1)在衬底上生长形成主要由作为势垒层的第二半导体和作为沟道层的第一半导体组成的异质结构，其中所述第二半导体叠设在第一半导体上；
(2)在第二半导体上形成兼作钝化层的掩膜层；
(3)对掩膜层的栅极区进行刻蚀，至暴露出第二半导体；
(4)在所述掩膜层的栅极区内生长p型层，所述p型层与第二半导体组成PN结；
(5)在所述p型层上设置p型栅，且使所述p型栅与p型层之间形成欧姆接触或肖特基接触。
显然的，所述第二半导体具有宽于第一半导体的带隙。
在一实施方案之中，所述异质结构与衬底之间还分布有高阻层。
其中，所述高阻层作用在于使有源区沟道与衬底之间形成良好的绝缘隔离，提高器件击穿电压。所述高阻层的材质可以选自GaN、AlGaN或两者的组合等，但不限于此。
在一实施方案之中，步骤(1)还可包括：依次在衬底上生长形成成核层、应力控制层、高阻层和所述异质结构。
其中，所述成核层的作用在于使外延材料高质量地生长在衬底上。所述成核层的材质可以选自AlN、GaN或两者的组合等，但不限于此。
其中，所述应力控制层的作用在于抵消材料外延生长过程中因晶格失配、热膨胀系数失配等原因而累积产生的应力，从而有效抑制外延片翘曲、裂纹等现象。所述应力控制层的材质可以选自单层AlGaN、双层或双层以上变铝组分AlGaN等，但不限于此。
在一实施方案之中，所述异质结构还可包括分布在第一、第二半导体之间的插入层。其中，所述插入层的作用在于使沟道处二维电子气获得更好的空间量子限域特性以及减小合金散射，提高电子迁移率。所述插入层的材质可以选自与沟道层形成较高带阶差的材料，例如AlN、AlInN或AlInGaN等，但不限于此。
在一实施方案之中，步骤(3)可以包括：先在掩膜层上形成光刻胶层，并对光刻胶层的p型栅区光刻处理，至暴露出掩膜层，而后以光刻胶层作为掩膜，对掩膜层的栅极区进行刻蚀，至暴露出第二半导体。其中，刻蚀方式可优选为干法刻蚀方式，例如RIE、ICP刻蚀等。而湿法腐蚀工艺也可用于在某些特定条件下(如低温等)生长的掩膜层。
在一实施方案之中，该制备方法还可包括：
(6)对步骤(5)所获器件进行刻蚀，实现有源区隔离。
在一实施方案之中，该制备方法还可包括：
(7)对步骤(6)所获器件的源、漏极区进行刻蚀，至暴露出第二半导体，以及在所述源、漏极区内分别设置源极和漏极，且使所述源极和漏极与第二半导体形成欧姆接触。
在一实施方案之中，该制备方法还可包括：
(8)在步骤(7)所获器件上设置分别与源极和漏极电性连接的引出电极。
进一步的，所述衬底包括硅、蓝宝石、碳化硅、氮化铝或氮化镓衬底，但不限于此。
进一步的，所述第二半导体的材质包括AlGaN、AlN、AInN或AlInGaN，所述第一半导体的材质包括GaN，但均不限于此。
进一步的，所述掩膜层的材质包括无定形氮化硅、无定形氧化硅、无定形氮氧硅、无定形氮化铝中的任一种或两种以上的组合，但不限于此。
进一步的，该制备方法之中材料外延生长工艺可以选自MBE(Molecular Beam Epitaxy，分子束外延)、MOCVD(Metal Organic Chemical Vapor Deposition,金属有机物化学气相沉积)等，且不限于此。
进一步的，该制备方法之中掩膜层/钝化层的沉积工艺可以选自PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)、MOCVD、LPCVD(Low Pressure Chemical Vapor Deposition，低压化学气相沉积)、ALD(Atom Layer Deposition，原子层沉积)、PLD(Pulsed Laser Deposition，脉冲激光沉积)等，且不限于此。
进一步的，所述p型层的材质包括p-AlGaN、p-GaN、p-AlGaN、p-AlInN、p-InGaN、p-AlInGaN中的任一种或两种以上的组合，但不限于此。
采用前述任一种工艺制备的III族氮化物增强型HEMT器件。
进一步的，在本发明中，HEMT的有源区结构可不仅仅局限于AlGaN/AlN/GaN异质结，也可以适用于具有其他有源区结构的HEMT，如基于近晶格匹配的AlInN/AlN/GaN、AlInGaN/AlN/GaN异质结HEMT、基于双沟道异质结的HEMT等。
与现有技术相比，本发明的优点包括：
(1)较之增强型HEMT的常规制备技术，如氟离子注入技术、槽栅技术、Cascode结构技术，本发明工艺可以有效解决器件的可靠性问题，实现真正意义上的增强型HEMT；
(2)较之基于选区刻蚀的p型栅技术，本发明工艺采取选区外延生长技术，在HEMT的外延生长层面直接解决p型栅的定位问题，从而省略了刻蚀非栅极区域的p型层的工艺步骤，极大降低了p型栅技术的实施难度，确保了工艺的重复性、均匀性、稳定性，适于大规模生产，同时，还避免了对栅-源、栅-漏之间区域的刻蚀，减小了引入额外的表面态的可能性，且采用的刻蚀掩膜层同时作为钝化层，极好地保护了器件表面，可以有效抑制电流崩塌。
附图说明
图1是槽栅技术制备增强型HEMT器件的示意图；
图2是p型栅技术制备增强型HEMT器件的示意图；
图3是本发明一典型实施案例中一种增强型HEMT器件的结构示意图；
图4是本发明一典型实施案例中一种增强型HEMT器件的制作工艺流程图。
具体实施方式
如前所述，鉴于现有技术的诸多缺陷，例如常规p型栅技术采取选区刻蚀的方案要求对非栅极区域的p型层的刻蚀深度精确可控，故而存在实施难度较大等缺陷。本案发明人经长期研究和大量实践，提出了本发明的技术方案，其是基于选区外延生长的新型p型栅技术，可在HEMT的外延生长过程中直接解决p型栅的定位问题，从而避开了刻蚀非栅极区域的p型层的工艺步骤，极大降低了p型栅技术的实施难度，确保了工艺的重复性、均匀性、稳定性，同时还能够有效抑制电流崩塌，从而提高器件的可靠性。
如下结合附图及一较佳实施例对本发明的技术方案作进一步的说明。
如下实施例涉及一种基于硅衬底及AlGaN/AlN/GaN异质结的HEMT器件，其中采用p-AlGaN作为p型层。
参阅图4，该HEMT器件的制备工艺可以包括：
S1：基于硅衬底的HEMT外延结构的制作；
S2：在HEMT外延结构上通过PECVD等工艺生长氮化硅作为掩膜层(钝化层)；
S3：光刻p型栅区域；
S4：RIE刻蚀栅极区域氮化硅掩膜层；
S5：MOCVD选区外延生长p-AlGaN；
S6：p型栅欧姆接触；
S7：有源区隔离；
S8：源、漏欧姆接触；
S9：引线电极制备。
更为具体的，该HEMT器件的制备工艺包括如下具体步骤：
1.MOCVD外延生长基于AlGaN/GaN异质结的HEMT。其中，AlGaN势垒层Al组分x为10％～30％，厚度为10～25nm；AlN插入层约为1nm；GaN沟道层为50～200nm，完整的基于硅衬底的HEMT外延结构如图4中S1所示。
2.PECVD生长氮化硅作为掩膜层，同时，氮化硅又作为钝化层，可以有效抑制电流崩塌效应。生长条件：衬底温度为100～350℃，反应腔室压强为1700mtorr,SiH4流量为13～45sccm，NH3流量为10～90sccm，N2吹扫流量为1000sccm，RF功率为67W，LF功率为53W。氮化硅掩膜层厚度为50–300nm，如图4中S2所示。
3.光刻p型栅区域。光刻条件：光刻胶AZ5214厚度1.5μm，硬接触模式下曝光6.5s，JZX3038显影45s,110℃下坚膜5min。p型栅区域尺寸为3μm×104μm，如图4中S3所示。在这一步工艺中，同时完成套刻标记的光刻。
4.利用光刻胶AZ5214作为掩膜，RIE刻蚀栅极区域氮化硅掩膜层。刻蚀条件：衬底温度为室温，腔室压强为1500mtorr，反应气体SF6流量为8sccm，反应气体CHF3流量为10sccm，载气He流量为150sccm，RF功率为200W。如图4中S4所示。在这一步工艺中，同时完成套刻标记区域的氮化硅掩膜层刻蚀。
5.MOCVD选区外延生长p-AlGaN。生长条件：生长温度500～1100℃，反应室压强55～500mbar，p-AlGaN镁掺杂浓度范围为1×1017～5×20cm-3，生长厚度为50～200nm。如图4中S5所示。
6.p型栅欧姆接触制备。制备条件：金属Pd/Pt/Au，厚度为30nm/30nm/50nm，退火条件为550℃，90s，氮气气氛。如图4中S6所示
7.采用RIE、ICP刻蚀，进行有源区隔离，其中，RIE刻蚀第2步生长的氮化硅掩膜层(钝化层)，ICP刻蚀至高阻层GaN或AlGaN。刻蚀条件：RIE刻蚀条件同4，确保氮化硅全部刻蚀；ICP刻蚀，衬底温度为室温，腔室压强为6mtorr，反应气体Cl2流量为30sccm，反应气体BCl3流量为30sccm，RF功率为100W，ICP功率为300W。如图4中S7所示。
8.采用RIE刻蚀，进行源漏欧姆接触开窗。刻蚀条件同4，确保氮化硅全部刻蚀，AlGaN势垒层可以略微刻蚀一些(～1nm)。
9.源漏欧姆接触制备。制备条件：金属Ti/Al/Ni/Au，厚度为20nm/130nm/50nm/150nm，退火条件为890℃，30s，氮气气氛。如图4中S8所示。
10.引线电极制备。制备条件：金属Ni/Au，厚度为50nm/400nm。如图4中S9所示。
该HEMT器件成品的结构请参阅图3，其较之采用氟离子注入技术、槽栅技术、Cascode结构技术制备的同类器件，可靠性有大幅提升，而较之采用现有p型栅技术制备的同类器件，制作成本大幅降低，良品率有显著提升，在工作过程中亦较少出现电流崩塌现象，能长时间稳定工作。
应当理解的是，对于本领域的普通技术人员来说，可以根据本发明的技术构思做出其他各种相应的改变与变形，而所有这些改变与变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种III族氮化物增强型HEMT的制备方法，其特征在于包括：
    (1)在衬底上生长形成主要由作为势垒层的第二半导体和作为沟道层的第一半导体组成的异质结构，其中所述第二半导体叠设在第一半导体上；
    (2)在第二半导体上形成兼作钝化层的掩膜层；
    (3)对掩膜层的栅极区进行刻蚀，至暴露出第二半导体；
    (4)在所述掩膜层的栅极区内生长第三半导体，所述第三半导体与第二半导体的导电类型不同，并且所述第三半导体为p型半导体；
    (5)在所述第三半导体上设置p型栅，且使所述p型栅与第三半导体之间形成欧姆接触或肖特基接触。
  2. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于：所述异质结构与衬底之间还分布有高阻层。
  3. 根据权利要求2所述III族氮化物增强型HEMT的制备方法，其特征在于，步骤(1)包括：依次在衬底上生长形成成核层、应力控制层、高阻层和所述异质结构。
  4. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于：所述异质结构还包括分布在第一、第二半导体之间的插入层，所述插入层的材质包括能与沟道层形成较高带阶差的材料。
  5. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于步骤(3)包括：先在掩膜层上形成光刻胶层，并对光刻胶层的p型栅区光刻处理，至暴露出掩膜层，而后以光刻胶层作为掩膜，对掩膜层的栅极区进行刻蚀，至暴露出第二半导体。
  6. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于还包括：
    (6)对步骤(5)所获器件进行刻蚀，实现有源区隔离。
  7. 根据权利要求6所述III族氮化物增强型HEMT的制备方法，其特征在于还包括：
    (7)对步骤(6)所获器件的源、漏极区进行刻蚀，至暴露出第二半导体，以及在所述源、漏极区内分别设置源极和漏极，且使所述源极和漏极与第二半导体形成欧姆接触。
  8. 根据权利要求7所述III族氮化物增强型HEMT的制备方法，其特征在于还包括：
    (8)在步骤(7)所获器件上设置分别与源极和漏极电性连接的引出电极。
  9. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于：所述衬底包括硅、蓝宝石、碳化硅、氮化铝或氮化镓衬底。
  10. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于：所述第二半导体的材质包括AlGaN、AlN、AlInN或AlInGaN。
  11. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于：所述第一半导体的材质包括GaN。
  12. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于：所述掩膜层的材质包括氮化硅、氧化硅、氮氧硅、氮化铝中的任一种或两种以上的组合。
  13. 根据权利要求1所述III族氮化物增强型HEMT的制备方法，其特征在于：所述第三半导体的材质包括p-AlGaN、p-GaN、p-AlGaN、p-AlInN、p-InGaN、p-AlInGaN中的任一种或两种以上的组合。
  14. 采用权利要求1-13中任一项所述方法制备的III族氮化物增强型HEMT器件。
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