WO2017113484A1 - 高电子迁移率晶体管及其制造方法 - Google Patents

高电子迁移率晶体管及其制造方法 Download PDF

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WO2017113484A1
WO2017113484A1 PCT/CN2016/074013 CN2016074013W WO2017113484A1 WO 2017113484 A1 WO2017113484 A1 WO 2017113484A1 CN 2016074013 W CN2016074013 W CN 2016074013W WO 2017113484 A1 WO2017113484 A1 WO 2017113484A1
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metal
barrier layer
gate
layer
drain
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French (fr)
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陈家诚
姚建可
丁庆
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深圳市华讯方舟微电子科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the present invention relates to the field of semiconductor devices, and in particular to a High Electron Mobility Transistor (HEMT) having a laterally different AlGaN barrier layer and a method of fabricating the same.
  • HEMT High Electron Mobility Transistor
  • the semiconductor material gallium nitride (GaN) is considered to be an excellent semiconductor material for high-power, high-speed semiconductor devices due to its large forbidden band width, high critical breakdown electric field, and high electron saturation speed.
  • HEMT High Electron Mobility Transistor
  • GaN gallium nitride
  • AlN aluminum nitride
  • the relative dielectric constant and the forbidden band width of AlxGa(1-x)N can also be continuously adjusted with x.
  • the wurtzite-structured AlGaN and GaN crystals do not have reverse symmetry in the (0001) direction, there is a spontaneous polarization effect in this direction, and the pressure electrodes of the lattice constants of AlGaN and GaN do not match.
  • the concentration of electron gas has a decisive influence on the performance of the device, and its concentration is closely related to the value of aluminum in the aluminum gallium nitride AlxGa(1-x)N.
  • the electron gas concentration at the AlGaN/GaN interface and the switching during the period can be controlled by the voltage of the gate. After the drain-source voltage reaches a certain level, the drain current of the device will decrease with respect to the saturation current. This is the ubiquitous current collapse effect of the HEMT, and the current collapse effect may cause degradation of the performance of the device.
  • the composition of aluminum in AlGaN grown by a certain method in a HEGaN device of AlGaN/GaN is constant. Due to the current collapse problem, due to the spontaneous polarization and piezoelectric polarization effects of the AlGaN/GaN heterojunction, the turn-on voltage is negative, making it generally an enhancement transistor.
  • a high electron mobility transistor comprising:
  • a barrier layer formed of a compound containing a first metal and a second metal formed on the buffer layer of the first metal compound
  • a passivation layer formed between the source and the gate and between the drain and the gate characterized by:
  • the barrier layer is divided into a first barrier layer and a second barrier layer in a lateral direction;
  • the first barrier layer is adjacent to the source between the gate and the source, and the composition of the second metal in the compound containing the first metal and the second metal remains unchanged;
  • the second barrier layer is adjacent to the drain between the gate and the drain, and the composition of the second metal in the compound containing the first metal and the second metal gradually increases from the gate terminal to the drain terminal Reduced.
  • the first metal is gallium (Ga) and the second metal is aluminum (Al).
  • the compound containing the first metal and the second metal is an aluminum gallium alloy, that is, AlxGa(1-x)N, and the composition of Al in the first barrier layer is constant.
  • the composition of Al in the second barrier layer is smaller with respect to the first barrier layer, and the composition from the gate terminal to the drain terminal A1 gradually decreases.
  • a method of fabricating a high electron mobility transistor comprising:
  • Defining a region of the barrier layer growing a barrier layer composed of a compound of the first metal and the second metal such that a composition of the second metal in the compound of the first metal and the second metal is different;
  • a gate electrode in which a composition of a second metal in a region between the gate and the drain is different, and a composition of the second metal gradually decreases from a gate end to a drain terminal;
  • a passivation layer is formed between the source and the gate and the drain and the gate.
  • the high electron mobility transistor of the present invention has an AlxGa(1-x)N barrier layer having a different lateral Al composition, and an AlxGa(1-x)N barrier layer near the drain terminal at the gate edge.
  • the aluminum composition gradually decreases from the gate terminal to the drain terminal, and the barrier layer structure having different lateral compositions can reduce the current collapse effect.
  • improving the turn-on voltage of the GaN-based high electron mobility transistor is beneficial to the design of the power amplifier circuit of the subsequent high electron mobility transistor based on AlGaN/GaN.
  • FIG. 1 is a schematic cross-sectional view showing a high electron mobility transistor according to a first embodiment of the present invention.
  • FIG. 2 is a graph comparing the characteristics of the high electron mobility transistor Id-Vg & Id-Vd of the prior art and the present invention.
  • FIG 3 is a schematic cross-sectional view of a high electron mobility transistor according to another embodiment of the present invention.
  • a high electron mobility transistor 100 includes a substrate 10 , a nucleation layer (not shown) formed on the substrate 10 , a buffer layer 20 , a barrier layer 30 , and a source .
  • the pole 40, the drain 50, the gate 60 and the passivation layer 70 are not shown.
  • the material of the substrate 10 may be sapphire, silicon carbide (SiC), or silicon.
  • the material of the nucleation layer may be aluminum nitride (AlN) or gallium nitride (GaN). Or aluminum gallium nitride (AlGaN), the nucleation layer has a thickness of between 100 nm and 200 nm.
  • the buffer layer 20 is gallium nitride (GaN) and has a thickness ranging from 1.5 um to 3 um.
  • the buffer layer 20 is grown on the nucleation layer by molecular velocity epitaxy (MBE) or metal organic vapor phase deposition (MOCVD).
  • the barrier layer 30 is an aluminum gallium nitride layer having a thickness ranging from 10 nm to 40 nm, and the aluminum gallium nitride barrier layer 40 has a chemical formula of AlxGa(1-x)N, wherein the composition of the Al is adjustable. The value of x ranges from 0.15 to 0.35.
  • the barrier layer 30 is formed on the buffer layer 20 by a metal organic vapor phase deposition (MOCVD) method.
  • MOCVD metal organic vapor phase deposition
  • the AlxGa(1-x)N barrier layer 30 has a different composition of Al in the lateral direction.
  • a layer of AlN having a thickness of 1 nm to 2 nm may be formed between the barrier layer 30 and the buffer layer 20 as a buffer layer of the interface.
  • the source 40 and the drain 50 are ohmic contact structures respectively formed at both ends of the AlxGa(1-x)N barrier layer 30 in the lateral direction.
  • the source 40 and the drain 50 may be a metal stacked layer of titanium, aluminum, nickel or gold (Ti, Al, Ni, Au).
  • the gate 60 is a Schottky contact structure formed on the AlxGa(1-x)N barrier layer 30.
  • the gate 60 may be a stacked layer of nickel or gold (Ni, Au).
  • a layer of high dielectric constant material or gallium nitride layer may be further deposited on the AlxGa(1-x)N barrier layer 30 before forming the three ends of the source and drain gates.
  • the Al x Ga (1-x) N barrier layer 30 is divided into two portions in the lateral direction, including the first barrier layer 31 between the gate 60 and the source 40 and between the gate 60 and the drain 50
  • the second barrier layer 32 The composition of Al in the first barrier layer 31 is constant, the composition of Al in the second barrier layer 32 is smaller relative to the first barrier layer 31, and the aluminum component from the gate 60 end to the drain 50 end. slowing shrieking.
  • the second barrier layer 32 the composition of Al from left to right gradually decreases from 0.3 to 0.25, wherein the drain is adjacent to the drain.
  • the second barrier layer 32 there are five different composition steps. The interval is 0.01/0.02 ⁇ m.
  • FIG. 2 is a comparison diagram of the Id-Vg & Id-Vd characteristic curves of the conventional HEMT of a certain composition of AlxGa(1-x)N/GaN structure and the HEMT of the present invention.
  • this The HEMT of the AlxGa(1-x)N/GaN structure having different compositions of the invention has a larger turn-on voltage than the HEMT of the prior art component having a certain AlxGa(1-x)N/GaN structure; Under the same gate-drain voltage, the current collapse effect is reduced.
  • the method of manufacturing the high electron mobility transistor 100 of the present invention includes the following steps:
  • Step 1 A substrate 10 is provided, and a nucleation layer is grown on the cleaned substrate 10.
  • the material of the substrate 10 may be sapphire, silicon carbide (SiC), or silicon.
  • the material of the nucleation layer may be aluminum nitride (AlN), gallium nitride (GaN) or aluminum gallium nitride (AlGaN), and the nucleation layer has a thickness of between 100 nm and 200 nm.
  • Step 2 A layer of gallium nitride buffer layer 20 is grown by a molecular velocity epitaxy (MBE) method or a metal organic vapor phase deposition (MOCVD) method, and the buffer layer 20 has a thickness ranging from 1.5 um to 3 um.
  • MBE molecular velocity epitaxy
  • MOCVD metal organic vapor phase deposition
  • Step 3 Using the region of the barrier layer 30 defined by the photoresist, the AlxGa(1-x)N barrier layer 30 having different Al composition is grown.
  • the method of growing AlxGa(1-x)N can control the composition of Al by controlling the flow rate of trimethylaluminum (TMAl), trimethylgallium (TMGa), and ammonia by MOCVD. .
  • the flow rate of trimethylaluminum (TMAl) and trimethylgallium (TMGa) may be 0.6 to 33 mol/min; and the flow rate of ammonia may be 0.08 to 0.32 mol/min.
  • the AlxGa (1-x) N barrier layer 30 has a thickness of 10 nm to 40 nm.
  • the composition of Al is adjustable, and the value of x ranges from 0.15 to 0.35.
  • Step 4 Deblocking is performed to form a source 40 and a drain 50.
  • the source 40 is in ohmic contact with the drain 50.
  • the source 40 and the drain 50 regions are defined, the aluminum gallium nitride is removed by RIE, and then the metal layer is deposited, and rapid thermal annealing (RTA) is performed to form the source 40 and the drain 50.
  • RTA rapid thermal annealing
  • An ohmic contact facilitates the transfer of two-dimensional electron gas (2DEG) between source 40 and drain 50.
  • the source 40 and the drain 50 may be a metal stack of titanium, aluminum, nickel or gold (Ti, Al, Ni, Au).
  • Step 5 Form a gate 60, which is a Schottky contact structure. Specifically, a region of the gate 60 is defined and a gate metal layer is deposited to enable control of the transmission of the 2DEG.
  • the gate metal layer may be a stacked layer of nickel or gold (Ni, Au).
  • the composition of Al between the gate 60 and the drain 50 of the Al x Ga (1-x) N barrier layer 30 is smaller than the composition of Al between the gate 60 and the source 40, Also, the aluminum composition gradually decreases from the gate 60 end to the drain 50 end.
  • Step 6 After the source 40, the drain 50 and the gate 60 are formed, then a passivation layer 70 is formed between the source 40 and the gate 60 and the drain 50 and the gate 60.
  • the passivation layer 70 is A layer of silicon nitride (Si3N4) is used to reduce the current collapse effect.
  • a layer buffer layer having a thickness of 1 nm to 2 nm is formed, and the material of the interface buffer layer is aluminum nitride (AlN).
  • step 5 the deposition of a high dielectric constant material layer or a gallium nitride layer is also included.
  • the high electron mobility transistor 100 of the present invention has an AlxGa(1-x)N barrier layer 30 having a different lateral Al composition, and AlxGa(1-x) near the drain 50 end at the edge of the gate 60.
  • the N barrier layer 30 has characteristics of different compositions.
  • the aluminum composition gradually decreases from the gate 60 end to the drain 50 end, and such a barrier composition having a different lateral composition can reduce the current collapse effect.
  • improving the turn-on voltage of the GaN-based high electron mobility transistor 100 facilitates the design of the power amplifier circuit of the subsequent high-electron mobility transistor 100 based on AlGaN/GaN.
  • the Al xGa(1-x)N barrier layer 30 of the high electron mobility transistor 100 may also be a structure having two segments, three segments, four segments, and a continuously adjustable Al composition. .

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Abstract

提供一种高电子迁移率晶体管（100）及其制造方法。该高电子迁移率晶体管（100）包括：衬底（10），形成于衬底（10）上的氮化镓缓冲层（20）、形成于氮化镓缓冲层（20）上的AlxGa(1-x)N势垒层（30）、分别形成于AlxGa(1-x)N势垒层（30）上的栅极（60）、源极（40）及漏极（50），以及钝化层（70）。在AlxGa(1-x)N势垒层（30）中，横向方向Al组分不同，从栅极端到漏极端Al组分逐渐减小。相对于现有技术，该高电子迁移率晶体管具有横向Al组分不同的AlxGa(1-x)N势垒层，在栅极边缘靠近漏极端的AlxGa(1-x)N势垒层具有不同组分的特性，从栅极端到漏极端Al组分逐渐减小，从而能够减小电流崩塌效应，提高开启电压。

Description

高电子迁移率晶体管及其制造方法 【技术领域】
本发明涉及一种半导体器件领域，具体涉及一种具有横向组分不同的AlGaN势垒层的高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)及其制造方法。
【背景技术】
半导体材料氮化镓(GaN)由于其拥有较大的禁带宽度、较高的临界击穿电场以及较高的电子饱和速度，被认为是一种制作大功率、高速半导体器件的优良半导体材料。
氮化镓基的半导体材料在高频大功率领域主要的应用是高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)。作为直接带隙半导体材料，氮化镓(GaN)和氮化铝(AlN)的带隙可从3.4eV到6.2eV连续变化，形成掺杂、可调制的AlGaN/GaN的异质结结构；同时AlxGa(1-x)N的相对介电常数、禁带宽度也可以随着x连续可调。由于纤锌矿(wurtzite)结构的AlGaN和GaN晶体在(0001)方向不具备反转对称性，在此方向上存在自发极化效应，同时AlGaN和GaN的晶格常数不匹配导致的压电极化效应，禁带宽度不一样的AlGaN和GaN之间形成的异质结，由于这两种效应的叠加，使得在GaN一端形成高浓度的二维电子气。其中，电子气的浓度对器件性能有决定性影响，其浓度与氮化铝镓AlxGa(1-x)N中铝成分x值有密切关系。
对于HEMT器件，通过栅极(Gate)的电压，可以控制AlGaN/GaN界面的电子气浓度以及期间的开关。在漏源电压达到一定程度之后，器件的漏极电流相对于饱和电流会有下降的现象，这就是HEMT普遍存在的电流崩塌(Current Collapse)效应，电流崩塌效应会导致器件的性能退化。
目前AlGaN/GaN的HEMT器件中通过一定方法生长的AlGaN中的铝的成分一定。由于存在电流崩塌问题，同时由于AlGaN/GaN异质结的自发极化和压电极化效应，其开启电压为负，使其一般为增强型晶体管。
【发明内容】
鉴于以上内容，有必要提供一种可减小电流崩塌效应，并可提高开启电压的高电子迁移率晶体管及其制造方法。
一种高电子迁移率晶体管，包括：
衬底；
形成于所述衬底上的第一金属化合物缓冲层；
形成于所述第一金属化合物缓冲层上的由含有第一金属和第二金属的化合物构成的势垒层；
分别形成于所述势垒层上的栅极、源极及漏极；以及
形成于源极与栅极和漏极与栅极之间的钝化层，其特征在于：
所述势垒层在横向方向上分为第一势垒层和第二势垒层；
所述第一势垒层，靠近源极，位于栅极与源极之间，其含有第一金属和第二金属的化合物中第二金属的组分维持不变；
所述第二势垒层，靠近漏极，位于栅极与漏极之间，其含有第一金属和第二金属的化合物中第二金属的组分从所述栅极端到所述漏极端逐渐减小。
上述高电子迁移率晶体管中，所述第一金属为镓(Ga)，所述第二金属为铝(Al)。
上述高电子迁移率晶体管中，所述含有第一金属和第二金属的化合物为铝镓合金，即AlxGa(1-x)N，则在所述第一势垒层中Al的组分一定，所述第二势垒层中Al的组分相对于第一势垒层较小，并且从栅极端到漏极端Al的组分逐渐减小。
一种高电子迁移率晶体管的制造方法，包括：
于一衬底上生长一成核层；
形成一第一金属化合物缓冲层；
定义一势垒层的区域，生长由第一金属和第二金属的化合物构成的势垒层，使得所述第二金属在所述第一金属和第二金属的化合物中的组分不同；
去光阻，形成源极及漏极；
形成栅极，所述势垒层中，栅极与漏极之间区域的第二金属的组分不同，并且，从栅极端到漏极端第二金属的组分逐渐减小；
在源极与栅极和漏极与栅极之间形成钝化层。
相对于现有技术，本发明的高电子迁移率晶体管具有横向Al组分不同的AlxGa(1-x)N势垒层，在栅极边缘靠近漏极端的AlxGa(1-x)N势垒层具有不同组分的特性。从栅极端到漏极端铝组分逐渐减小，这种横向组分不同的势垒层结构能够减小电流崩塌效应。并且提高基于GaN基高电子迁移率晶体管的开启电压，有利于后续基于AlGaN/GaN的高电子迁移率晶体管的功放电路的设计。
【附图说明】
图1为本发明第一实施方式的高电子迁移率晶体管的剖面示意图。
图2为现有技术与本发明的高电子迁移率晶体管Id-Vg&Id-Vd特性曲线比较图。
图3为本发明其他实施方式的高电子迁移率晶体管的剖面示意图。
【具体实施方式】
下面结合附图和实施方式对本发明作进一步说明。
请参阅图1，本发明实施方式提供的高电子迁移率晶体管100包括衬底10、形成于所述衬底10上的成核层(图未示)、缓冲层20、势垒层30、源极40、漏极50、栅极60及钝化层70。
本实施方式中，所述衬底10的材料可以是蓝宝石(sapphire)、碳化硅(SiC)、硅(silicon)。所述成核层的材料可以是氮化铝(AlN)、氮化镓(GaN) 或氮化铝镓(AlGaN)，成核层厚度为100nm～200nm之间。
所述缓冲层20为氮化镓(GaN)，其厚度范围为1.5um～3um。在本实施方式中，缓冲层20通过分子速外延(MBE)或者金属有机气相沉积(MOCVD)方法生长于成核层上。
所述势垒层30为氮化铝镓层，其厚度范围为10nm～40nm，所述氮化铝镓势垒层40的化学式为AlxGa(1-x)N，其中，Al的成分可调，x的值范围为0.15～0.35。在本实施方式中，所述势垒层30通过金属有机气相沉积(MOCVD)方法形成于缓冲层20上。AlxGa(1-x)N势垒层30在横向方向上Al的组分不同。
在其他实施方式中，还可以在势垒层30与缓冲层20之间形成一层厚度为1nm～2nm的AlN，作为界面的缓冲层。
所述源极40和漏极50为欧姆接触结构，分别形成在AlxGa(1-x)N势垒层30横向方向的两端。在本实施方式中，源极40和漏极50可以是钛、铝、镍或金(Ti、Al、Ni、Au)的金属堆叠层。
所述栅极60为肖特基接触结构，其形成在AlxGa(1-x)N势垒层30上。在本实施方式中，栅极60可以是镍或金(Ni、Au)的堆叠层。
在其他实施方式中，在形成源漏栅三端之前，还可以在AlxGa(1-x)N势垒层30上再淀积一层高介电常数材料层或者氮化镓层。
所述AlxGa(1-x)N势垒层30在横向方向上被分成两个部分，包括栅极60与源极40之间的第一势垒层31以及栅极60与漏极50之间的第二势垒层32。在第一势垒层31中Al的组分一定，第二势垒层32中Al的组分相对于第一势垒层31较小，并且从栅极60端到漏极50端铝组分逐渐减小。具体的，在第一势垒层31中，Al的组分为x＝0.3，在第二势垒层32中，从左至右Al的组分从0.3到0.25逐渐减小，其中临近漏极50区域的Al的组分为x＝0.25。在本实施方式中，在第二势垒层32中，具有五个不同组分阶梯。间隔为0.01/0.02μm。
请参阅图2，图2为现有的组分一定的AlxGa(1-x)N/GaN结构的HEMT与本发明的HEMT的Id-Vg&Id-Vd特性曲线比较图。从图中可以看出，本 发明的组分不同的AlxGa(1-x)N/GaN结构的HEMT相对于现有技术的组分一定的AlxGa(1-x)N/GaN结构的HEMT有较大的开启电压；而且，在相同栅漏电压下，电流崩塌效应有所减小。
本发明的高电子迁移率晶体管100的制造方法包括以下几个步骤：
步骤一：提供一衬底10，在清洗干净的所述衬底10上生长一层成核层。所述衬底10的材料可以是蓝宝石(sapphire)、碳化硅(SiC)、硅(silicon)。所述成核层的材料可以是氮化铝(AlN)、氮化镓(GaN)或氮化铝镓(AlGaN)，所述成核层厚度为100nm～200nm之间。
步骤二：利用分子速外延(MBE)方法或者金属有机气相沉积(MOCVD)方法生长一层氮化镓缓冲层20，所述缓冲层20的厚度范围为1.5um～3um。
步骤三：利用光阻定义出的势垒层30的区域，成长Al的组分不同的AlxGa(1-x)N势垒层30。具体的：生长AlxGa(1-x)N的方法可以通过MOCVD的方法，通过控制三甲基铝(TMAl)、三甲基镓(TMGa)以及氨气(ammonia)的流量，控制Al的组分。三甲基铝(TMAl)、三甲基镓(TMGa)的流量可以为：0.6～33摩尔/分钟；氨气(ammonia)的流量可以为0.08～0.32摩尔/分钟。AlxGa(1-x)N势垒层30的厚度为10nm～40nm的。Al的成分可调，x的值范围为：0.15～0.35。
步骤四：去光阻，形成源极40及漏极50，所述源极40与所述漏极50为欧姆接触。具体的，定义出所述源极40及漏极50区域，用RIE方法去除氮化铝镓，然后淀积金属层，在进行快速热退火(RTA)，以便形成源极40及漏极50的欧姆接触，便于二维电子气(2DEG)在源极40及漏极50之间的传输。所述源极40与所述漏极50可以是钛、铝、镍或金(Ti、Al、Ni、Au)的金属堆叠层。
步骤五：形成栅极60，所述栅极60为肖特基接触结构。具体的，定义出栅极60区域，淀积栅极金属层，以便能够控制2DEG的传输。栅极金属层可以是镍或金(Ni、Au)的堆叠层。所述AlxGa(1-x)N势垒层30在栅极60与漏极50之间的Al的组分小于栅极60与源极40之间的Al的组分， 并且，从栅极60端到漏极50端铝组分逐渐减小。
步骤六：在源极40、漏极50及栅极60形成之后，然后在源极40与栅极60和漏极50与栅极60之间形成钝化层70，所述钝化层70为一氮化硅(Si3N4)层，用于减小电流崩塌效应。
其他实施方式中，步骤三之前还包括形成一层厚度为1nm～2nm的界面缓冲层，所述界面缓冲层的材料为氮化铝(AlN)。
步骤五之后还包括淀积一高介电常数的材料层或者氮化镓层。
相对于现有技术，本发明的高电子迁移率晶体管100具有横向Al组分不同的AlxGa(1-x)N势垒层30，在栅极60边缘靠近漏极50端的AlxGa(1-x)N势垒层30具有不同组分的特性。从栅极60端到漏极50端铝组分逐渐减小，这种横向组分不同的势垒层结构能够减小电流崩塌效应。并且提高基于GaN基高电子迁移率晶体管100的开启电压，有利于后续基于AlGaN/GaN的高电子迁移率晶体管100的功放电路的设计。
请参阅图3，在其他实施方式中，高电子迁移率晶体管100的AlxGa(1-x)N势垒层30还可以是具有两段、三段、四段以及Al组分连续可调的结构。
本领域的技术人员在上述实施例的基础上，在不付出创造性劳动的前提下，可以推导出使用其他金属化合物来实现本发明的技术思路，例如，用砷化物代替氮化物，用其他金属离子代替铝离子和镓离子等；只要使得势垒层在靠近漏极的区域，化合物中一种金属的组分逐渐变化，以达到减小电流崩塌效应的目的即可。
以上所述的仅是本发明的实施方式，在此应当指出，对于本领域的普通技术人员来说，在不脱离本发明创造构思的前提下，还可以做出改进，但这些均属于本发明的保护范围。

Claims (11)

  1. 一种高电子迁移率晶体管，包括：
    衬底；
    形成于所述衬底上的第一金属化合物缓冲层；
    形成于所述第一金属化合物缓冲层上的由含有第一金属和第二金属的化合物构成的势垒层；
    分别形成于所述势垒层上的栅极、源极及漏极；以及
    形成于源极与栅极和漏极与栅极之间的钝化层，其特征在于：
    所述势垒层在横向方向上分为第一势垒层和第二势垒层；
    所述第一势垒层，靠近源极，位于栅极与源极之间，其含有第一金属和第二金属的化合物中第二金属的组分维持不变；
    所述第二势垒层，靠近漏极，位于栅极与漏极之间，其含有第一金属和第二金属的化合物中第二金属的组分从所述栅极端到所述漏极端逐渐减小。
  2. 据权利要求1所述的高电子迁移率晶体管，其特征在于：所述第一金属为镓(Ga)，所述第二金属为铝(Al)。
  3. 据权利要求2所述的高电子迁移率晶体管，其特征在于：所述含有第一金属和第二金属的化合物为铝镓合金，即AlxGa(1-x)N，则在所述第一势垒层中Al的组分一定，所述第二势垒层中Al的组分相对于第一势垒层较小，并且从栅极端到漏极端Al的组分逐渐减小。
  4. 据权利要求3所述的高电子迁移率晶体管，其特征在于：在第一势垒层中，Al的组分为x＝0.3，在第二势垒层中，从栅极端到漏极端Al的组分从0.3到0.25逐渐减小。
  5. 据权利要求3所述的高电子迁移率晶体管，其特征在于：所述衬底的材料为蓝宝石、碳化硅或硅，所述衬底与缓冲成之间还具有一成核层，所述成核层的材料氮化铝、氮化镓或氮化铝镓，所述成核层厚度范围为 100nm～200nm。
  6. 据权利要求2所述的高电子迁移率晶体管，其特征在于：所述缓冲层为氮化镓，其厚度范围为1.5um～3um，。
  7. 据权利要求3所述的高电子迁移率晶体管，其特征在于：所述AlxGa(1-x)N势垒层的厚度范围为10nm～40nm，其中，Al的成分可调，x的值范围为0.15～0.35。
  8. 据权利要求3所述的高电子迁移率晶体管，其特征在于：所述缓冲层与所述势垒层之间还具有一界面缓冲层，所述界面缓冲层的材料为氮化铝，所述氮化铝的厚度范围为1nm～2nm。
  9. 据权利要求3所述的高电子迁移率晶体管，其特征在于：所述氮化铝镓势垒层与栅极、源极及漏极之间还具有一高介电常数材料层或氮化镓层。
  10. 据权利要求1所述的高电子迁移率晶体管，其特征在于：所述源极/漏极欧姆接触，所述栅极肖特基接触。
  11. 一种高电子迁移率晶体管的制造方法，包括：
    于一衬底上生长一成核层；
    形成一第一金属化合物缓冲层；
    定义一势垒层的区域，生长由第一金属和第二金属的化合物构成的势垒层，使得所述第二金属在所述第一金属和第二金属的化合物中的组分不同；
    去光阻，形成源极及漏极；
    形成栅极，所述势垒层中，栅极与漏极之间区域的第二金属的组分不同，并且，从栅极端到漏极端第二金属的组分逐渐减小；
    在源极与栅极和漏极与栅极之间形成钝化层。
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