TWI461828B - 形成蝕刻罩之方法 - Google Patents

形成蝕刻罩之方法 Download PDF

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TWI461828B
TWI461828B TW095140484A TW95140484A TWI461828B TW I461828 B TWI461828 B TW I461828B TW 095140484 A TW095140484 A TW 095140484A TW 95140484 A TW95140484 A TW 95140484A TW I461828 B TWI461828 B TW I461828B
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hard mask
film
etching
photoresist
gas
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Gi Chung Kwon
Nae Eung Lee
Chang Ki Park
Chun Hee Lee
Duck Ho Kim
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Jusung Eng Co Ltd
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Description

形成蝕刻罩之方法
本發明係關於一種形成蝕刻罩之方法,且更特定而言係關於一種形成蝕刻罩之方法,此蝕刻罩具有用於對光阻形成薄膜圖案之硬罩的高蝕刻選擇性。
以往,為形成薄膜圖案,應用G線(436 nm)抗蝕劑及I線(365 nm)抗蝕劑或KrF(248 nm)抗蝕劑,且接著藉由使用罩來執行光微影製程以形成光阻圖案。隨後,藉由使用光阻圖案作為蝕刻罩來執行蝕刻製程,從而形成薄膜圖案。
然而,由於設備線寬度之減小及及光微影製程之限制,目前使用ArF(193 nm)抗蝕劑及具有80 nm或更小之線寬度之硬罩圖案來形成具有超細線寬度之薄膜圖案。
圖1A至1C為在概念上說明使用ArF(193 nm)抗蝕劑及硬罩圖案形成薄膜圖案之習知方法的問題之截面圖。
參看圖1A,將經圖案化之薄膜20形成於基板10上。硬罩膜30及光阻圖案40形成於薄膜20上。硬罩膜30A由氮化矽膜製成,而光阻圖案40由ArF抗蝕劑製成。此是因為抗蝕劑之厚度由於及光微影製程之限制而減小,使得僅僅現有之抗蝕劑不能用作有效的蝕刻阻擋層罩。因此,使硬罩膜30形成於抗蝕劑與薄膜之間,予以用作蝕刻罩。
參看圖1B及1C,為了將硬罩膜30用作蝕刻罩,藉由使用ArF光阻圖案40蝕刻硬罩膜30來圖案化硬罩膜30。隨後,藉由使用經圖案化之ArF光阻及硬罩膜30作為蝕刻罩來執行蝕刻製程以使下部薄膜圖案化。
然而,因為在圖案化習知硬罩膜30時,硬罩膜30對光阻圖案40之蝕刻選擇性較低且因此罩膜被腐蝕,所以存在之問題為未形成具有所需形狀之硬罩膜30的圖案。
氧氣(O2 )與以碳氟化合物為主之氣體(fluorocarbon-based gas)混合的混合氣體在當前用作用於蝕刻硬罩膜30的蝕刻氣體。然而,當使用上述混合氣體時,用作硬罩膜30之氮化矽膜對ArF光阻之蝕刻選擇性在1.5:1與4:1之間的範圍內。因此,導致的問題為當蝕刻硬罩膜30時,光阻亦被去除,或當蝕刻具有與光阻相同厚度之硬罩膜30時,光阻之耐久性被混合氣體削弱,且光阻塌陷。
亦即,應對硬罩膜30及薄膜20圖案化以使其每一者均具有與起始光阻圖案40之間的寬度A同樣之寬度,如圖1A所示。然而,如上文所述,因為硬罩膜30對光阻圖案40之蝕刻選擇性係較低,所以當蝕刻硬罩膜30時,光阻圖案40亦被去除。因此,形成具有大於所需寬度A之寬度B的硬罩膜30之圖案,如圖1B所示。隨後,在藉由使用具有上述較大寬度之硬罩膜30的圖案作為蝕刻罩執行蝕刻製程來圖案化薄膜20之情況下,導致的問題為形成具有比起始所需形狀之寬度更大的寬度之薄膜圖案。
另外,儘管未圖示,因為在硬罩膜30之圖案的蝕刻製程中光阻之耐久性被削弱,所以光阻圖案40塌陷。因此,導致的問題為下部硬罩膜30沒有被圖案化,且因此不可能圖案化薄膜20。
因此,設想本發明以解決先前技術中之上述問題。本發明之目的係提供一種形成蝕刻罩之方法,其能夠增加硬罩膜對光阻膜之蝕刻選擇性以用於形成193 nm或更小之細線寬度,且增強硬罩膜之蝕刻速率。
根據本發明之一態樣,提供一種形成蝕刻罩之方法,其包含以下步驟:在基板上沈積含有矽之硬罩膜;在該硬罩膜上沈積光阻;圖案化該光阻;及使用該光阻圖案作為罩且使用包括CHx Fy (x,y=1,2,3)氣體之蝕刻氣體蝕刻該硬罩膜。
較佳該蝕刻氣體為CH2 F2 氣體,且以10至100 sccm之流動速率注入。該蝕刻氣體可進一步包含H2 氣體。有效的是以20至150 sccm之流動速率注入H2 氣體。較佳該蝕刻氣體進一步包含Ar。
該硬罩膜可形成於氮化矽及氧化矽之至少任一者的單層或多層膜中。
較佳該光阻包含ArF(193 nm)、F2(157 nm)及EUV(遠紫外)抗蝕劑中之任一者。
另外,該方法較佳包含以下步驟:在硬罩膜與光阻圖案之間沈積抗反射塗層(ARC);及在蝕刻硬罩膜之前蝕刻ARC。
根據本發明之另一態樣,提供一種形成蝕刻罩以蝕刻基板上硬罩膜下之膜的方法,該基板具有順序形成於其上之含有矽的硬罩膜及經圖案化之光阻,該方法包含步驟:使用該光阻圖案作為罩且使用包括CHx Fy (x,y=1,2,3)氣體之蝕刻氣體蝕刻該硬罩膜。
此處,較佳該蝕刻氣體為CH2 F2 氣體,且以10至100 sccm之流動速率注入。該蝕刻氣體進一步包含以20至150 sccm之流動速率注入的H2 氣體亦較佳。有效的是該蝕刻氣體進一步包含以200至800 sccm之流動速率注入的Ar氣體。
較佳該光阻包含ArF(193 nm)、F2(157 nm)及EUV(遠紫外)抗蝕劑中之任一者。
另外,根據本發明之又一態樣,提供一種形成蝕刻罩以蝕刻基板上硬罩膜下之膜的方法,該基板具有順序形成於其上之含有矽的硬罩膜、ARC及經圖案化之光阻,該方法包含下列步驟:使用該光阻圖案作為罩蝕刻該ARC;及使用該光阻圖案及ARC作為罩且使用包括CHx Fy (x,y=1,2,3)氣體之蝕刻氣體來蝕刻硬罩膜。
此時,較佳該蝕刻氣體為CH2 F2 氣體,且以10至100 sccm之流動速率注入。有效的是該蝕刻氣體進一步包含以20至150 sccm之流動速率注入的H2 氣體。該蝕刻氣體進一步包含以200至800 sccm之流動速率注入的Ar氣體亦較佳。
較佳該光阻包含ArF(193 nm)、F2(157 nm)及EUV(遠紫外)抗蝕劑中之任一者。
另外,根據本發明之又一態樣,提供一種形成蝕刻罩以蝕刻基板上硬罩膜下之膜的方法,該基板具有順序形成於其上之含有矽的硬罩膜、ARC及經圖案化之光阻,該方法包含以下步驟:使用該光阻圖案作為罩蝕刻該ARC;及在該光阻圖案之表面聚合的同時,使用光阻圖案及ARC作為罩且使用一包括CHx Fy (x,y=1,2,3)氣體之蝕刻氣體來蝕刻該硬罩膜。
此處,較佳該蝕刻氣體為CH2 F2 氣體,且以10至100 sccm之流動速率注入。另外,較佳該蝕刻氣體進一步包含以20至150 sccm之流動速率注入的H2 氣體。
有效的是該光阻使用ArF(193 nm)、F2(157 nm)及EUV(遠紫外)抗蝕劑中之任一者。
下文中,將參看附圖詳細描述本發明之較佳實施例。然而,本發明並不限於下文將揭示之實施例,而是可建構為多種不同形式。僅為說明性目的及在熟習此項技術者完全理解本發明之範疇內提供該等實施例。所有附圖中,類似參考數字表示類似元件。
圖2A至2D為說明根據本發明實施例形成薄膜圖案之方法的截面圖。
如圖2A所示,薄膜120、硬罩膜130及抗反射塗層(ARC)140形成於基板110上。下文中,將光阻施加於ARC 140,且接著藉由使用罩執行及光微影製程來形成光阻圖案150。
此處,不僅可使用用於製造半導體設備之半導體基板作為基板110,亦可使用用於製造平板顯示設備之透明絕緣基板作為基板110。薄膜120不限於此,而是可為用於製造半導體設備或平板顯示設備之薄膜。
較佳地,使用相對於下部薄膜120具有高蝕刻選擇性之膜作為硬罩膜130。在此實施例中,氮化矽膜(SiN)用作硬罩膜130亦較佳。使用用於最小化光曝露製程中產生之光反射的膜,以10至50 nm之厚度施加ARC 140,以用於使光阻圖案150形成於ARC 140上。
隨後,藉由旋塗方法將用於193 nm或更小波長之光阻施加至ARC 140。較佳地,將ArF(193 nm)、F2(157 nm)及EUV(遠紫外)抗蝕劑中之任一者用作光阻。
在此實施例中,施加ArF抗蝕劑。藉由使用用於形成薄膜之罩執行及光微影製程來形成ArF抗蝕劑圖案150。亦即,藉由旋塗方法將ArF抗蝕劑施加至ARC,並接著將其載入193 nm光曝露儀器中。隨後,藉由使用用於圖案化薄膜之罩執行光曝露製程且接著執行顯影製程來形成ArF光阻圖案。
如圖2B所示,藉由使用ArF抗蝕劑圖案150作為蝕刻罩執行蝕刻製程來蝕刻經曝露之ARC 140。亦即,藉由使用CF4 /O2 /C4 F6 /Ar之混合氣體執行電漿蝕刻製程來去除ARC 140為有效的。此時,較佳分別以20至40 sccm、1至20 sccm、1至20 sccm及200至800 sccm之流動速率將CF4 、O2 、C4 F6 及Ar氣體供應至電漿蝕刻裝置。
接著,如圖2C所示,蝕刻硬罩膜130,其中藉由使用包括用於光阻圖案150之增強氣體的蝕刻氣體來執行硬罩膜130對光阻圖案150具有增強之蝕刻選擇性的蝕刻製程。
此處,較佳使用CHx Fy (x,y=1,2,3)及H2 之混合氣體作為蝕刻氣體。在使用混合氣體之情況下,ArF光阻圖案150之表面聚合成具有幾乎無窮大之蝕刻選擇性的聚合物151,在該無窮大的蝕刻選擇性下ArF光阻圖案150不會被去除,但僅下部硬罩膜130被蝕刻。
在此實施例中,CH2 F2 /H2 /Ar之混合氣體用作蝕刻氣體。另外,較佳在蝕刻製程中分別以10至200 sccm、20至200 sccm及100至1000 sccm之流動速率注入CH2 F2 、H2 及Ar氣體。
將上述蝕刻製程描述如下:如上文所述,將具有形成於硬罩膜130上之光阻圖案150的基板110載入圖3所示之蝕刻儀器200的腔室中,使得基板110就位於基板支撐構件210上。較佳地,使用靜電夾盤作為基板支撐構件210。另外,較佳在蝕刻製程中將靜電夾盤之溫度維持在攝氏-10至80度。將蝕刻儀器200(亦即,腔室)中之壓力維持在1至500 mTorr。隨後,將CH2 F2 、H2 及Ar氣體注入蝕刻儀器200,且接著藉由產生電漿來進行蝕刻製程。
較佳地,蝕刻儀器200對基板支撐構件210施加不同之高頻功率,如圖3(a)所示。此時,第一、第二及第三高頻功率源220、230及240較佳地分別施加400 KHz至10 MHz、10至30 MHz及10至100 MHz之頻率的電壓。另外,蝕刻儀器200可對基板支撐構件210施加不同的高頻功率,並對蝕刻儀器200之上部部分中的天線250施加頻率功率,如圖3(b)所示。亦即,第一及第二高頻功率源220及230對用作下部電極之基板支撐構件210施加400 KHz至10 MHz及10至30 MHz之頻率的電壓,而第三高頻功率源240對提供於基板支撐構件210上方之天線250施加10至100 MHz之頻率的電壓。
上文中,第一及第二高頻功率源220及230較佳地分別施加100至400 W及300至600 W之電功率。
可使用上述的蝕刻氣體及蝕刻儀器200來調整蝕刻速率及蝕刻選擇性。亦即,可能獲得在蝕刻硬罩膜130時光阻圖案150決不會被去除的蝕刻選擇性。
圖4為說明根據CH2 F2 氣體流動速率的改變之蝕刻速率的曲線圖,且圖5為說明根據H2 氣體流動速率的改變之蝕刻速率的曲線圖。圖6為具有根據本發明實施例蝕刻之硬罩膜的基板之平面照片,且圖7及8為具有根據本發明實施例蝕刻之硬罩膜的基板之截面照片。
圖4說明在H2 氣體之流動速率維持在80 sccm的狀態下改變CH2 F2 氣體之流動速率時,硬罩膜130之蝕刻速率改變(見曲線a)、光阻圖案150之蝕刻速率改變(見曲線b)及硬罩膜130對光阻圖案150之蝕刻選擇性改變(見曲線c)。此時,圖4(a)、(b)及(c)分別說明第一高頻功率源220之電功率設置為100、150及200 W時的改變。此處,相同地維持其它製程條件。自圖4之曲線可瞭解,在已注入H2 氣體之狀態下增加CH2 F2 氣體的流動速率時,硬罩膜130之蝕刻速率減小,但硬罩膜130對光阻圖案150之蝕刻選擇性增加至無窮大。另外,亦可瞭解蝕刻速率及蝕刻選擇性係根據所施加電源之功率而改變的。
另外,圖5說明在CH2 F2 氣體之流動速率維持在20 sccm的狀態下改變H2 氣體之流動速率時,硬罩膜130之蝕刻速率改變(見曲線a)、光阻圖案150之蝕刻速率改變(見曲線b)及硬罩膜130對光阻圖案150之蝕刻選擇性改變(見曲線c)。此時,圖5(a)、(b)及(c)分別說明第一高頻功率源220之電功率如上文所述設定為100、150及200 W時的改變。自圖5之曲線可瞭解,在已注入CH2 F2 氣體之狀態下增加H2 氣體之流動速率時,硬罩膜130對光阻圖案150之蝕刻選擇性自接近無窮大之值逐漸減小,但硬罩膜130之蝕刻速率增加。
回顧兩幅曲線圖,當使用包括CH2 F2 及H2 氣體之混合氣體執行蝕刻時,SiN膜(亦即,硬罩膜130)之蝕刻速率增加,而ArF光阻圖案150之蝕刻速率為負值,使得蝕刻選擇性變為接近無窮大的值。此是因為在將CH2 F2 及H2 氣體供應至蝕刻儀器時,聚合物151產生於ArF光阻圖案150之表面上以包圍其表面。
因此,不會產生ArF光阻圖案150之塌陷或蝕刻,從而可形成具有所需圖案之硬罩膜130,且可增強硬罩膜130之蝕刻速率,如圖6至8之照片中所示。在上文中,圖7為在已執行蝕刻約1分鐘之後的照片,且圖8為已執行蝕刻約3分鐘之後的照片。亦即,圖6(a)、7(a)及8(a)為已藉由分別以20、60及500 sccm將CH2 F2 、H2 及Ar氣體注入圖3之電漿蝕刻儀器中來蝕刻硬罩膜130之後的FE-SEM照片,且圖6(b)、7(b)及8(b)為已藉由分別以20、100及500 sccm將CH2 F2 、H2 及Ar氣體注入圖3之電漿蝕刻儀器中來蝕刻硬罩膜130之後的FE-SEM照片。如照片中所示,可瞭解用於硬罩膜130之蝕刻製程未改變硬罩膜130頂部上之ArF光阻圖案150,且根據本發明藉由使用包括CH2 F2 及H2 氣體的混合氣體使硬罩膜130圖案化而具有與光阻圖案150相同之形狀。
此是因為CH2 F2 及H2 氣體被引入蝕刻儀器並接著借助於電漿而活化,經活化之活化基團對ArF光阻圖案150反應,使聚合物151形成於其表面上。因此,此聚合物151用作阻擋層以用於防止藉由CH2 F2 及H2 氣體而去除ArF光阻圖案150,從而可防止ArF光阻圖案150之蝕刻。聚合物151亦用以硬化ArF光阻圖案150之外表面,從而防止ArF光阻圖案150之塌陷。此時,產生之聚合物151為CF2 (z=0.1至0.5)。在CH2 F2 氣體之流動速率增加時,聚合物151內碳(C)的量及聚合物151的厚度相對增加,使得抵抗ArF抗蝕劑之蝕刻的耐久性增加。另一方面,因為在將CH2 F2 及H2 氣體一起添加時產生例如HCN之蝕刻反應劑,所以活化了增加SiN硬罩膜130中N元素之去除的反應,從而繼續硬罩膜130之蝕刻。在此情況下,藉由蝕刻,ArF抗蝕劑被去除而硬罩膜130被連續去除,從而可獲得接近無窮大之蝕刻選擇性。然而,若H2 氣體之流動速率過度增加,ArF抗蝕劑圖案150上聚合物151之產生速率就減小,使得ArF抗蝕劑以及硬罩膜之蝕刻速率亦增加,且蝕刻選擇性具有相對較小的值。因此,為獲得接近無窮大的值之蝕刻選擇性,CH2 F2 及H2 氣體之流動速率的適當組合變為一個重要的製程參數。
如圖2d所示,藉由使用經圖案化之硬罩膜130及ArF光阻圖案150作為蝕刻罩之蝕刻製程來去除薄膜120的一部分,且因此使薄膜120圖案化。接著,去除ArF光阻圖案150及硬罩膜130以形成薄膜圖案。
上述描述中已描述用於薄膜之一般圖案化方法。
根據本實施例之圖案化薄膜的方法可應用於圖案化半導體設備之設備隔離膜及閘電極與閘極線,以及包括源極及汲極線之金屬導線。
亦即,使用氮化矽膜將一硬罩膜形成於半導體基板上,且將光阻圖案形成於其頂部上。隨後,使用包括CH2 F2 、H2 及Ar氣體之混合氣體來蝕刻硬罩膜,且因此暴露半導體基板之一部分。接著,蝕刻半導體基板之暴露部分以藉由使用硬罩膜及光阻圖案作為蝕刻罩執行蝕刻製程來形成槽。隨後,用HDP氧化膜填充該槽,使用硬罩膜作為停止膜(stop film)來執行平坦化製程,且接著去除硬罩膜,由此形成設備隔離膜。將顯而易見,上述方法只是用於形成半導體設備之槽的實施例。因此,本發明不限於此,而是可進行各種修改。
同時,將閘極氧化膜及導電膜按順序形成於半導體基板上,且將硬罩膜及光阻圖案形成於其上。使用包括CH2 F2 、H2 及Ar氣體之混合氣體來蝕刻硬罩膜,從而暴露導電膜之一部分。隨後,藉由使用硬罩膜作為蝕刻罩執行蝕刻製程來去除導電膜之暴露部分,因此形成閘電極與閘極線。將顯而易見,上述描述只是用於形成用於半導體設備之閘電極及閘極線的實施例。因此,本發明不限於以上實施例,而是可進行各種修改。
另外,閘電極及設備隔離膜可同時形成。亦即,將閘極氧化膜、導電膜及硬罩膜按順序形成於半導體基板上,且接著將光阻圖案形成於其頂部上。使用包括CH2 F2 、H2 及Ar氣體之混合氣體來蝕刻硬罩膜,且接著藉由使用硬罩膜作為蝕刻罩執行蝕刻製程來蝕刻導電膜之一部分、閘極氧化膜及基板以形成槽。接著,在用HDP氧化膜填充該槽之後,藉由使用導電膜作為停止膜執行平坦化製程來形成閘電極及閘極線,且同時形成設備隔離膜。
另外,層間絕緣膜形成於基板上,該基板具有源極及汲極電極或上面形成有下部金屬布線,硬罩膜形成於層間絕緣膜上,且接著光阻圖案形成於硬罩膜之頂部上。接著,在使用包括CH2 F2 、H2 及Ar氣體之混合氣體蝕刻硬罩膜之後,藉由使用硬罩膜作為蝕刻罩執行蝕刻製程來蝕刻層間絕緣膜,以形成暴露下部源極電極、汲極電極或下部金屬布線之接觸孔,且硬罩膜被去除。隨後,形成填充該接觸孔之導電膜,且接著藉由圖案化層間絕緣膜上之導電膜來形成金屬布線。儘管在上述描述中已簡要描述藉由單鑲嵌製程形成金屬布線之實施例,但本發明不限於此。亦即,可藉由各種修改來形成金屬布線。
因而,視下部薄膜之形狀而定,本發明可應用於製造半導體設備之整個製程。
儘管上文中已描述使用硬罩膜形成單個SiN膜,但本發明不限於此。亦即多層膜可用作硬罩膜。換言之,可使用具有至少兩層(其中形成有氮化矽及/或氧化物膜)之膜作為硬罩膜。
如上文所述,根據本發明,在蝕刻用於193 nm或更小波長之光阻圖案下之硬罩膜時,可使用包括CH2 F2 及H2 氣體之混合氣體來增加硬罩膜對光阻圖案之蝕刻選擇性。
本發明並不限於上述實施例,而是可建構為不同形式。亦即,僅為說明性目的在熟習此項技術者完全理解本發明之範疇內提供該等實施例。另外,應在由隨附申請專利範圍所界定之本發明的範疇內理解本發明之範疇。
10...基板
20...薄膜
30...硬罩膜
40...光阻圖案
110...基板
120...薄膜
130...硬罩膜
140...抗反射塗層
150...光阻圖案
151...聚合物
200...蝕刻儀器
210...基板支撐構件
220...高頻功率源
230...高頻功率源
240...高頻功率源
250...天線
a...曲線
A...寬度
b...曲線
B...寬度
c...曲線
圖1A至1C為概念上說明使用ArF(193 nm)抗蝕劑及硬罩圖案形成薄膜圖案之習知方法的問題之截面圖;圖2A至2D為說明根據本發明實施例之形成薄膜圖案的方法之截面圖;圖3為根據本發明之用於蝕刻硬罩膜的裝置之概念圖;圖4為說明根據CH2 F2 氣體流動速率之改變的蝕刻速率之曲線圖;圖5為說明根據H2 氣體流動速率之改變的蝕刻速率之曲線圖;圖6為具有根據本發明實施例而蝕刻之硬罩膜的基板之平面照片;及圖7及8為具有根據本發明實施例而蝕刻之硬罩膜的基板之截面照片。
110...基板
120...薄膜
130...硬罩膜
140...抗反射塗層
150...光阻圖案
151...聚合物

Claims (7)

  1. 一種形成蝕刻罩之方法,其包含以下步驟:在基板上沈積包含SiN之硬罩膜;在該硬罩膜上沈積光阻,該光阻包含ArF(193nm)抗蝕劑;圖案化該光阻;及使用該光阻圖案作為罩且使用包括以20至40sccm之流動速率注入之CH2 F2 氣體及以40至80sccm之流動速率注入之H2 氣體之蝕刻氣體來蝕刻該硬罩膜,以使得該硬罩膜相對於該光阻之蝕刻選擇性接近無窮大。
  2. 如請求項1之方法,其中該蝕刻氣體進一步包含Ar。
  3. 如請求項1之方法,其中該硬罩膜形成於單層或多層膜中,且該硬罩膜進一步包含氧化矽。
  4. 如請求項1之方法,其進一步包含以下步驟:在該硬罩膜與該光阻圖案之間沈積一抗反射塗層(ARC);及在蝕刻該硬罩膜之前蝕刻該ARC。
  5. 一種形成蝕刻罩以蝕刻在基板上硬罩膜下之一膜的方法,該基板具有順序形成於其上之包含SiN的該硬罩膜及一經圖案化之光阻,該經圖案化之光阻包含一ArF(193nm)抗蝕劑,該方法包含以下步驟:使用該光阻圖案作為罩且使用包括以20至40sccm之流動速率注入之CH2 F2 氣體及以40至80sccm之流動速率注入之H2 氣體之蝕刻氣體來蝕刻該硬罩膜,以使得該硬罩 膜相對於該光阻之蝕刻選擇性接近無窮大。
  6. 如請求項5之方法,其中該蝕刻氣體進一步包含以200至800sccm之流動速率注入的Ar氣體。
  7. 一種形成蝕刻罩以蝕刻在基板上硬罩膜下之一膜的方法,該基板具有按順序形成於其上之包含SiN的該硬罩膜、一抗反射塗層(ARC)及一經圖案化之光阻,該經圖案化之光阻包含一ArF(193nm)抗蝕劑,該方法包含以下步驟:使用該光阻圖案作為罩來蝕刻該ARC;及在該光阻圖案之一表面被聚合時使用該光阻圖案及ARC作為罩,且使用包括以20至40sccm之流動速率注入之CH2 F2 氣體及以40至80sccm之流動速率注入之H2 氣體之蝕刻氣體來蝕刻該硬罩膜,以使得該硬罩膜相對於該光阻之蝕刻選擇性接近無窮大。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100836069B1 (ko) * 2007-06-29 2008-06-09 세메스 주식회사 기판 처리 장치
US8298958B2 (en) * 2008-07-17 2012-10-30 Lam Research Corporation Organic line width roughness with H2 plasma treatment
CN103065946B (zh) * 2011-10-18 2016-04-13 中芯国际集成电路制造(上海)有限公司 一种光刻方法
US8748989B2 (en) * 2012-02-28 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistors
CN110249410B (zh) * 2017-02-01 2023-07-04 应用材料公司 用于硬掩模应用的硼掺杂碳化钨

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961147A (ja) * 1982-09-30 1984-04-07 Toshiba Corp 半導体装置の製造方法
US5480051A (en) * 1993-05-27 1996-01-02 Siemens Aktiengesellschaft Method for the anisotropic etching of an aluminiferous layer
JPH1171363A (ja) * 1997-06-25 1999-03-16 Wako Pure Chem Ind Ltd レジスト組成物及びこれを用いたパターン形成方法並びにレジスト剤用架橋剤
US6300251B1 (en) * 2000-02-10 2001-10-09 Chartered Semiconductor Manufacturing Ltd. Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon
JP2002000444A (ja) * 2000-06-20 2002-01-08 Zojirushi Corp 炊飯ジャーの蓋
US20020096487A1 (en) * 1997-12-31 2002-07-25 Timothy R. Demmin Method of etching and cleaning using fluorinated carbonyl compounds
US6579809B1 (en) * 2002-05-16 2003-06-17 Advanced Micro Devices, Inc. In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric
US6583065B1 (en) * 1999-08-03 2003-06-24 Applied Materials Inc. Sidewall polymer forming gas additives for etching processes
US20040072443A1 (en) * 2002-10-11 2004-04-15 Lam Research Corporation Method for plasma etching performance enhancement
US20040074869A1 (en) * 2002-10-18 2004-04-22 Applied Materials, Inc. Fluorine free integrated process for etching aluminum including chamber dry clean
US6743725B1 (en) * 2001-08-13 2004-06-01 Lsi Logic Corporation High selectivity SiC etch in integrated circuit fabrication
WO2004097923A1 (ja) * 2003-04-30 2004-11-11 Fujitsu Limited 半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4910122A (en) * 1982-09-30 1990-03-20 Brewer Science, Inc. Anti-reflective coating
DE3420347A1 (de) * 1983-06-01 1984-12-06 Hitachi, Ltd., Tokio/Tokyo Gas und verfahren zum selektiven aetzen von siliciumnitrid
US5438006A (en) * 1994-01-03 1995-08-01 At&T Corp. Method of fabricating gate stack having a reduced height
JPH07335612A (ja) * 1994-06-13 1995-12-22 Hitachi Ltd 半導体集積回路装置の製造方法
US5858847A (en) * 1997-03-28 1999-01-12 Chartered Semiconductor Manufacturing, Ltd. Method for a lightly doped drain structure
EP0887706A1 (en) * 1997-06-25 1998-12-30 Wako Pure Chemical Industries Ltd Resist composition containing specific cross-linking agent
US5986344A (en) * 1998-04-14 1999-11-16 Advanced Micro Devices, Inc. Anti-reflective coating layer for semiconductor device
US6841483B2 (en) * 2001-02-12 2005-01-11 Lam Research Corporation Unique process chemistry for etching organic low-k materials
US20060084243A1 (en) * 2004-10-20 2006-04-20 Ying Zhang Oxidation sidewall image transfer patterning method
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20060166416A1 (en) * 2005-01-27 2006-07-27 International Business Machines Corporation Addition of ballast hydrocarbon gas to doped polysilicon etch masked by resist
JP4476171B2 (ja) * 2005-05-30 2010-06-09 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961147A (ja) * 1982-09-30 1984-04-07 Toshiba Corp 半導体装置の製造方法
US5480051A (en) * 1993-05-27 1996-01-02 Siemens Aktiengesellschaft Method for the anisotropic etching of an aluminiferous layer
JPH1171363A (ja) * 1997-06-25 1999-03-16 Wako Pure Chem Ind Ltd レジスト組成物及びこれを用いたパターン形成方法並びにレジスト剤用架橋剤
US20020096487A1 (en) * 1997-12-31 2002-07-25 Timothy R. Demmin Method of etching and cleaning using fluorinated carbonyl compounds
US6583065B1 (en) * 1999-08-03 2003-06-24 Applied Materials Inc. Sidewall polymer forming gas additives for etching processes
US6300251B1 (en) * 2000-02-10 2001-10-09 Chartered Semiconductor Manufacturing Ltd. Repeatable end point method for anisotropic etch of inorganic buried anti-reflective coating layer over silicon
JP2002000444A (ja) * 2000-06-20 2002-01-08 Zojirushi Corp 炊飯ジャーの蓋
US6743725B1 (en) * 2001-08-13 2004-06-01 Lsi Logic Corporation High selectivity SiC etch in integrated circuit fabrication
US6579809B1 (en) * 2002-05-16 2003-06-17 Advanced Micro Devices, Inc. In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric
US20040072443A1 (en) * 2002-10-11 2004-04-15 Lam Research Corporation Method for plasma etching performance enhancement
US20040074869A1 (en) * 2002-10-18 2004-04-22 Applied Materials, Inc. Fluorine free integrated process for etching aluminum including chamber dry clean
WO2004097923A1 (ja) * 2003-04-30 2004-11-11 Fujitsu Limited 半導体装置の製造方法

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