TWI457982B - 半導體裝置、電源供應裝置、放大器及半導體裝置之製造方法 - Google Patents
半導體裝置、電源供應裝置、放大器及半導體裝置之製造方法 Download PDFInfo
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- TWI457982B TWI457982B TW101103741A TW101103741A TWI457982B TW I457982 B TWI457982 B TW I457982B TW 101103741 A TW101103741 A TW 101103741A TW 101103741 A TW101103741 A TW 101103741A TW I457982 B TWI457982 B TW I457982B
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims description 98
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 33
- 239000011203 carbon fibre reinforced carbon Substances 0.000 claims description 15
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 14
- 229910052799 carbon Inorganic materials 0.000 claims description 10
- 229910002704 AlGaN Inorganic materials 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 4
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 description 71
- 230000007704 transition Effects 0.000 description 22
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 18
- 239000002245 particle Substances 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 9
- 238000012546 transfer Methods 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 238000000926 separation method Methods 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000000875 corresponding effect Effects 0.000 description 5
- 229910002804 graphite Inorganic materials 0.000 description 5
- 239000010439 graphite Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010891 electric arc Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 239000003960 organic solvent Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910003468 tantalcarbide Inorganic materials 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 238000001771 vacuum deposition Methods 0.000 description 4
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 3
- 239000010432 diamond Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 229910052684 Cerium Inorganic materials 0.000 description 2
- 239000004821 Contact adhesive Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 2
- 230000005274 electronic transitions Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000007858 starting material Substances 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- -1 carbon ions Chemical class 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32055—Arc discharge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32357—Generation remote from the workpiece, e.g. down-stream
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32422—Arrangement for selecting ions or species in the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/3266—Magnetic control means
- H01J37/32669—Particular magnets or magnet arrangements for controlling the discharge
-
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28264—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
-
- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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Description
本發明係關於半導體裝置、電源供應裝置、放大器及半導體裝置之製造方法的範例。
包含於氮化物半導體之GaN、AlN及InN或包含混合有GaN、AlN及InN等等晶體之材料係具有寬頻帶間隙(band gap)並用於高輸出電子裝置或短波長光發射裝置。場效電晶體(FET),例如高電子移動率電晶體(HEMT)係用於高輸出電子裝置。包含氮化物半導體之HEMT係用於高輸出高效率放大器、或高電源切換裝置等。
具有高汲極崩潰電壓和閘極崩潰電壓之HEMT可包含含有即將成為閘極絕緣膜之絕緣膜的金屬絕緣半導體(MIS)結構。由於所述MIS結構,產生了一種適合用於電源應用之半導體裝置。
相關技術揭露於日本早期公開專利申請案第2002-359256號、日本早期公開專利申請案第2008-218479號等等。
由於導通狀態電阻(on-resistance)、常關操作(normally-off operation)的減少、或切換元件的崩潰電壓的增加,可提供使用電晶體用於電源應用之高效率切換元件。像這樣的切換元件可穩定實施切換操作。
需要一種穩定地實施切換操作之半導體裝置。
根據所述具體實施例的一面向,半導體裝置包含:形成於基板上之半導體層;形成於該半導體層上之絕緣膜;形成於該絕緣膜上之電極,其中,該絕緣膜包含含碳的非晶膜。
根據上述半導體裝置,可穩定實施切換操作,以便可提供高可靠度之半導體裝置。
本發明的其他優點和新穎特徵將會一部分從以下敘述提出,而一部分會對於所述技術領域中具通常知識者在審視本發明或實踐而了解本發明之後更加顯而易見。
第1圖說明例示性半導體裝置。第1圖所述之半導體裝置可不穩定地實施切換操作。第1圖所述之半導體裝置包含層壓在含矽基板1上之緩衝層2、電子過渡層(electron transit layer)3、間隔層4、電子供應層5、蓋層6、及形成於該蓋層6上之絕緣膜7。所述電子過渡層3、間隔層4、電子供應層5及蓋層6可藉由金屬有機氣相磊晶(MOVPE)方法而形成。為了磊晶生長所述電子過渡層3等,緩衝層2可形成於基板1上。藉由基板1上之緩衝層2,所述電子過渡層3等係磊晶生長於緩衝層2上。
所述電子過渡層3可為具有厚度約3μm之i-GaN。所述間隔層4可為具有厚度約5nm之i-AlGaN。所述電子供應層5可為具有厚度約5nm之n-AlGaN。n-AlGaN可以濃度5×1018
cm-3
的矽(Si)作為雜質元素來摻雜。所述蓋層6可為具有厚度約10nm之n-GaN。n-GaN可以濃度5×
1018
cm-3
的矽(Si)作為雜質元素來摻雜。在電子過渡層3接近電子供應層5的一側產生二維電子雲(2DEG)3a。所述絕緣膜7可對應於閘極絕緣膜。所述絕緣膜7包含具有藉由原子層沈積(ALD)方法所形成之厚度約20nm之氧化鋁之膜。
第2A及2B圖說明半導體元件之例示性測量。於第2圖中,包含汞之陽極電極8和陰極電極9設置在絕緣膜7上。可測量陽極電極8與陰極電極9之間的電容。所述陽極電極8可為具有直徑約500μm的圓盤形狀。所述陰極電極9可為具有內徑約1500μm和外徑約2500μm的環形。可配置陰極電極9以使得陰極電極9的中央與陽極電極8的中央相配。陰極電極9可為接地,以便能達到接地電位。第2A圖說明半導體元件的俯視圖。第2B圖說明沿著第2A圖的Ⅱ B-Ⅱ B虛線之剖面圖。
第3圖說明施加電壓與電容之間的例示關係。例如,第3圖可說明當施加在陽極電極8的電壓有變化時,在陽極電極8與陰極電極9之間測量到的電容。例如,將陰極電極9接地,並施加一給定電壓(疊加有100kHz和25mV之交流成分)至陽極電極8,則測量到所述電容。
如第3圖所示,當施加於陽極電極8的電壓自-30V逐步增加至10V時,電容大約在電壓為-7V時自0突然增加。當電壓進一步增加時,電容為實質上常數而沒有劇烈變化。然而,當電壓達到約0V時,電容增加。之後,電容隨著施加電壓的增加而增加,並逐漸接近某一值。當施加
於陽極電極8的電壓自10V逐步下降至-30V時,電容隨著施加電壓的減少而下降。然而,當電壓達到接近7V時,電容成為實質上常數。當電壓下降至0V時,電容可能不改變。之後,隨著施加電壓的進一步下降,當電壓已通過0時電容減少,且當電壓達到接近-1.5V時電容成為0,之後,當電壓下降,電容仍為0而沒有變化。例如,當第1圖所示之半導體元件之絕緣膜7包含氧化鋁時,於電壓增加時期施加電壓與電容之間的關係以及於電壓減少時期施加電壓與電容之間的關係係彼此不相同。
當施加電壓從低電壓開始增加時,空乏層厚度減少,而於2DEG 3a形成於電子過渡層3時會產生電容,然後電容會劇烈增加。當施加電壓自高電壓開始減少時,空乏層厚度增加,電容隨著2DEG 3a的減少而下降。由於形成於絕緣膜7中的陷阱能階(trap level)所捕捉的電子等會影響2DEG 3a之分佈,所以施加電壓增加時的曲線可幾乎被施加電壓減少時偏移的曲線重疊。例如,陷阱能階形成於絕緣膜7中,以至於電子等被捕捉,電容將被偵測到有變化。當施加實質上相同的電壓時,於電壓增加時所偵測到的電容與電壓減少時所偵測到的電容可不相同。
當電壓與電容之間的關係取決於先前施加電壓的過程而變化時,可能無法達到穩定的切換操作,以至於半導體裝置的可靠性下降。於電壓增加時期電容曲線與於電壓減少時期電容曲線之間的偏移量可被稱為閾值電壓變化範圍。舉例而言,當第1圖所示之半導體裝置的絕緣膜7包
含氧化鋁時,其閾值電壓變化範圍可為大約5.4V。
例如,當絕緣膜7的氧化鋁膜為化合物的非晶膜時,可形成陷阱能階。當絕緣膜7包含非晶膜等化合物(如氧化物或氮化物)時,可形成陷阱能階。
第4A圖至4C圖說明例示性絕緣膜。第4A圖說明具有厚度約20nm且包含氧化鋁之絕緣膜7。第4B和4C圖說明包含有別於氧化物和氮化物材料之絕緣膜。例如,第4B圖所示之絕緣膜7a可包含非晶碳膜。第4C圖所示之絕緣膜7b說明在絕緣膜7b中的非晶碳膜和氧化鋁膜為層疊的。於第4B圖所述之絕緣膜7a中,形成有約20nm的非晶碳膜。於第4C圖所述之絕緣膜7b中,藉由ALD方法形成約10nm的氧化鋁膜,而接著形成有約10nm的非晶碳膜。所述非晶碳膜可為包含碳作為主要組成之非晶膜,且可藉由過濾式陰極電弧(FCA)(其為一種電弧氣相沈積方法)形成非晶碳膜。
第5圖說明非晶碳膜的厚度與閾值電壓變化範圍之間的例示性關係。當非晶碳膜的厚度變大時,閾值電壓變化範圍變小。當絕緣膜為非晶碳膜時,閾值電壓變化範圍可實質上變成零。
例如,當絕緣膜包含非晶碳膜時,閾值電壓變化範圍變小。當整體絕緣膜為非晶碳膜時,閾值電壓變化範圍可實質上變成零。當對應於閘極絕緣膜的絕緣膜包含非晶碳膜時,可穩定實施切換操作。例如,當對應於閘極絕緣膜的絕緣膜係部份或整體為非晶碳膜時,可穩定實施切換操
作,以至於可提供高穩定性之半導體裝置。
第6圖說明例示性半導體裝置。第6圖所述之半導體裝置可為HEMT。半導體裝置包含形成在基板10上之緩衝層20,包含半導體等和含有藉由磊晶生長層疊在緩衝層20上的半導體之電子過渡層21、電子供應層22、及蓋層23。在蓋層23上形成有絕緣膜30。在絕緣膜30上形成有閘極電極41。源極電極42和汲極電極43係耦接至電子過渡層21。在暴露的絕緣膜30上形成有包含絕緣體之保護膜50。
基板10可包含矽基板、碳化矽基板、藍寶石(Al2
O3
)基板等。例如,基板10為矽基板且緩衝層20形成於該基板上。當基板10包含其他材料時,可能不會形成緩衝層20。電子過渡層21可為i-GaN,電子供應層22可為n-AlGaN,而蓋層23可為n-GaN。在電子供應層22接近電子過渡層21的一側形成有二維電子雲(2DEG)21a。在電子過渡層21和電子供應層22之間可形成間隔層(未圖示)。
閘極電極41、源極電極42、及汲極電極43可包含金屬材料。即將成為閘極絕緣膜之絕緣膜30可包含厚度為20nm的非晶碳膜。保護膜50可包含藉由電漿ALD所形成之氧化鋁(Al2
O3
)膜。
作為絕緣膜30之非晶碳膜可為包含碳作為主要組成物之非晶膜,且可稱之為類鑽碳(DLC)。非晶碳膜具有高密度、高絕緣性質及高表面平滑。可減少具有高絕緣特性、高密度等之非晶碳膜中的含氫量,則非晶碳膜可為類鑽膜。例如,非晶碳膜可具有高的膜密度且在非晶碳膜中的
碳-碳鍵結中sp3含量可高於sp2含量。處於碳-碳鍵結中sp3含量可高於sp2含量之狀態之非晶碳膜變成接近高密度鑽石之狀態之膜。因此,可減少陷阱能階等的形成而閾值電壓變化範圍可能變小。例如,包含非晶碳膜之絕緣膜30可穩定實施切換操作。
碳-碳鍵結包含鍵結方式sp2和sp3。石墨是以碳-碳鍵結sp2形成,而鑽石是以碳-碳鍵結sp3形成。當非晶碳進一步為類鑽膜時,sp3鍵結含量可高於sp2鍵結含量。例如,碳-碳鍵結含量可為sp2≦sp3。
第7圖說明碳-碳鍵結比例與膜密度或電漿峰值之間的例示性關係。如第7圖所示,碳-碳鍵結sp3比例和非晶碳膜的膜密度具有關聯性,且當碳-碳鍵結sp3比例變高時,膜密度亦變高。碳-碳鍵結sp3比例和非晶碳膜的電漿峰值具有關聯性,且當碳-碳鍵結sp3比例變高時,電漿峰值亦變高。例如,非晶碳膜的碳-碳鍵結sp3比例為50%或更多。非晶碳膜的鍵結比例sp3係高於鍵結比例sp2且難以包含氫,並具有2.6g/cm3
或更多的膜密度以及28eV或更高的電漿峰值。可基於形成在矽基板上的非晶碳膜中藉由拉賽福(Rutherford)背向散射光譜學所獲得之結果以及藉由穿透電子顯微鏡(TEM)量測之剖面長度所獲得的膜厚度來計算膜密度。
當非晶碳膜的膜密度為2.6g/cm3
或更多且電漿峰值為28eV或更高時,可藉由電弧氣相沈積方法的FCA方法來形成非晶碳膜。例如,藉由FCA方法所形成之非晶碳膜的
膜密度可為3.2g/cm3
。鑽石的密度可為3.56g/cm3
。非晶碳膜的膜密度可為2.6g/cm3
或更多以及3.56g/cm3
或更少。藉由FCA方法所形成之非晶碳膜的氫含量係低於藉由CVD所形成之非晶碳膜的氫含量。藉由FCA方法所形成之非晶碳膜的氫含量可為1atm%或更低。藉由化學氣相沈積(CVD)所形成之含氫的非晶碳膜的最高膜密度可低於約2.6g/cm3
。
第8圖說明例示性電漿峰值。第8圖說明藉由FCA方法或CVD方法所形成之非晶碳膜之電漿峰值。藉由FCA方法所形成之非晶碳膜之電漿峰值8A可為大約30eV以及為28eV或更高。藉由CVD方法所形成之非晶碳膜之電漿峰值8B可為大約23eV以及可低於28eV。藉由FCA方法所形成之非晶碳膜之電漿峰值可為28eV或更高。絕緣膜30可為藉由FCA方法所形成之非晶碳膜。非晶碳膜之碳-碳鍵結可為sp2≦sp3,而密度可為2.6g/cm3
或更多及3.56 g/cm3
或更少,且電漿峰值可為28eV或更高。
形成作為絕緣膜30之非晶碳膜的厚度可為2nm或更多以及200nm或更少,例如,10nm或更多及30nm或更少。當非晶碳膜覆蓋整個表面時,非晶碳膜的厚度可至少數個原子層或更多。非晶碳膜的厚度低於2nm時可能無法覆蓋整個表面。舉例而言,非晶碳膜的厚度可為如第5圖所示之10nm或更多。因為非晶碳膜的壓力是高的,會由於在厚度超過30nm的非晶碳膜中之應力,而可能發生膜分離。非晶碳膜的厚度可為30nm或更少。
第9A至9E圖說明用於製造半導體裝置之例示性方法。
如第9A圖所示,緩衝層20係形成在基板10上以及包含電子過渡層21、電子供應層22、蓋層23等之半導體層係藉由金屬有機氣相磊晶生長(MOVPE)等磊晶生長而形成在緩衝層20上。基板10可為包含矽、碳化矽、藍寶石(Al2
O3
)等之基板。在基板10上,為了磊晶生長電子過渡層21等可形成緩衝層20。例如,緩衝層20可為厚度約0.1μm的無摻雜i-AlN層。所述電子過渡層21可為厚度約3μm的無摻雜i-GaN。所述電子供應層22可為厚度約30nm的n-Al0.25
Ga0.75
N層,其可以濃度為5×1018
cm-3
的矽作為雜質元素進行摻雜。所述蓋層23可為具有厚度約10nm之n-GaN層,其可以濃度5×1018
cm-3
的矽作為雜質元素來進行摻雜。所述半導體層可藉由晶體生長,如分子束磊晶(MBE)所形成。
如第9B圖所示,形成源極電極42和汲極電極43。例如,光阻層鋪設在蓋層23上,接著以曝光設備曝光並顯影,因而在即將形成源極電極42和汲極電極43之區域形成具有開口部之阻劑圖案(未圖示)。實施乾蝕刻,如使用氯氣的反應性離子蝕刻(RIE)以移除在無形成阻劑圖案的區域中之蓋層23和電子供應層22,以至於暴露電子過渡層21的表面。於乾蝕刻中,引入約30 sccm的氯氣進入腔室中作為蝕刻氣體,腔室中的壓力設定為約2 Pa並施加20W的RF功率。藉由真空沈積等形成包含Ta/Al層疊膜
等之金屬膜,且形成在該阻劑圖案上的金屬膜係和該阻劑一起被剝離並藉由浸入有機溶劑等而移除。源極電極42和汲極電極43係形成在無形成該阻劑圖案之區域。於剝離之後,實施例如溫度550℃之熱處理,則達到歐姆接觸。乾蝕刻中的阻劑圖案可用於剝離中的阻劑圖案,然而,可分別執行乾蝕刻和剝離。
如第9C圖所示,對應於閘極絕緣膜之絕緣膜30係形成在蓋層23上。可藉由FCA方法成長非晶碳膜而形成絕緣膜30。例如,藉由利用石墨靶材作為初始材料,將電弧電流設定為70A及將電弧電壓設定為26V,可藉由FCA方法形成厚度約20nm的非晶碳膜。
如第9D圖所示,形成閘極電極41。舉例而言,在絕緣層30上鋪設光阻層,接著利用曝光設備曝光並顯影,因而形成在即將形成閘極電極41的區域中具有開口部之阻劑圖案(未圖示)。藉由真空沈積形成金屬膜(例如具有厚度約10nm的鎳膜或具有厚度約300nm的金膜)在整體表面上,而形成在該阻劑圖案上之金屬膜係和該阻劑一起被剝離並藉由浸入有機溶劑等而移除。包含鎳/金之閘極電極41係形成在絕緣膜30上的給定區域中。
如第9E圖所示,保護膜50係形成在絕緣膜30上。舉例而言,保護膜50可包含藉由ALD方法形成之氧化鋁膜、藉由FCA方法形成之非晶碳膜、藉由電漿CVD方法形成之氮化矽膜、或這些膜之層疊。
經過上述過程可形成電晶體。半導體層可包含GaN和
AlGaN並亦可包含氮化物半導體,例如InAlN或InGaAlN。
第10圖說明例示性膜形成設備。如第10圖所示之膜形成設備可為用於FCA方法的FCA膜形成設備。所述FCA膜形成設備包含電漿產生部110、電漿分離部120、粒子捕捉部130、電漿傳輸部140、及膜形成腔室150。所述電漿產生部110、電漿分離部120、及粒子捕捉部130可具有圓柱形狀且可以此順序結合。所述電漿傳輸部140亦可具有圓柱形狀。電漿傳輸部140的一端幾乎垂直耦接於電漿分離部120而電漿傳輸部的另一端耦接於膜形成腔室150。於所述膜形成腔室150的內部,設置有用於配置基板151等作為膜形成目標之平台152。
絕緣板111設置在電漿產生部110的殼的下端部上,且作為靶材(陰極)112的石墨係設置在絕緣板111上。在電漿產生部110的殼的下端部之周圍上設置有陰極線圈114。於該殼的內壁表面上設置有陽極113。當形成非晶碳膜時,藉由在靶材112與陽極113之間施加來自未圖示之電源的給定電壓而發生電弧放電,以至於在靶材112上形成電漿。於陰極線圈114中,藉由供應來自另一未圖示之電源的給定電流而產生用於穩定該電弧放電的磁場。由於該電弧放電,碳(其為石墨的靶材112)蒸發並提供至電漿中作為膜形成材料的離子。
絕緣環121係設置在電漿產生部110與電漿分離部120之間的邊界部分上。電漿產生部110的殼和電漿分離部120的殼係藉由絕緣膜121而電性分離。在電漿分離部
120的周圍上設置有導引線圈122a和122b,其產生用於移動電漿產生部110中在給定方向所形成之電漿同時聚集該電漿至該殼的中央部分之磁場。電漿分離部120和電漿傳輸部140的相連部分附近設置有傾斜磁場產生線圈123,其產生實質上垂直偏轉電漿移動方向之磁場。
電漿產生部110中所產生的粒子進入且不易受到電漿分離部120的磁場影響而直走進入粒子捕捉部130。在粒子捕捉部130的上端部設置有用以在橫向反射粒子之反射器131以及用以擷取由反射器131所反射的粒子之粒子擷取部132。在所述粒子擷取部132中,傾斜設置有複數鰭片133在該殼的內部。進入粒子擷取部132中的粒子藉由鰭片133重複反射而失去動能。最後,粒子黏附至鰭片133或粒子擷取部132的殼的壁表面而被擷取。
從電漿分離部120中的粒子分離出來的電漿進入電漿傳輸部140。所述電漿傳輸部140分為負電壓施加部142和結合部146。絕緣環141設置在負電壓施加部142與電漿分離部120之間以及在負電壓施加部142與結合部146之間。電漿分離部120和負電壓施加部142係電性分離且結合部146和負電壓施加部142係電性分離。
負電壓施加部142分為在電漿分離部120一側之入口部143、在結合部146一側之出口部145、及在入口部143與出口部145之間的中間部144。在入口部143的周圍上設置有用於移動膜形成腔室150的一側的電漿同時聚集該電漿之143a。在入口部143的內部設置傾斜於殼內表面之
用於擷取進入入口部143的粒子之複數個鰭片143b。
在中間部144的入口部143側和出口部145側分別設置有各自具有用以校準電漿的流動路徑之開口部之孔隙144a和144b。在中間部144的周圍上設置有用以產生磁場以偏轉電漿移動方向之導引線圈144c。
結合部146的直徑可自負電壓施加部142側至膜形成腔室150逐漸變大。結合部146的內部中亦設置有複數個鰭片146a。在結合部146和膜形成腔室150之邊界部分的周圍上設置有用以將電漿移動至膜形成腔室150側同時聚集該電漿之導引線圈146b。
在FCA膜形成設備中,電漿產生部110釋放電弧並產生含有碳離子的電漿。該電漿接觸到基板151等同時傾斜磁場產生線圈123等正移動成為粒子的組成物。因此,在基板151等上形成非晶碳膜。
第11圖說明例示性半導體裝置。如第11圖所示之半導體裝置包含絕緣膜230,其包含氧化鋁膜231和非晶碳膜232的層疊結構,例如,其中有非晶碳膜2322形成在氧化鋁膜231上之絕緣膜230,取代第6圖所示之半導體裝置之包含非晶碳膜之絕緣膜30。可利用三甲基鋁(TMA)和純水(H2
O)並設定基板溫度為300℃而藉由ALD方法形成具有厚度約10nm的氧化鋁膜231。藉由上述FCA方法,可形成具有厚度約10nm的非晶碳膜232。第12A及12B圖各自說明例示性絕緣膜。第12A圖可為第11圖所示之絕緣膜230之放大圖。
在對應於絕緣膜230之閘極絕緣膜中,層疊有兩種不同材料的膜。因而可減少閘極漏電流。例如,可藉由堆疊其絕緣特性大於那些非晶碳膜之氧化鋁膜(當相較於僅含有非晶碳膜之絕緣膜時)來降低閘極漏電流。
為了減少閾值電壓變化範圍,非晶碳膜232的厚度可等於或大於第5圖所示之氧化鋁膜231。非晶碳膜232的厚度可為10nm或更多。
可形成二氧化鉿膜或氮化矽膜以代替氧化鋁膜231。如第12B圖所示,藉由形成非晶碳膜232以及形成氧化鋁膜231在非晶碳膜232上,可形成絕緣膜233或絕緣膜230。其他元件可實質上相同或相似於第9圖所示之元件。
第13圖說明例示性半導體裝置。第13圖所示之半導體裝置可為HEMT。所述半導體裝置可包含形成在基板310上之緩衝層320以及包含藉由磊晶生長層疊在緩衝層320上之電子過渡層321、電子供應層322及蓋層323之半導體。源極電極342和汲極電極343耦接至電子過渡層321。閘極電極341係通過在藉由部份地移除蓋層323和電子供應層322所形成之開口部中之絕緣膜330而形成。所述絕緣膜330亦形成在蓋層323上,且包含絕緣體之保護膜350形成在絕緣膜330上。
基板310可包含矽基板、碳化矽基板、藍寶石(Al2
O3
)基板等。當基板310為矽基板時,形成緩衝層320。當基板310包含其他材料時,可能不會形成緩衝層320。電子過渡層321可為i-GaN,電子供應層322可為n-AlGaN,
而蓋層323可為n-GaN。在電子供應層322接近電子過渡層321的一側形成有二維電子雲(2DEG)321a。在電子過渡層321和電子供應層322之間可形成間隔層(未圖示)。
閘極電極341、源極電極342、及汲極電極343包含金屬材料。例如,對應於閘極絕緣膜之絕緣膜含有非晶碳膜且具有厚度20nm。保護膜50可藉由電漿ALD所形成之氧化鋁(Al2
O3
)膜而形成。
第14A至14F圖說明用於製造半導體裝置之例示性方法。
如第14A圖所示,緩衝層320係形成在基板310上。具有所述電子過渡層321、電子供應層322、蓋層323等之半導體層藉由磊晶生長(如MOVPE)而形成在緩衝層320上。基板310可為包含矽、碳化矽、藍寶石(Al2
O3
)等之基板。為了藉由磊晶生長而形成電子過渡層321等,緩衝層320可形成在基板310上。例如,緩衝層320可為厚度約0.1μm的無摻雜i-AlN。所述電子過渡層321可為厚度約3μm的無摻雜i-GaN。所述電子供應層322可為厚度約30nm的n-Al0.25
Ga0.75
N,其可以濃度約5×1018
cm-3
的矽作為雜質元素進行摻雜。所述蓋層323可為具有厚度約10nm之n-GaN,其可以濃度5×1018
cm-3
的矽作為雜質元素來摻雜。
如第14B圖所示,形成源極電極342和汲極電極343。例如,光阻層鋪設在蓋層323上,接著以曝光設備曝光並顯影,因而在即將形成源極電極342和汲極電極343之區
域形成具有開口部之阻劑圖案(未圖示)。實施乾蝕刻,如使用氯氣的RIE以移除在無形成阻劑圖案的區域中之蓋層323和電子供應層322,以至於暴露電子過渡層321的表面。藉由真空沈積等形成包含Ta/Al層疊膜等之金屬膜,且形成在該阻劑圖案上的金屬膜係和該阻劑圖案一起被剝離並藉由浸入有機溶劑等而移除。源極電極342和汲極電極343係形成在無形成該阻劑圖案之區域。於剝離之後,歐姆接觸係藉由溫度550℃之熱處理而達成。
如第14C圖所示,形成開口部361。例如,在蓋層232上鋪設光阻層,接著利用曝光設備曝光並顯影,因而形成在即將形成開口部361的區域中具有開口部之阻劑圖案(未圖示)。利用阻劑圖案作為遮罩引入包括氯的氣體,並藉由RIE等實施乾蝕刻。部份地移除蓋層323和電子供應層322之阻劑圖案未形成之區域,接著形成開口部361。移除阻劑圖案。
如第14D圖所示,絕緣膜330係形成在蓋層323及開口部361的內表面上。可藉由FCA方法形成的非晶碳膜而形成絕緣膜330。例如,藉由利用石墨靶材作為初始材料,將電弧電流設定為70A及將電弧電壓設定為26V,可藉由FCA方法形成厚度約20nm的非晶碳膜,則形成絕緣膜330。
如第14E圖所示,形成閘極電極341。舉例而言,藉由旋轉塗布方法等應用將未圖示之下方阻劑層如(由U.S MicroChem公司所製造之PMGI(商標名稱))和上阻劑層(如
由Sumitomo Chemical有限公司所製造之PFI32-A8(商標名稱))分別形成在絕緣膜330上。利用曝光設備實施曝光並顯影,其中具有直徑約0.8μm的開口形成在含有開口部361形成於其中的區域之上阻劑層中。使用該上阻劑層作為遮罩藉由鹼性顯像劑蝕刻該下方阻劑層。藉由真空沈積形成金屬膜(例如具有厚度約10nm的鎳膜或具有厚度約300nm的金膜)在整體表面上,並利用熱有機溶劑實施剝離移除形成在該上阻劑層上的金屬膜及該下方阻劑層和上阻劑層。包含鎳/金之閘極電極341係通過絕緣膜330形成在開口部361中。
如第14F圖所示,保護膜350係形成在絕緣膜330上。舉例而言,保護膜350可包含藉由ALD方法形成之氧化鋁膜、藉由FCA方法形成之非晶碳膜、藉由電漿CVD方法形成之氮化矽膜、或這些膜之層疊結構。
第15圖說明例示性離散封裝半導體裝置。所述半導體裝置可為第6、11或13圖所示之半導體裝置。第15圖概略繪示離散封裝半導體裝置之內部,其中,電極等配置可與第6、11或13圖所示之電極配置不相同。
舉例而言,可藉由切粒(dicing)等方式切割第6、11或13圖所示之半導體裝置,藉此形成含有GaN基半導體材料之HEMT半導體晶片410。所述半導體晶片410藉由晶粒接觸黏著劑430(如焊料)固定在引線架420上。
閘極電極441通過接合導線431耦接至閘極引線421。源極電極442通過接合導線432耦接至源極引線
422。汲極電極443通過接合導線433耦接至汲極引線423。接合導線431、432及433可包含金屬材料,例如鋁。閘極電極441可為閘極電極墊,並耦接至閘極電極41或第6、11或13圖所示之341。源極電極442可為源極電極墊,並耦接至源極電極42或342。汲極電極443可為汲極電極墊,並耦接至汲極電極43或343。
藉由轉移模(transfer mold)方法利用壓模樹脂440實施樹脂密封。形成具有包含GaN基半導體材料之HEMT之離散封裝的半導體裝置。
第16圖說明例示性電源供應裝置。所述電源供應裝置460包含高壓一次側電路461、低壓二次側電路462及配置在一次側電路461與二次側電路462之間的變壓器463。所述一次側電路461包含AC電源供應器464、橋式整流器465、複數個切換元件466(例如四個切換元件)、及一個切換元件467。所述二次側電路462包含複數個切換元件468(例如三個切換元件)。第6、11或13圖所示之半導體裝置可使用作為一次側電路461之切換元件466和467。一次側電路461之切換元件466和467可為常關狀態半導體裝置。在二次側電路462側之切換元件468可包含含有矽之金屬半導體場效電晶體(MISFET)。
第17圖說明例示性高頻放大器。高頻放大器470可應用於例如行動電話的基地台之功率放大器。所述高頻放大器470包含數位預失真電路471、混合器472、功率放大器473及定向耦合器474。所述預失真電路471補償輸入
訊號的非線性失真。所述混合器472混合該輸入訊號,其中該非線性失真已補償且具有交流電訊號。所述功率放大器473放大混合有該交流電訊號之輸入訊號。所述功率放大器473可包含第6、11或13圖所示之半導體裝置。所述定向耦合器474監視輸入訊號或輸出訊號。例如,所述混合器472可混合輸出訊號和交流電訊號,並基於開關的切換將該混合訊號傳輸至該數位預失真電路471。
已依照上述優點描述本發明的例示具體實施例。得以理解這些範例僅說明本發明。各種變化和修改對於所屬技術領域中具有通常知識者而言將是顯而易見的。
1、10、151、310‧‧‧基板
2、20、320‧‧‧緩衝層
3、21、321‧‧‧電子過渡層
3a、21a、321a‧‧‧二維電子雲
4‧‧‧間隔層
5、22、322‧‧‧電子供應層
6、23、323‧‧‧蓋層
7、7a、7b、30、230、233、330‧‧‧絕緣膜
8‧‧‧陽極電極
8A、8B‧‧‧電漿峰值
9‧‧‧陰極電極
41、341、441‧‧‧閘極電極
42、342、442‧‧‧源極電極
43、343、443‧‧‧汲極電極
50、350‧‧‧保護膜
110‧‧‧電漿產生部
111‧‧‧絕緣板
112‧‧‧靶材
113‧‧‧陽極
114‧‧‧陰極線圈
120‧‧‧電漿分離部
121、141‧‧‧絕緣環
122a、122b、144c、146b‧‧‧導引線圈
123‧‧‧傾斜磁場產生線圈
130‧‧‧粒子捕捉部
131‧‧‧反射器
132‧‧‧粒子擷取部
133、143b、146a‧‧‧鰭片
140‧‧‧電漿傳輸部
142‧‧‧負電壓施加部
143‧‧‧入口部
144‧‧‧中間部
144a、144b‧‧‧孔隙
145‧‧‧出口部
146‧‧‧結合部
150‧‧‧膜形成腔室
152‧‧‧平台
231‧‧‧氧化鋁膜
232‧‧‧非晶碳膜
361‧‧‧開口部
410‧‧‧半導體晶片
420‧‧‧引線架
421‧‧‧閘極引線
422‧‧‧源極引線
423‧‧‧汲極引線
430‧‧‧晶粒接觸黏著劑
431、432、433‧‧‧接合導線
440‧‧‧壓模樹脂
460‧‧‧電源供應裝置
461‧‧‧一次側電路
462‧‧‧二次側電路
463‧‧‧變壓器
464‧‧‧電源供應器
465‧‧‧橋式整流器
466、467、468‧‧‧切換元件
470‧‧‧高頻放大器
471‧‧‧數位預失真電路
472‧‧‧混合器
473‧‧‧功率放大器
474‧‧‧定向耦合器
第1圖說明例示性半導體元件;第2A圖及第2B圖說明半導體元件之例示性測量;第3圖說明施加電壓與電容之間的例示性關係;第4A圖至第4C圖說明例示性絕緣膜;第5圖說明非晶碳膜的厚度與閾值電壓變化範圍之間的例示性關係;第6圖說明例示性半導體裝置;第7圖說明碳-碳鍵結比例與膜密度或電漿峰值之間的例示性關係;第8圖說明例示性電漿峰值;第9A圖至第9E圖說明用於製造半導體裝置之例示性方法;第10圖說明例示性膜形成設備;
第11圖說明例示性半導體裝置;第12A圖及第12B圖說明例示性絕緣膜;第13圖說明例示性半導體裝置;第14A圖至第14F圖說明用於製造半導體裝置之例示性方法;第15圖說明例示性離散封裝半導體裝置;第16圖說明例示性電源供應裝置;以及第17圖說明例示性高頻放大器。
1‧‧‧基板
2‧‧‧緩衝層
3‧‧‧電子過渡層
3a‧‧‧二維電子雲
4‧‧‧間隔層
5‧‧‧電子供應層
6‧‧‧蓋層
7‧‧‧絕緣膜
Claims (13)
- 一種半導體裝置,係包括:形成在基板上之半導體層;形成在該半導體層上之絕緣膜;形成在該絕緣膜上之閘極電極;以及源極及汲極電極,至少各該源極及汲極電極之一部份形成在該半導體層內,其中,該絕緣膜包含含碳之非晶膜,其中,該絕緣膜之下表面位於該閘極電極之下,其中,屬於含碳之非晶膜之該絕緣膜之下表面係接觸該半導體層之上表面,其中,該絕緣膜沿著該半導體層朝向該源極及汲極電極延伸,且於該源極電極之側壁及該汲極電極之側壁停止延伸,使得該絕緣膜之一側壁與該源極電極之該側壁接觸,該絕緣膜之另一側壁與該汲極電極之該側壁接觸,且該絕緣膜並未設置於該源極及汲極電極之上表面。
- 如申請專利範圍第1項所述之半導體裝置,其中,該非晶膜之厚度為10nm或更多。
- 如申請專利範圍第1項所述之半導體裝置,其中,該非晶膜中之碳-碳鍵結比例為sp2≦sp3。
- 如申請專利範圍第1項所述之半導體裝置,其中,該非晶膜之密度為2.6g/cm3 或更多以及3.56g/cm3 或更少。
- 如申請專利範圍第1項所述之半導體裝置,其中,基於該非晶膜中之該碳之電漿峰值係為28eV或更高。
- 如申請專利範圍第1項所述之半導體裝置,其中,該非晶膜中之氫含量為1atm%或更低。
- 如申請專利範圍第1項所述之半導體裝置,復包括:在該第二半導體層之開口部,其中,該絕緣膜係形成在該開口部的內表面上;以及該電極係通過該絕緣膜形成在該開口部中。
- 如申請專利範圍第1項所述之半導體裝置,其中,該第一半導體層包含GaN。
- 如申請專利範圍第1項所述之半導體裝置,其中,該第二半導體層包含AlGaN。
- 一種半導體裝置之製造方法,係包括以下步驟:在基板上形成半導體層;形成源極及汲極電極,使得至少各該源極及汲極電極之一部份形成在該半導體層內,在該半導體層上形成包含含碳的非晶膜之絕緣膜,其中,該絕緣膜沿著該半導體層朝向該源極及汲極電極延伸,且於該源極電極之側壁及該汲極電極之側壁停止延伸,使得該絕緣膜之一側壁與該源極電極之該側壁接觸,該絕緣膜之另一側壁與該汲極電極之該側壁接觸,且該絕緣膜並未設置於該源極及汲極電極之上表面;以及在該絕緣膜上形成閘極電極,其中,該絕緣膜之下表面位於該閘極電極之下, 以及其中,屬於含碳之非晶膜之該絕緣膜之下表面係接觸該半導體層之上表面。
- 如申請專利範圍第10項所述之半導體裝置之製造方法,包括:形成第一半導體層;在該第一半導體層上形成第二半導體層;以及其中,該源極電極及該汲極電極係接觸該第一半導體層或該第二半導體層。
- 如申請專利範圍第10項所述之半導體裝置之製造方法,包括:形成開口部於第二半導體層中;形成該絕緣膜於該第二半導體層及該開口部的內表面上;以及通過該絕緣膜形成該電極於該開口部中。
- 如申請專利範圍第10項所述之製造半導體裝置之方法,其中,該非晶膜係藉由電弧蒸氣氣相沈積方法而形成。
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JP2021145049A (ja) * | 2020-03-12 | 2021-09-24 | 富士通株式会社 | 半導体装置 |
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