TWI446505B - 元件內埋式基板與應用其之半導體封裝結構以及製作方法 - Google Patents

元件內埋式基板與應用其之半導體封裝結構以及製作方法 Download PDF

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TWI446505B
TWI446505B TW099124915A TW99124915A TWI446505B TW I446505 B TWI446505 B TW I446505B TW 099124915 A TW099124915 A TW 099124915A TW 99124915 A TW99124915 A TW 99124915A TW I446505 B TWI446505 B TW I446505B
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module
structure module
electronic component
layer
conductive layer
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TW099124915A
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English (en)
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TW201143005A (en
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Bernd Karl Appelt
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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Description

元件內埋式基板與應用其之半導體封裝結構以及製作方法
本發明是有關於一種基板、半導體封裝結構及其製作方法，且特別是有關於一種元件內埋式基板、應用此元件內埋式基板的半導體封裝結構及其製作方法。
一般而言，線路基板是由多個圖案化線路層與多個介電層交替堆疊而成，其中介電層用以隔絕兩相鄰圖案化線路層。相鄰的圖案化線路層可經由穿過介電層的鍍通孔(plated through hole,PTH)或導電通孔(conductive via)相互電性連接。此外，各種電子元件(如主動或被動元件)可被設置於線路基板的表面或埋入線路基板，以藉由內部線路的設計來達到電信號傳遞的目的。
為了滿足市面上之電子產品輕量化與微型化的需求，更發展出採用內埋式基板的封裝技術。然而，由於電子元件通常具有標準規格與特定的電氣特性，為了容置各種電氣特性的電子元件，元件內埋式基板必須客製化，而導致低製程良率與較長的生產週期。
為促進此技術的發展，有必要簡化元件內埋式基板的製作，以增加製程良率並降低生產成本。
本發明提出一種具有至少一電子元件的元件內埋式半導體封裝結構的封裝製程，其可增進生產良率並降低製作成本與生產週期。
本發明提出一種具有至少一內埋式電子元件的半導體封裝結構，或內埋至少一電子元件的基板。
本發明之一實施例提出一種半導體封裝結構，包括一組裝架構模塊、一間隔架構模塊以及一遮蓋架構模塊，其中組裝架構模塊上組裝有至少一電子元件。間隔架構模塊接合至組裝架構模塊以及遮蓋架構模塊。半導體封裝結構更包括多個導電通孔，用以電性連接組裝架構模塊、間隔架構模塊以及遮蓋架構模塊，以及一封膠，填入組裝架構模塊、間隔架構模塊以及遮蓋架構模塊接合後共同形成的一凹穴中。所述至少一電子元件配置於凹穴內並且埋入封膠。
本發明之另一實施例提出一種半導體封裝結構，包括一組裝架構模塊，其上組裝有至少一第一電子元件，以及一凹穴架構模塊，其上組裝有至少一第二電子元件。凹穴架構模塊接合至組裝架構模塊。半導體封裝結構更包括多個導電通孔，用以電性連接組裝架構模塊以及凹穴架構模塊，以及一封膠，填入組裝架構模塊與凹穴架構模塊接合後所形成的一凹穴內。所述至少一第一電子元件以及所述至少一第二電子元件配置於凹穴內並且埋入封膠。
本發明之另一實施例提出一種具有內埋式電子元件的半導體封裝結構的封裝製程。首先提供一組裝架構模塊，其上組裝至少一電子元件。接著，接合一間隔架構模塊至該組裝架構模塊，使所述至少一電子元件配置於接合後的間隔架構模塊與組裝架構模塊共同形成的一凹穴內。然後，在凹穴內填入一封膠，以包封所述至少一電子元件。之後，接合一遮蓋架構模塊至間隔架構模塊，以密封凹穴。
本發明之另一實施例提出一種具有內埋式電子元件的半導體封裝結構的封裝製程。首先，提供一組裝架構模塊，並且組裝至少一第一電子元件至組裝架構模塊上，其中所述至少一第一電子元件電性連接至組裝架構模塊。接著，提供一凹穴架構模塊，並且組裝至少一第二電子元件至凹穴架構模塊，其中所述至少一第二電子元件電性連接至凹穴架構模塊。然後，將一封膠填入凹穴架構模塊的一凹穴，以包封所述至少一第二電子元件。之後，接合凹穴架構模塊至組裝架構模塊，使得所述至少一第一電子元件以及所述至少一第二電子元件配置於凹穴架構模塊與組裝架構模塊形成的凹穴內，並且埋入封膠。
在本發明之實施例中，不同的架構模塊之間可直接接合或是透過導電膠接合。
在本發明中，藉由預先形成的架構模塊可以簡化具有內埋式電子元件的半導體封裝結構的封裝製程，並且提供較大的製程彈性。因此，可縮短半導體封裝結構的組裝時程，並提高其生產良率。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
雖然在本申請中使用『第一』、『第二』或其他類似用語來描述元件、區域、膜層或部位，但該用語並非用來限定所述元件、區域、膜層或部位，而僅是用來區分不同的元件、區域、膜層或部位。因此，在不脫離本發明所教示的範圍的情形下，所述第一元件、區域、膜層或部位也可能是第二元件、區域、膜層或部位。
本發明的一實施例提出一種具有內埋式元件的半導體封裝結構的製作方法，至少包括提供兩個以上預先形成的架構模塊(即，結構元件)，組裝至少一電子元件(主動或被動元件)至所述架構模塊中的至少一個上，並且接合所述架構模塊，以得到元件內埋式半導體封裝結構。由此，此封裝製程可提供較大的製程彈性。
圖1A至1D繪示依據本發明之一實施例的一種基板的架構模塊的製作流程。如圖1A所示，提供一基板110。基板110例如是多層線路板、雙面層壓結構(double-sided lamination structure)或覆銅箔層壓板(copper clad laminate,CCL)。基板110至少包括一頂部導電層112、一底部導電層114以及一核心層116。核心層116可由包括樹脂與玻璃纖維的預浸材料所製成。頂部導電層112與底部導電層114分別設置於核心層116的頂面116a與底面116b。頂部導電層112與底部導電層114可由銅、鋁、鋁-銅合金或其他適當的導電材料製成。
同樣地，雖然本發明中採用『頂(部)』、『底(部)』或其他類似用語來描述特定區域、表面或膜層，然該些用語僅適用來區分該些元件的相對位置，並非用來限定本發明。因此，在不脫離本發明所教示的範圍的情形下，所述頂面或頂部膜層亦可為底面或底部膜層。
接著，如圖1B所示，形成多個導電通孔120於基板110中。每一導電通孔120連接頂部導電層112與底部導電層114。因此，頂部導電層112藉由導電通孔120電性連接至底部導電層114。導電通孔120可採用鑽孔、化學鍍銅或電鍍等方式來形成。導電通孔120內可藉由電鍍填滿銅，或僅是如一般的鍍通孔內襯一銅層。
如圖1C所示，在形成導電通孔120之後，頂部導電層112與底部導電層114(如圖1B所示)會被圖案化，以分別形成一圖案化頂部導電層124以及一圖案化底部導電層126。頂部導電層112以及底部導電層114可藉由微影與蝕刻製程來被圖案化。
圖案化頂部導電層124包括多條線路124a以及多個第一連接墊124b。圖案化底部導電層126包括多個接合墊126a以及多個第二連接墊126b。第一連接墊124b以及第二連接墊126b藉由導電通孔120相互電性連接。
如圖1D所示，進行一表面處理製程以分別形成一表面加工層130於圖案化頂部導電層124以及圖案化底部導電層126的表面上。表面加工層130例如是鎳/金疊層，含銀層或是含錫層。尤其，表面加工層130的材質可為化學鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)、化學鎳金(electroless nickel immersion gold,ENIG)，化學浸銀(immersion silver,iAg)、化學浸錫(immersion tin,iSn)，化學鍍錫(electroless plating tin,eSn)或甚至有機保焊劑(organic solderability preservatives,OSP)。圖1D繪示的架構模塊可被視為一組裝架構模塊10，其中圖案化底部導電層126包括接合墊126a，適於與電子元件接合。
另外，若圖1C的圖案化製程是採用不同的連接墊與線路設計，則如圖2所示，圖案化頂部導電層124’包括多條第一線路124a’以及多個第一連接墊124b’。圖案化底部導電層126’包括多條第二線路126a’以及多個第二連接墊126b’。第一連接墊124b’以及第二連接墊126b’藉由導電通孔120’相互電性連接，而表面加工層130’分別配置於圖案化頂部導電層124’以及圖案化底部導電層126’的表面。圖2所示的架構模塊可被視為一遮蓋架構模塊20。組裝架構模塊10與遮蓋架構模塊20的不同處主要在於遮蓋架構模塊20不需要具有元件的接合墊，且可能被設計為僅具有單側的導電圖案。
圖3繪示依據本發明之一實施例的另一種基板的架構模塊。接續類似圖1A-1D所示的製作流程，可進行一沖孔製程來切除一部分的核心層316而形成至少一中空部份340。核心層316可包括具有內埋線路的預浸材料、多層層壓板或覆銅箔層壓板。圖案化頂部導電層324包括多個第一連接墊324b，而圖案化底部導電層326包括多個第二連接墊326b。導電通孔320連接第一連接墊324b以及第二連接墊326b，而表面加工層330可被分別設置於第一連接墊324b以及第二連接墊326b的表面。圖3所示的架構模塊可被視為一間隔架構模塊30，而中空部份340可承載裝配的元件。
前述製作架構模塊的製程步驟並非用以限制本發明的範圍，已知可供替換的製程步驟皆可應用於本發明中，包括增層(additive)、減層(subtractive)或半增層(semi-additive)的疊層基板技術，以及無芯(coreless)基板技術等。
另外，雖然在此描述了三種架構模塊，然本領域中具有通常知識者在不脫離本發明的範圍內應能藉由改變膜層圖案設計、材質或膜層數量來得到不同的架構模塊。若需要單面的架構模塊，也可對前述塊狀結構進一步加工，以移除一側的導電圖案。
前述架構模塊也可相互接合以形成另一種架構模塊。舉例而言，如圖4A所示，取決於兩個架構模塊之表面加工層的材質，組裝架構模塊10以及間隔架構模塊30可選擇藉由超音波接合(ultrasonic bonding)或熱壓(thermal compression)等技術直接相互接合，以形成一凹穴架構模塊40A。依據連接墊之金屬表面處理的選擇，前述架構模塊也可以藉由回銲技術來接合。另一方面，如圖4B所示，組裝架構模塊10以及間隔架構模塊30也可藉由一導電膠A相互接合，以形成凹穴架構模塊40B。在此，組裝架構模塊10以及間隔架構模塊30經由導電通孔120/320相互電性連接。
圖4C繪示依據本發明之一實施例的一種元件內埋式基板的製作方法。如圖4C所示，提供如圖4A或4B所示的凹穴架構模塊40A或40B。此處以凹穴架構模塊40B為例，並且將一電子元件402組裝至架構模塊40A的接合墊406，使電子元件402位於凹穴440內。實際上，可選擇在接合組裝架構模塊10與間隔架構模塊30之前或之後來組裝電子元件402。本發明所應用的電子元件可為主動元件，如晶片，或被動元件，如電容或電阻。本實施例的電子元件402例如是一晶片，其藉由例如覆晶接合技術透過多個凸塊404電性連接至接合墊406。另外，電子元件402也可透過打線接合技術電性連接至接合墊406。由此，圖4C所示的結構可被視為元件內埋式基板400。
圖5A-5D繪示依據本發明之一實施例的一種具有內埋式元件的半導體封裝結構的製作流程。
如圖5A所示，提供組裝架構模塊10，並且組裝一電子元件502至組裝架構模塊10的接合墊126a。本發明所應用的電子元件可為主動元件，如晶片，或被動元件，如電容或電阻。電子元件502例如是一晶片，其藉由例如覆晶接合技術透過多個凸塊504電性連接至接合墊126a。凸塊504可為銲料凸塊、金凸塊或銅柱凸塊。另一方面，電子元件502也可透過打線接合技術電性連接至接合墊126a(如圖6A所示)。
如圖5B所示，提供間隔架構模塊30，並且將組裝架構模塊10連同組裝的電子元件502接合至間隔架構模塊30。在此，組裝架構模塊10(連同組裝的電子元件502)可透過熱壓或超音波接合技術接合至間隔架構模塊30。在接合組裝架構模塊10(連同組裝的電子元件502)以及間隔架構模塊30之後，組裝的電子元件502會位於接合結構的凹穴540內。
另一方面，組裝架構模塊10(連同組裝的電子元件502)以及間隔架構模塊30也可透過導電膠(如圖4B所示)來相互接合。
在接合製程之前，可選擇在凸塊504周圍形成一底填材料506，以增進封裝強度。然而，是否形成底填材料506是可選擇的，並取決於電子元件或凸塊的穩定性與可操縱性(handle ability)。
如圖5C所示，在凹穴540內填入一封膠508。在此，封膠508可略微突出於間隔架構模塊30的底面30a，或是至少填滿凹穴540。
如圖5D所示，將遮蓋架構模塊20接合至間隔架構模塊30的底面30a，以形成具有元件內埋式基板的半導體封裝結構50。遮蓋架構模塊20可藉由熱壓接合、超音波接合、回銲或應用導電膠接合等方式來接合至由組裝架構模塊10與間隔架構模塊30所構成的接合結構。遮蓋架構模塊20、組裝架構模塊10以及間隔架構模塊30可透過導電通孔120/320/120’相互電性連接。
另一方面，在另一實施例中，前述製程步驟的順序可被變更。如圖6A所示，將遮蓋架構模塊20接合至間隔架構模塊30的底面30a。遮蓋架構模塊20具有單面的導電圖案。接著，封膠608被填入接合結構的凹穴640內。之後，提供組裝架構模塊10以及電子元件602，其中電子元件602可為被動元件，如電阻，並且電子元件602透過銲線604電性連接(打線接合)至組裝架構模塊10的接合墊126a。銲線604可為金線、銅線或鋁線。
如圖6B所示，組裝架構模塊10連同電子元件602被接合至由間隔架構模塊30以及遮蓋架構模塊20構成的接合結構。其中，應注意控制封膠608的量，以確保接合後封膠608可填滿凹穴640以及電子元件602周圍的空隙。
圖7A與7B繪示依據本發明之另一實施例的一種具有內埋式元件的半導體封裝結構的製作流程。
如圖7A所示，提供如圖4C所示的元件內埋式基板400，並且將一封膠708填入元件內埋式基板400的凹穴440，並填滿電子元件402周圍的空隙。換言之，即是將圖4C所示的結構倒置。
如圖7B所示，組裝架構模塊10連同電子元件502被接合至元件內埋式基板400(即，內埋有電子元件402的凹穴架構模塊40A)，以形成具有元件內埋式基板400的半導體封裝結構70。其中，應注意控制封膠708的量，以確保接合後封膠708可填滿凹穴440以及電子元件402與502周圍的空隙。
綜上所述，藉由預先形成的架構模塊，可以簡化元件內埋式基板的製作，以提高生產良率並降低的生產成本。另外，可在組裝製程前，先對預先形成的元件內埋式基板進行電性或功能性測試，以確保可靠度。
再者，應用本發明提出的各類型的架構模塊或結合元件內埋式基板，可以得到晶片堆疊式半導體封裝結構、多晶片半導體封裝結構或甚至封裝堆疊結構。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．組裝架構模塊
110．．．基板
112．．．頂部導電層
114．．．底部導電層
116．．．核心層
116a．．．核心層的頂面
116b．．．核心層的底面
120、120’．．．導電通孔
124、124’．．．圖案化頂部導電層
126、126’．．．圖案化底部導電層
124a、124a’．．．線路
124b、124b’．．．第一連接墊
126a、126a’．．．接合墊
126b、126b’．．．第二連接墊
130、130’．．．表面加工層
20．．．遮蓋架構模塊
30．．．間隔架構模塊
30a．．．間隔架構模塊的底面
316．．．核心層
320．．．導電通孔
324．．．圖案化頂部導電層
324b．．．第一連接墊
326．．．圖案化底部導電層
326b．．．第二連接墊
330．．．表面加工層
340．．．中空部份
40A．．．凹穴架構模塊
40B．．．凹穴架構模塊
400．．．元件內埋式基板
402．．．電子元件
404．．．凸塊
406．．．接合墊
440．．．凹穴
50．．．半導體封裝結構
502．．．電子元件
504．．．凸塊
506．．．底填材料
508．．．封膠
540．．．凹穴
602．．．電子元件
604．．．銲線
608．．．封膠
640．．．凹穴
70．．．半導體封裝結構
708．．．封膠
A．．．導電膠
圖1A至1D繪示依據本發明之一實施例的一種基板的架構模塊的製作流程。
圖2繪示依據本發明之一實施例的另一種基板的架構模塊。
圖3繪示依據本發明之一實施例的另一種基板的架構模塊。
圖4A與4B繪示依據本發明之其他實施例的多種基板的架構模塊。
圖4C繪示依據本發明之一實施例的一種元件內埋式基板的製作方法。
圖5A-5D繪示依據本發明之一實施例的一種具有內埋式元件的半導體封裝結構的製作流程。
圖6A與6B繪示依據本發明之另一實施例的一種具有內埋式元件的半導體封裝結構的製作流程。
圖7A與7B繪示依據本發明之一實施例的一種具有內埋式元件的半導體封裝結構的製作流程。
10．．．組裝架構模塊
116．．．核心層
120、120’．．．導電通孔
124．．．圖案化頂部導電層
126’．．．圖案化底部導電層
124a．．．線路
124b．．．第一連接墊
126a、126a’．．．接合墊
126b’．．．第二連接墊
130、130’．．．表面加工層
316．．．核心層
320．．．導電通孔
330．．．表面加工層
40A．．．凹穴架構模塊
402．．．電子元件
440．．．凹穴
502．．．電子元件
504．．．凸塊
70．．．半導體封裝結構
708．．．封膠

Claims (15)

  1. 一種半導體封裝結構，包括：一組裝架構模塊，其上組裝有至少一電子元件，該組裝架構模塊包括：一第一核心層，具有一第一表面以及與該第一表面相對的一第二表面；一第一導電層，位於該第一核心層的該第一表面上，其中該第一導電層包括多個第一連接墊與形成在各該第一連接墊上的一第一表面加工層；一第二導電層，位於該第一核心層的該第二表面上，其中該第二導電層包括多個第二連接墊、多個接合墊與形成在各該第二連接墊表面的一第二表面加工層，該第一導電層以及該第二導電層是透過所述多個導電通孔相互電性連接，其中該至少一電子元件電性連接至該些接合墊；一間隔架構模塊，接合至該組裝架構模塊的該第二表面，該間隔架構模塊包括：一第二核心層，具有一第三表面以及與該第三表面相對的一第四表面；一第三導電層，位於該第二核心層的該第三表面上，其中該第三導電層包括多個第三連接墊與形成在各該第三連接墊上的一第三表面加工層，該些第三表面加工層連接於該些第二表面加工層；一第四導電層，位於該第二核心層的該第四表面上，其中該第四導電層包括多個第四連接墊與形成在各該 第四連接墊上的一第四表面加工層；一遮蓋架構模塊，接合該間隔架構模塊的該些第四表面加工層；多個導電通孔，分別形成於該組裝架構模塊中、該間隔架構模塊中以及該遮蓋架構模塊中，且該組裝架構模塊、該間隔架構模塊以及該遮蓋架構模塊藉由該些導電通孔與該些第二表面加工層、該些第三表面加工層與該些第四表面加工層而彼此電性連接；一封膠，填充一凹穴，該凹穴為該組裝架構模塊、該間隔架構模塊以及該遮蓋架構模塊接合後共同形成，其中該至少一電子元件配置於該凹穴內並且埋入該封膠。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中該至少一電子元件是透過多個凸塊電性接合至該組裝架構模塊的該些接合墊。
  3. 如申請專利範圍第2項所述之半導體封裝結構，更包括包圍該些凸塊設置的一底填材料。
  4. 一種封裝製程，包括：提供一組裝架構模塊，該組裝架構模塊包括：一第一核心層，具有一第一表面以及與該第一表面相對的一第二表面；一第一導電層，位於該第一核心層的該第一表面上，該第一導電層包括多個第一連接墊；一第二導電層，位於該第一核心層的該第二表面 上，該第二導電層包括多個第二連接墊與多個接合墊；對該些第一連接墊與該些第二連接墊進行一表面處理製程，以在各該第一連接墊上形成一第一表面加工層，並在各該第二連接墊上形成一第二表面加工層；組裝至少一電子元件至該組裝架構模塊上，其中該至少一電子元件電性連接至該組裝架構模塊的該些接合墊；提供一間隔架構模塊，該間隔架構模塊包括：一第二核心層，具有一第三表面以及與該第三表面相對的一第四表面；一第三導電層，位於該第二核心層的該第三表面上，其中該第三導電層包括多個第三連接墊；一第四導電層，位於該第二核心層的該第四表面上，其中該第四導電層包括多個第四連接墊；對該些第三連接墊與該些第四連接墊進行一表面處理製程，以在各該第三連接墊上形成一第三表面加工層，以在各該第四連接墊上形成一第四表面加工層；接合該間隔架構模塊至該組裝架構模塊，使得該至少一電子元件設置於該間隔架構模塊與該組裝架構模塊共同形成的一凹穴內，並使該些第三表面加工層連接於該些第二表面加工層；將一封膠填入該凹穴內以包封該至少一電子元件；以及接合一遮蓋架構模塊至該間隔架構模塊，以密封該凹穴，其中該遮蓋架構模塊連接該些第四表面加工層。
  5. 如申請專利範圍第4項所述之封裝製程，其中接合該間隔架構模塊至該組裝架構模塊的方法包括藉由熱壓製程或超音波接合製程直接接合該間隔架構模塊的該些第三表面加工層至該組裝架構模塊的該些第二表面加工層。
  6. 如申請專利範圍第4項所述之封裝製程，其中接合該間隔架構模塊至該組裝架構模塊的方法包括應用一導電膠來黏合該間隔架構模塊的該些第三表面加工層與該組裝架構模塊的該些第二表面加工層。
  7. 如申請專利範圍第4項所述之封裝製程，更包括在填充該凹穴之前，形成環繞該至少一電子元件的一底填材料。
  8. 如申請專利範圍第4項所述之封裝製程，其中接合該遮蓋架構模塊至該間隔架構模塊的該些第四表面加工層的方法包括藉由熱壓製程或超音波接合製程直接接合該間隔架構模塊至該遮蓋架構模塊。
  9. 如申請專利範圍第4項所述之封裝製程，其中接合該遮蓋架構模塊至該間隔架構模塊的該些第四表面加工層的方法包括應用一導電膠來黏合該間隔架構模塊與該遮蓋架構模塊的該些第四表面加工層。
  10. 一種半導體封裝結構，包括：一組裝架構模塊，其上組裝有至少一第一電子元件，該組裝架構模塊包括：一第一核心層，具有一第一表面以及與該第一表面相對的一第二表面； 一第一導電層，位於該第一核心層的該第一表面上，其中該第一導電層包括多個第一連接墊與形成在各該第一連接墊上的一第一表面加工層；一第二導電層，位於該第一核心層的該第二表面上，其中該第二導電層包括多個第二連接墊、多個接合墊與形成在各該第二連接墊表面的一第二表面加工層，該第一導電層以及該第二導電層是透過所述多個導電通孔相互電性連接，該至少一電子元件電性連接至該些接合墊；一凹穴架構模塊，接合至該組裝架構模塊，其中該凹穴架構模塊包括：一第二核心層，具有一第三表面以及與該第三表面相對的一第四表面；一第三導電層，位於該第二核心層的該第三表面上，其中該第三導電層包括多個第三連接墊與形成在各該第三連接墊上的一第三表面加工層，該些第三表面加工層連接於該些第二表面加工層，至少一第二電子元件組裝至該凹穴架構模塊並且位於由該組裝架構模塊與該凹穴架構模塊共同形成的一凹穴內，其中該至少一第二電子元件電性連接至該凹穴架構模塊；多個導電通孔，分別形成於該組裝架構模塊中以及該凹穴架構模塊中，且該組裝架構模塊與該凹穴架構模塊藉由該些導電通孔與該些第二表面加工層、該些第三表面加工層而彼此電性連接；以及一封膠，填入該組裝架構模塊與該凹穴架構模塊接合 後共同圍出的該凹穴，其中該至少一第一電子元件以及該至少一第二電子元件位於該凹穴內並且被該封膠所包封。
  11. 如申請專利範圍第10項所述之半導體封裝結構，其中該至少一第一電子元件透過多個第一凸塊電性連接至該組裝架構模塊，而該至少一第二電子元件透過多個第二凸塊電性連接至該凹穴架構模塊。
  12. 如申請專利範圍第10項所述之半導體封裝結構，其中該至少一第一電子元件透過多條第一銲線電性連接至該組裝架構模塊，而該至少一第二電子元件透過多條第二銲線電性連接至該凹穴架構模塊。
  13. 如申請專利範圍第10項所述之半導體封裝結構，其中該凹穴架構模塊包括：另一組裝架構模塊，其上組裝有該至少一第二電子元件，其中該至少一第二電子元件電性連接至該另一組裝架構模塊；以及一間隔架構模塊，夾置並接合於該兩組裝架構模塊之間，以形成該凹穴。
  14. 一種封裝製程，包括：提供一組裝架構模塊，該組裝架構模塊包括：一第一核心層，具有一第一表面以及與該第一表面相對的一第二表面；一第一導電層，位於該第一核心層的該第一表面上，該第一導電層包括多個第一連接墊；一第二導電層，位於該第一核心層的該第二表面 上，該第二導電層包括多個第二連接墊與多個接合墊；對該些第一連接墊與該些第二連接墊進行一表面處理製程，以在各該第一連接墊上形成一第一表面加工層，並在各該第二連接墊上形成一第二表面加工層；組裝至少一第一電子元件至該組裝架構模塊上，其中該至少一第一電子元件電性連接至該組裝架構模塊的該些接合墊；提供一凹穴架構模塊，其中該凹穴架構模塊包括：一第二核心層，具有一第三表面以及與該第三表面相對的一第四表面；一第三導電層，位於該第二核心層的該第三表面上，其中該第三導電層包括多個第三連接墊；對該些第三連接墊進行一表面處理製程，以在各該第三連接墊上形成一第三表面加工層；組裝至少一第二電子元件至該凹穴架構模塊，其中該至少一第二電子元件電性連接至該凹穴架構模塊；將一封膠填入該凹穴架構模塊的一凹穴，以包封該至少一第二電子元件；以及接合該凹穴架構模塊於該第三表面上的該第三表面加工層至該組裝架構模塊於該第二表面上的該些第二表面加工層，使得該至少一第一電子元件以及該至少一第二電子元件埋入由該凹穴架構模塊與該組裝架構模塊形成的該凹穴內的該封膠內。
  15. 如申請專利範圍第14項所述之封裝製程，其中接 合該凹穴架構模塊至該組裝架構模塊的方法包括藉由熱壓製程或超音波接合製程直接接合該凹穴架構模塊的該些第三表面加工層至該組裝架構模塊的該些第二表面加工層。
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