CN101937899B - 半导体封装结构及封装工艺 - Google Patents

半导体封装结构及封装工艺 Download PDF

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CN101937899B
CN101937899B CN2010102552075A CN201010255207A CN101937899B CN 101937899 B CN101937899 B CN 101937899B CN 2010102552075 A CN2010102552075 A CN 2010102552075A CN 201010255207 A CN201010255207 A CN 201010255207A CN 101937899 B CN101937899 B CN 101937899B
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structure module
conductive layer
assembling structure
electronic component
core layer
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CN101937899A (zh
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博德·K·艾皮特
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

本发明公开了一种具有内埋式电子元件的半导体封装结构及其封装工艺。通过两个以上预先形成的架构模块，可将电子元件组装置接合后的架构模块，以得到元件内埋式半导体封装结构。通过预先形成的架构模块可以简化具有内埋式电子元件的半导体封装结构的封装工艺，并且提供较大的工艺弹性。因此，可缩短半导体封装结构的组装时程，并提高其生产良率。

Description

半导体封装结构及封装工艺
技术领域
本发明涉及一种基板、半导体封装结构及其制作方法，且特别是涉及一种元件内埋式基板、应用此元件内埋式基板的半导体封装结构及其制作方法。
背景技术
一般而言，线路基板是由多个图案化线路层与多个介电层交替堆叠而成，其中介电层用以隔绝两相邻图案化线路层。相邻的图案化线路层可经由穿过介电层的镀通孔(plated through hole，PTH)或导电通孔(conductive via)相互电性连接。此外，各种电子元件(如有源或无源元件)可被设置于线路基板的表面或埋入线路基板，以通过内部线路的设计来达到电信号传递的目的。
为了满足市面上的电子产品轻量化与微型化的需求，更发展出采用内埋式基板的封装技术。然而，由于电子元件通常具有标准规格与特定的电气特性，为了容置各种电气特性的电子元件，元件内埋式基板必须客制化，而导致低工艺良率与较长的生产周期。
为促进此技术的发展，有必要简化元件内埋式基板的制作，以增加工艺良率并降低生产成本。
发明内容
本发明提出一种具有至少一电子元件的元件内埋式半导体封装结构的封装工艺，其可增进生产良率并降低制作成本与生产周期。
本发明提出一种具有至少一内埋式电子元件的半导体封装结构，或内埋至少一电子元件的基板。
本发明的实施例提出一种半导体封装结构，包括组装架构模块、间隔架构模块以及遮盖架构模块，其中组装架构模块上组装有至少一电子元件。间隔架构模块接合至组装架构模块以及遮盖架构模块。半导体封装结构还包括多个导电通孔，用以电性连接组装架构模块、间隔架构模块以及遮盖架构模块，以及封胶，填入组装架构模块、间隔架构模块以及遮盖架构模块接合后共同形成的凹穴中。所述至少一电子元件配置于凹穴内并且埋入封胶。
本发明的另一实施例提出一种半导体封装结构，包括组装架构模块，其上组装有至少一第一电子元件，以及凹穴架构模块，其上组装有至少一第二电子元件。凹穴架构模块接合至组装架构模块。半导体封装结构还包括多个导电通孔，用以电性连接组装架构模块以及凹穴架构模块，以及封胶，填入组装架构模块与凹穴架构模块接合后所形成的凹穴内。所述至少一第一电子元件以及所述至少一第二电子元件配置于凹穴内并且埋入封胶。
本发明的另一实施例提出一种具有内埋式电子元件的半导体封装结构的封装工艺。首先提供组装架构模块，其上组装至少一电子元件。接着，接合间隔架构模块至该组装架构模块，使所述至少一电子元件配置于接合后的间隔架构模块与组装架构模块共同形成的凹穴内。然后，在凹穴内填入封胶，以包封所述至少一电子元件。之后，接合遮盖架构模块至间隔架构模块，以密封凹穴。
本发明的另一实施例提出一种具有内埋式电子元件的半导体封装结构的封装工艺。首先，提供组装架构模块，并且组装至少一第一电子元件至组装架构模块上，其中所述至少一第一电子元件电性连接至组装架构模块。接着，提供凹穴架构模块，并且组装至少一第二电子元件至凹穴架构模块，其中所述至少一第二电子元件电性连接至凹穴架构模块。然后，将封胶填入凹穴架构模块的凹穴，以包封所述至少一第二电子元件。之后，接合凹穴架构模块至组装架构模块，使得所述至少一第一电子元件以及所述至少一第二电子元件配置于凹穴架构模块与组装架构模块形成的凹穴内，并且埋入封胶。
在本发明的实施例中，不同的架构模块之间可直接接合或是通过导电胶接合。
在本发明中，通过预先形成的架构模块可以简化具有内埋式电子元件的半导体封装结构的封装工艺，并且提供较大的工艺弹性。因此，可缩短半导体封装结构的组装时程，并提高其生产良率。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A至1D绘示依据本发明的实施例的一种基板的架构模块的制作流程。
图2绘示依据本发明的实施例的另一种基板的架构模块。
图3绘示依据本发明的实施例的另一种基板的架构模块。
图4A与4B绘示依据本发明的其他实施例的多种基板的架构模块。
图4C绘示依据本发明的实施例的一种元件内埋式基板的制作方法。
图5A-5D绘示依据本发明的实施例的一种具有内埋式元件的半导体封装结构的制作流程。
图6A与6B绘示依据本发明的另一实施例的一种具有内埋式元件的半导体封装结构的制作流程。
图7A与7B绘示依据本发明的实施例的一种具有内埋式元件的半导体封装结构的制作流程。
附图标记说明
10：组装架构模块
110：基板
112：顶部导电层
114：底部导电层
116：核心层
116a：核心层的顶面
116b：核心层的底面
120、120’：导电通孔
124、124’：图案化顶部导电层
126、126’：图案化底部导电层
124a、124a’：线路
124b、124b’：第一连接垫
126a、126a’：接合垫
126b、126b’：第二连接垫
130、130’：表面加工层
20：遮盖架构模块
30：间隔架构模块
30a：间隔架构模块的底面
316：核心层
320：导电通孔
324：图案化顶部导电层
324b：第一连接垫
326：图案化底部导电层
326b：第二连接垫
330：表面加工层
340：中空部分
40A：凹穴架构模块
40B：凹穴架构模块
400：元件内埋式基板
402：电子元件
404：凸块
406：接合垫
440：凹穴
50：半导体封装结构
502：电子元件
504：凸块
506：底填材料
508：封胶
540：凹穴
602：电子元件
604：焊线
608：封胶
640：凹穴
70：半导体封装结构
708：封胶
A：导电胶
具体实施方式
虽然在本申请中使用“第一”、“第二”或其他类似用语来描述元件、区域、膜层或部位，但该用语并非用来限定所述元件、区域、膜层或部位，而仅是用来区分不同的元件、区域、膜层或部位。因此，在不脱离本发明所教示的范围的情形下，所述第一元件、区域、膜层或部位也可能是第二元件、区域、膜层或部位。
本发明的实施例提出一种具有内埋式元件的半导体封装结构的制作方法，至少包括提供两个以上预先形成的架构模块(即，结构元件)，组装至少一电子元件(有源或无源元件)至所述架构模块中的至少一个上，并且接合所述架构模块，以得到元件内埋式半导体封装结构。由此，此封装工艺可提供较大的工艺弹性。
图1A至1D绘示依据本发明的实施例的一种基板的架构模块的制作流程。如图1A所示，提供基板110。基板110例如是多层线路板、双面层压结构(double-sided lamination structure)或覆铜箔层压板(copper clad laminate，CCL)。基板110至少包括顶部导电层112、底部导电层114以及核心层116。核心层116可由包括树脂与玻璃纤维的预浸材料所制成。顶部导电层112与底部导电层114分别设置于核心层116的顶面116a与底面116b。顶部导电层112与底部导电层114可由铜、铝、铝-铜合金或其他适当的导电材料制成。
同样地，虽然本发明中采用“顶(部)”、“底(部)”或其他类似用语来描述特定区域、表面或膜层，然该些用语仅适用来区分该些元件的相对位置，并非用来限定本发明。因此，在不脱离本发明所教示的范围的情形下，所述顶面或顶部膜层亦可为底面或底部膜层。
接着，如图1B所示，形成多个导电通孔120于基板110中。每一导电通孔120连接顶部导电层112与底部导电层114。因此，顶部导电层112通过导电通孔120电性连接至底部导电层114。导电通孔120可采用钻孔、化学镀铜或电镀等方式来形成。导电通孔120内可通过电镀填满铜，或仅是如一般的镀通孔内衬铜层。
如图1C所示，在形成导电通孔120之后，顶部导电层112与底部导电层114(如图1B所示)会被图案化，以分别形成图案化顶部导电层124以及图案化底部导电层126。顶部导电层112以及底部导电层114可通过光刻与蚀刻工艺来被图案化。
图案化顶部导电层124包括多条线路124a以及多个第一连接垫124b。图案化底部导电层126包括多个接合垫126a以及多个第二连接垫126b。第一连接垫124b以及第二连接垫126b通过导电通孔120相互电性连接。
如图1D所示，进行表面处理工艺以分别形成表面加工层130于图案化顶部导电层124以及图案化底部导电层126的表面上。表面加工层130例如是镍/金叠层，含银层或是含锡层。尤其，表面加工层130的材料可为化学镍钯浸金(electroless nickel electroless palladium immersion gold，ENEPIG)、化学镍金(electroless nickel immersion gold，ENIG)，化学浸银(immersion silver，iAg)、化学浸锡(immersion tin，iSn)，化学镀锡(electroless plating tin，eSn)或甚至有机保焊剂(organic solderability preservatives，OSP)。图1D绘示的架构模块可被视为组装架构模块10，其中图案化底部导电层126包括接合垫126a，适于与电子元件接合。
另外，若图1C的图案化工艺是采用不同的连接垫与线路设计，则如图2所示，图案化顶部导电层124’包括多条第一线路124a’以及多个第一连接垫124b’。图案化底部导电层126’包括多条第二线路126a’以及多个第二连接垫126b’。第一连接垫124b’以及第二连接垫126b’通过导电通孔120’相互电性连接，而表面加工层130’分别配置于图案化顶部导电层124’以及图案化底部导电层126’的表面。图2所示的架构模块可被视为遮盖架构模块20。组装架构模块10与遮盖架构模块20的不同处主要在于遮盖架构模块20不需要具有元件的接合垫，且可能被设计为仅具有单侧的导电图案。
图3绘示依据本发明的实施例的另一种基板的架构模块。接续类似图1A-1D所示的制作流程，可进行冲孔工艺来切除一部分的核心层316而形成至少一中空部分340。核心层316可包括具有内埋线路的预浸材料、多层层压板或覆铜箔层压板。图案化顶部导电层324包括多个第一连接垫324b，而图案化底部导电层326包括多个第二连接垫326b。导电通孔320连接第一连接垫324b以及第二连接垫326b，而表面加工层330可被分别设置于第一连接垫324b以及第二连接垫326b的表面。图3所示的架构模块可被视为间隔架构模块30，而中空部分340可承载装配的元件。
前述制作架构模块的工艺步骤并非用以限制本发明的范围，已知可供替换的工艺步骤皆可应用于本发明中，包括增层(additive)、减层(subtractive)或半增层(semi-additive)的叠层基板技术，以及无芯(coreless)基板技术等。
另外，虽然在此描述了三种架构模块，然本领域中普通技术人员在不脱离本发明的范围内应能通过改变膜层图案设计、材料或膜层数量来得到不同的架构模块。若需要单面的架构模块，也可对前述块状结构进一步加工，以移除一侧的导电图案。
前述架构模块也可相互接合以形成另一种架构模块。举例而言，如图4A所示，取决于两个架构模块的表面加工层的材料，组装架构模块10以及间隔架构模块30可选择通过超声波接合(ultrasonic bonding)或热压(thermalcompression)等技术直接相互接合，以形成凹穴架构模块40A。依据连接垫的金属表面处理的选择，前述架构模块也可以通过回焊技术来接合。另一方面，如图4B所示，组装架构模块10以及间隔架构模块30也可通过导电胶A相互接合，以形成凹穴架构模块40B。在此，组装架构模块10以及间隔架构模块30经由导电通孔120/320相互电性连接。
图4C绘示依据本发明的实施例的一种元件内埋式基板的制作方法。如图4C所示，提供如图4A或4B所示的凹穴架构模块40A或40B。此处以凹穴架构模块40B为例，并且将电子元件402组装至架构模块40A的接合垫406，使电子元件402位于凹穴440内。实际上，可选择在接合组装架构模块10与间隔架构模块30之前或之后来组装电子元件402。本发明所应用的电子元件可为有源元件，如芯片，或无源元件，如电容或电阻。本实施例的电子元件402例如是芯片，其通过例如倒装片接合技术通过多个凸块404电性连接至接合垫406。另外，电子元件402也可通过引线接合技术电性连接至接合垫406。由此，图4C所示的结构可被视为元件内埋式基板400。
图5A-5D绘示依据本发明的实施例的一种具有内埋式元件的半导体封装结构的制作流程。
如图5A所示，提供组装架构模块10，并且组装电子元件502至组装架构模块10的接合垫126a。本发明所应用的电子元件可为有源元件，如芯片，或无源元件，如电容或电阻。电子元件502例如是芯片，其通过例如倒装接合技术通过多个凸块504电性连接至接合垫126a。凸块504可为焊料凸块、金凸块或铜柱凸块。另一方面，电子元件502也可通过引线接合技术电性连接至接合垫126a(如图6A所示)。
如图5B所示，提供间隔架构模块30，并且将组装架构模块10连同组装的电子元件502接合至间隔架构模块30。在此，组装架构模块10(连同组装的电子元件502)可通过热压或超声波接合技术接合至间隔架构模块30。在接合组装架构模块10(连同组装的电子元件502)以及间隔架构模块30之后，组装的电子元件502会位于接合结构的凹穴540内。
另一方面，组装架构模块10(连同组装的电子元件502)以及间隔架构模块30也可通过导电胶(如图4B所示)来相互接合。
在接合工艺之前，可选择在凸块504周围形成底填材料506，以增进封装强度。然而，是否形成底填材料506是可选择的，并取决于电子元件或凸块的稳定性与可操纵性(handle ability)。
如图5C所示，在凹穴540内填入封胶508。在此，封胶508可略微突出于间隔架构模块30的底面30a，或是至少填满凹穴540。
如图5D所示，将遮盖架构模块20接合至间隔架构模块30的底面30a，以形成具有元件内埋式基板的半导体封装结构50。遮盖架构模块20可通过热压接合、超声波接合、回焊或应用导电胶接合等方式来接合至由组装架构模块10与间隔架构模块30所构成的接合结构。遮盖架构模块20、组装架构模块10以及间隔架构模块30可通过导电通孔120/320/120’相互电性连接。
另一方面，在另一实施例中，前述工艺步骤的顺序可被变更。如图6A所示，将遮盖架构模块20接合至间隔架构模块30的底面30a。遮盖架构模块20具有单面的导电图案。接着，封胶608被填入接合结构的凹穴640内。之后，提供组装架构模块10以及电子元件602，其中电子元件602可为无源元件，如电阻，并且电子元件602通过焊线604电性连接(引线接合)至组装架构模块10的接合垫126a。焊线604可为金线、铜线或铝线。
如图6B所示，组装架构模块10连同电子元件602被接合至由间隔架构模块30以及遮盖架构模块20构成的接合结构。其中，应注意控制封胶608的量，以确保接合后封胶608可填满凹穴640以及电子元件602周围的空隙。
图7A与7B绘示依据本发明的另一实施例的一种具有内埋式元件的半导体封装结构的制作流程。
如图7A所示，提供如图4C所示的元件内埋式基板400，并且将封胶708填入元件内埋式基板400的凹穴440，并填满电子元件402周围的空隙。换言之，即是将图4C所示的结构倒置。
如图7B所示，组装架构模块10连同电子元件502被接合至元件内埋式基板400(即，内埋有电子元件402的凹穴架构模块40A)，以形成具有元件内埋式基板400的半导体封装结构70。其中，应注意控制封胶708的量，以确保接合后封胶708可填满凹穴440以及电子元件402与502周围的空隙。
综上所述，通过预先形成的架构模块，可以简化元件内埋式基板的制作，以提高生产良率并降低的生产成本。另外，可在组装工艺前，先对预先形成的元件内埋式基板进行电性或功能性测试，以确保可靠度。
再者，应用本发明提出的各类型的架构模块或结合元件内埋式基板，可以得到芯片堆叠式半导体封装结构、多芯片半导体封装结构或甚至封装堆叠结构。
虽然本发明已以实施例披露如上，然其并非用以限定本发明，任何所属技术领域中普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附的权利要求所界定为准。

Claims (14)

1.一种半导体封装结构，包括：
组装架构模块，其上组装有至少一电子元件，其中该至少一电子元件电性连接至该组装架构模块，该组装架构模块包括：
第一核心层，具有第一表面以及与该第一表面相对的第二表面；
第一导电层，位于该第一核心层的该第一表面上；
第二导电层，位于该第一核心层的该第二表面上，其中该第二导电层包括多个接合垫以及多个第一连接垫；以及
间隔架构模块，接合至该组装架构模块，该间隔架构模块包括：
第二核心层，具有第三表面以及与该第三表面相对的第四表面；
第三导电层，位于该第二核心层的该第三表面上，其中该第三导电层包括多个第二连接垫；
第四导电层，位于该第二核心层的该第四表面上；
该间隔架构模块的所述多个第二连接垫与该组装架构模块的所述多个第一连接垫对应接合且相互电性连接；
遮盖架构模块，接合该间隔架构模块；以及多个导电通孔，电性连接该组装架构模块、该间隔架构模块以及该遮盖架构模块，其中该第一导电层、该第二导电层、该第三导电层以及该第四导电层是通过所述多个导电通孔相互电性连接；以及
封胶，填充凹穴，该凹穴为该组装架构模块、该间隔架构模块以及该遮盖架构模块接合后共同形成，其中该至少一电子元件配置于该凹穴内并且埋入该封胶。
2.如权利要求1所述的半导体封装结构，其中该至少一电子元件是通过多个凸块电性接合至该组装架构模块的该多个接合垫。
3.如权利要求2所述的半导体封装结构，还包括包围该多个凸块设置的底填材料。
4.一种封装工艺，包括：
提供组装架构模块，该组装架构模块包括：
第一核心层，具有第一表面以及与该第一表面相对的第二表面；
第一导电层，位于该第一核心层的该第一表面上；
第二导电层，位于该第一核心层的该第二表面上，其中该第二导电层包括多个接合垫以及多个第一连接垫；以及
第一导电通孔，贯穿该第一核心层，并且电性连接该第一导电层以及该第二导电层；
组装至少一电子元件至该组装架构模块上，其中该至少一电子元件经由该些接合垫电性连接至该组装架构模块；
接合间隔架构模块至该组装架构模块，使得该至少一电子元件设置于该间隔架构模块与该组装架构模块共同形成的凹穴内，其中，该间隔架构模块包括：
第二核心层，具有第三表面以及与该第三表面相对的第四表面；
第三导电层，位于该第二核心层的该第三表面上，其中该第三导电层包括多个第二连接垫；
第四导电层，位于该第二核心层的该第四表面上；以及
第二导电通孔，贯穿该第二核心层，并且电性连接该第三导电层以及该第四导电层，该间隔架构模块的所述多个第二连接垫与该组装架构模块的所述多个第一连接垫对应接合且相互电性连接；
将封胶填入该凹穴内以包封该至少一电子元件；以及
接合遮盖架构模块至该间隔架构模块，以密封该凹穴。
5.如权利要求4所述的封装工艺，其中接合该间隔架构模块至该组装架构模块的方法包括通过热压工艺或超声波接合工艺直接接合该间隔架构模块至该组装架构模块。
6.如权利要求4所述的封装工艺，其中接合该间隔架构模块至该组装架构模块的方法包括应用导电胶来粘合该间隔架构模块与该组装架构模块。
7.如权利要求4所述的封装工艺，还包括在填充该凹穴之前，形成环绕该至少一电子元件的底填材料。
8.如权利要求4所述的封装工艺，其中接合该遮盖架构模块至该间隔架构模块的方法包括通过热压工艺或超声波接合工艺直接接合该间隔架构模块至该遮盖架构模块。
9.如权利要求4所述的封装工艺，其中接合该遮盖架构模块至该间隔架构模块的方法包括应用导电胶来粘合该间隔架构模块与该遮盖架构模块。
10.一种半导体封装结构，包括：
组装架构模块，其上组装有至少一第一电子元件，其中该第一电子元件电性连接至该组装架构模块，该组装架构模块包括：
第一核心层，具有第一表面以及与该第一表面相对的第二表面；
第一导电层，位于该第一核心层的该第一表面上；
第二导电层，位于该第一核心层的该第二表面上，其中该第二导电层包括多个第一接合垫以及多个第一连接垫；以及
第二组装架构模块，其上组装有至少一第二电子元件，其中该第二电子元件电性连接至该第二组装架构模块，该第二组装架构模块包括：
第二核心层，具有第三表面以及与该第三表面相对的第四表面；
第三导电层，位于该第二核心层的该第三表面上，其中该第三导电层包括多个第二接合垫以及多个第二连接垫；
第四导电层，位于该第二核心层的该第四表面上；以及
间隔架构模块，夹置并接合于该第一组装架构模块以及该第二组装架构模块之间，以形成凹穴，该至少一第一电子元件以及该至少一第二电子元件位于该凹穴内，该间隔架构模块包括：
第三核心层，具有第五表面以及与该第五表面相对的第六表面；
第五导电层，位于该第三核心层的该第五表面上，且该第五导电层包括多个第三连接垫；
第六导电层，位于该第三核心层的该第六表面上，且该第六导电层包括多个第四连接垫；
该间隔架构模块的所述多个第三连接垫与该第一组装架构模块的所述多个第一连接垫对应接合且相互电性连接，且该间隔架构模块的所述多个第四连接垫与该第二组装架构模块的所述多个第二连接垫对应接合且相互电性连接；以及
多个导电通孔，电性连接该组装架构模块以及该凹穴架构模块，其中该第一导电层、该第二导电层、该第三导电层、该第四导电层、该第五导电层以及该第六导电层是通过所述多个导电通孔相互电性连接；以及封胶，填入该凹穴，以包封该至少一第一电子元件以及该至少一第二电子元件。
11.如权利要求10所述的半导体封装结构，其中该至少一第一电子元件通过多个第一凸块电性连接至该第一组装架构模块的该多个第一连接垫，而该至少一第二电子元件通过多个第二凸块电性连接至该第二组装架构模块的该多个第二连接垫。
12.如权利要求10所述的半导体封装结构，其中该至少一第一电子元件通过多条第一焊线电性连接至该第一组装架构模块的该多个第一连接垫，而该至少一第二电子元件通过多条第二焊线电性连接至该第二组装架构模块的该多个第二连接垫。
13.一种封装工艺，包括：
提供第一组装架构模块，该第一组装架构模块包括：
第一核心层，具有第一表面以及与该第一表面相对的第二表面；
第一导电层，位于该第一核心层的该第一表面上；
第二导电层，位于该第一核心层的该第二表面上，其中该第二导电层包括多个第一接合垫以及多个第一连接垫；以及
第一导电通孔，贯穿该第一核心层，并且电性连接该第一导电层以及该第二导电层；
组装至少一第一电子元件至该第一组装架构模块上，其中该至少一第一电子元件电性连接至该第一组装架构模块；
提供预先形成的凹穴架构模块，该凹穴架构模块包括第二组装架构模块以及间隔架构模块，且该第二组装架构模块以及该间隔架构模块形成凹穴，
该第二组装架构模块包括：
第二核心层，具有第三表面以及与该第三表面相对的第四表面；
第三导电层，位于该第二核心层的该第三表面上，其中该第三导电层包括多个第二接合垫以及多个第二连接垫；
第四导电层，位于该第二核心层的该第四表面上；以及
第二导电通孔，贯穿该第二核心层，并且电性连接该第三导电层以及该第四导电层，
该间隔架构模块包括：
第三核心层，具有第五表面以及与该第五表面相对的第六表面；
第五导电层，位于该第三核心层的该第五表面上，且该第五导电层包括多个第三连接垫；
第六导电层，位于该第三核心层的该第六表面上，且该第六导电层包括多个第四连接垫；以及
第三导电通孔，贯穿该第三核心层，并且电性连接该第五导电层以及该第六导电层，该间隔架构模块的所述多个第四连接垫与该第二组装架构模块的所述多个第二连接垫对应接合且相互电性连接；
组装至少一第二电子元件至该第二组装架构模块，其中该至少一第二电子元件电性连接至该第二组装架构模块；
将封胶填入该凹穴架构模块的凹穴，以包封该至少一第二电子元件；以及
接合该凹穴架构模块至该组装架构模块，使得该至少一第一电子元件以及该至少一第二电子元件埋入该封胶内，其中该间隔架构模块的所述多个第三连接垫与该第一组装架构模块的所述多个第一连接垫对应接合且相互电性连接。
14.如权利要求13所述的封装工艺，其中接合该凹穴架构模块至该组装架构模块的方法包括通过热压工艺或超声波接合工艺直接接合该凹穴架构模块至该组装架构模块。
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