TWI440083B - 脈衝超高縱橫尺寸比之介電材料蝕刻 - Google Patents

脈衝超高縱橫尺寸比之介電材料蝕刻 Download PDF

Info

Publication number
TWI440083B
TWI440083B TW097104575A TW97104575A TWI440083B TW I440083 B TWI440083 B TW I440083B TW 097104575 A TW097104575 A TW 097104575A TW 97104575 A TW97104575 A TW 97104575A TW I440083 B TWI440083 B TW I440083B
Authority
TW
Taiwan
Prior art keywords
etching
gas
source
selective
dielectric layer
Prior art date
Application number
TW097104575A
Other languages
English (en)
Chinese (zh)
Other versions
TW200849377A (en
Inventor
秦孔固
依德柏格 艾瑞克A
Original Assignee
蘭姆研究公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 蘭姆研究公司 filed Critical 蘭姆研究公司
Publication of TW200849377A publication Critical patent/TW200849377A/zh
Application granted granted Critical
Publication of TWI440083B publication Critical patent/TWI440083B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Plasma Technology (AREA)
TW097104575A 2007-02-05 2008-02-05 脈衝超高縱橫尺寸比之介電材料蝕刻 TWI440083B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/671,342 US7547636B2 (en) 2007-02-05 2007-02-05 Pulsed ultra-high aspect ratio dielectric etch

Publications (2)

Publication Number Publication Date
TW200849377A TW200849377A (en) 2008-12-16
TWI440083B true TWI440083B (zh) 2014-06-01

Family

ID=39676541

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097104575A TWI440083B (zh) 2007-02-05 2008-02-05 脈衝超高縱橫尺寸比之介電材料蝕刻

Country Status (6)

Country Link
US (1) US7547636B2 (enExample)
JP (2) JP5503976B2 (enExample)
KR (1) KR101455883B1 (enExample)
CN (1) CN101606232B (enExample)
TW (1) TWI440083B (enExample)
WO (1) WO2008097925A1 (enExample)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070218691A1 (en) * 2006-03-17 2007-09-20 Tokyo Electron Limited Plasma etching method, plasma etching apparatus and computer-readable storage medium
US9059116B2 (en) * 2007-11-29 2015-06-16 Lam Research Corporation Etch with pulsed bias
US8609546B2 (en) * 2007-11-29 2013-12-17 Lam Research Corporation Pulsed bias plasma process to control microloading
KR101522251B1 (ko) * 2008-09-22 2015-05-21 어플라이드 머티어리얼스, 인코포레이티드 고 종횡비 피쳐들을 식각하기에 적합한 식각 반응기
US8383001B2 (en) * 2009-02-20 2013-02-26 Tokyo Electron Limited Plasma etching method, plasma etching apparatus and storage medium
US8475673B2 (en) * 2009-04-24 2013-07-02 Lam Research Company Method and apparatus for high aspect ratio dielectric etch
US8394723B2 (en) * 2010-01-07 2013-03-12 Lam Research Corporation Aspect ratio adjustment of mask pattern using trimming to alter geometry of photoresist features
JP2012079792A (ja) * 2010-09-30 2012-04-19 Fujitsu Semiconductor Ltd 半導体装置の製造方法
TWI478234B (zh) * 2011-03-04 2015-03-21 東京威力科創股份有限公司 氮化矽膜之蝕刻方法
US8420545B2 (en) * 2011-05-23 2013-04-16 Nanya Technology Corporation Plasma etching method and plasma etching apparatus for preparing high-aspect-ratio structures
JP5802454B2 (ja) * 2011-06-30 2015-10-28 株式会社日立ハイテクノロジーズ プラズマ処理方法
US20130119018A1 (en) * 2011-11-15 2013-05-16 Keren Jacobs Kanarik Hybrid pulsing plasma processing systems
US9224618B2 (en) * 2012-01-17 2015-12-29 Lam Research Corporation Method to increase mask selectivity in ultra-high aspect ratio etches
US20140051256A1 (en) * 2012-08-15 2014-02-20 Lam Research Corporation Etch with mixed mode pulsing
TWI584374B (zh) 2012-09-18 2017-05-21 東京威力科創股份有限公司 Plasma etching method and plasma etching device
JP6267953B2 (ja) * 2013-12-19 2018-01-24 東京エレクトロン株式会社 半導体装置の製造方法
US9159561B2 (en) * 2013-12-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning
JP6315809B2 (ja) * 2014-08-28 2018-04-25 東京エレクトロン株式会社 エッチング方法
SG11201901207TA (en) * 2016-09-14 2019-04-29 Mattson Tech Inc Strip process for high aspect ratio structure
US10134600B2 (en) 2017-02-06 2018-11-20 Lam Research Corporation Dielectric contact etch
JP6840041B2 (ja) * 2017-06-21 2021-03-10 東京エレクトロン株式会社 エッチング方法
JP2019102483A (ja) * 2017-11-28 2019-06-24 東京エレクトロン株式会社 エッチング方法およびエッチング装置
KR102799403B1 (ko) * 2018-02-05 2025-04-22 램 리써치 코포레이션 비정질 탄소 층 개방 프로세스
US10504744B1 (en) 2018-07-19 2019-12-10 Lam Research Corporation Three or more states for achieving high aspect ratio dielectric etch
US12266535B2 (en) 2019-10-01 2025-04-01 Lam Researh Corporation Mask encapsulation to prevent degradation during fabrication of high aspect ratio features
CN113035706A (zh) * 2019-12-25 2021-06-25 中微半导体设备(上海)股份有限公司 一种等离子体刻蚀方法和刻蚀装置
JP7462444B2 (ja) * 2020-03-19 2024-04-05 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
US12266534B2 (en) * 2020-06-15 2025-04-01 Tokyo Electron Limited Forming a semiconductor device using a protective layer
JP7650349B2 (ja) * 2021-04-14 2025-03-24 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
US11495470B1 (en) * 2021-04-16 2022-11-08 Applied Materials, Inc. Method of enhancing etching selectivity using a pulsed plasma
TW202538865A (zh) * 2024-02-22 2025-10-01 日商東京威力科創股份有限公司 基板處理方法及基板處理系統

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687543A (en) 1986-02-21 1987-08-18 Tegal Corporation Selective plasma etching during formation of integrated circuitry
JP3239460B2 (ja) * 1992-09-08 2001-12-17 ソニー株式会社 接続孔の形成方法
US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
US20010051438A1 (en) 1997-06-25 2001-12-13 Samsung Electronics Process and apparatus for dry-etching a semiconductor layer
JP3336975B2 (ja) * 1998-03-27 2002-10-21 日本電気株式会社 基板処理方法
US6284149B1 (en) * 1998-09-18 2001-09-04 Applied Materials, Inc. High-density plasma etching of carbon-based low-k materials in a integrated circuit
JP4153606B2 (ja) * 1998-10-22 2008-09-24 東京エレクトロン株式会社 プラズマエッチング方法およびプラズマエッチング装置
JP4408313B2 (ja) * 1999-10-29 2010-02-03 東京エレクトロン株式会社 プラズマ処理装置およびプラズマ処理方法
KR100327346B1 (ko) 1999-07-20 2002-03-06 윤종용 선택적 폴리머 증착을 이용한 플라즈마 식각방법 및 이를이용한 콘택홀 형성방법
US6147005A (en) 1999-07-23 2000-11-14 Worldwide Semiconductor Manufacturing Corp. Method of forming dual damascene structures
US6368974B1 (en) 1999-08-02 2002-04-09 United Microelectronics Corp. Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching
JP2001332510A (ja) * 2000-05-25 2001-11-30 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6831018B2 (en) 2001-08-21 2004-12-14 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
US20030153195A1 (en) * 2002-02-13 2003-08-14 Applied Materials, Inc. Method and apparatus for providing modulated bias power to a plasma etch reactor
US6759340B2 (en) 2002-05-09 2004-07-06 Padmapani C. Nallan Method of etching a trench in a silicon-on-insulator (SOI) structure
US6916746B1 (en) * 2003-04-09 2005-07-12 Lam Research Corporation Method for plasma etching using periodic modulation of gas chemistry
US20050112891A1 (en) 2003-10-21 2005-05-26 David Johnson Notch-free etching of high aspect SOI structures using a time division multiplex process and RF bias modulation
CN101124661A (zh) * 2004-05-11 2008-02-13 应用材料公司 碳氟化合物蚀刻化学剂中使用氢气添加剂的掺碳的硅氧化物蚀刻
US7344975B2 (en) 2005-08-26 2008-03-18 Micron Technology, Inc. Method to reduce charge buildup during high aspect ratio contact etch
US7432210B2 (en) * 2005-10-05 2008-10-07 Applied Materials, Inc. Process to open carbon based hardmask
US7531102B2 (en) 2006-03-31 2009-05-12 Intel Corporation Simultaneous selective polymer deposition and etch pitch doubling for sub 50nm line/space patterning

Also Published As

Publication number Publication date
JP5503976B2 (ja) 2014-05-28
TW200849377A (en) 2008-12-16
CN101606232A (zh) 2009-12-16
US7547636B2 (en) 2009-06-16
KR20090125076A (ko) 2009-12-03
JP2013239729A (ja) 2013-11-28
CN101606232B (zh) 2013-01-23
WO2008097925A1 (en) 2008-08-14
JP2010518605A (ja) 2010-05-27
US20080188082A1 (en) 2008-08-07
KR101455883B1 (ko) 2014-11-03

Similar Documents

Publication Publication Date Title
TWI407504B (zh) 超高縱橫尺寸比之介電材料蝕刻
JP5503976B2 (ja) 超高アスペクト比の誘電体パルスエッチング
CN101779276B (zh) 掩模修整
JP5254351B2 (ja) 酸化物スペーサを使用したピッチ低減
TWI381427B (zh) 臨界尺寸縮減及粗糙度控制
CN100543946C (zh) 蚀刻掩模特征临界尺寸的减小
TWI496212B (zh) 包含光阻遮罩預處理之電漿製程
JP4886513B2 (ja) フィーチャ微小寸法の低減
CN102150244B (zh) 侧壁形成工艺
CN101779277B (zh) 用于蚀刻设在反射层下方的介电层的方法和设备
TWI545648B (zh) 擬硬遮罩用之擺動控制
JP2012124535A (ja) 複数のマスキングステップを用いて微小寸法を低減する方法
JP2012151510A (ja) エッチングプロセスのための安定化したフォトレジスト構成
WO2009099769A2 (en) Double mask self-aligned double patterning technology (sadpt) process
TWI424490B (zh) 垂直輪廓修正
JP2007503728A (ja) 改良されたバイレイヤフォトレジストパターンを提供する方法