CN101606232B - 脉冲超高纵横比电介质蚀刻 - Google Patents

脉冲超高纵横比电介质蚀刻 Download PDF

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Publication number
CN101606232B
CN101606232B CN2008800041803A CN200880004180A CN101606232B CN 101606232 B CN101606232 B CN 101606232B CN 2008800041803 A CN2008800041803 A CN 2008800041803A CN 200880004180 A CN200880004180 A CN 200880004180A CN 101606232 B CN101606232 B CN 101606232B
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China
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gas
source
etching
etch
selective etch
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CN2008800041803A
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Chinese (zh)
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CN101606232A (zh
Inventor
池贞浩
埃里克·A·埃德尔伯格
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Pan Lin Semiconductor Equipment Technology (shanghai) Co Ltd
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Lam Research Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Plasma Technology (AREA)
CN2008800041803A 2007-02-05 2008-02-04 脉冲超高纵横比电介质蚀刻 Active CN101606232B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/671,342 2007-02-05
US11/671,342 US7547636B2 (en) 2007-02-05 2007-02-05 Pulsed ultra-high aspect ratio dielectric etch
PCT/US2008/052950 WO2008097925A1 (en) 2007-02-05 2008-02-04 Pulsed ultra-high aspect ratio dielectric etch

Publications (2)

Publication Number Publication Date
CN101606232A CN101606232A (zh) 2009-12-16
CN101606232B true CN101606232B (zh) 2013-01-23

Family

ID=39676541

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008800041803A Active CN101606232B (zh) 2007-02-05 2008-02-04 脉冲超高纵横比电介质蚀刻

Country Status (6)

Country Link
US (1) US7547636B2 (enExample)
JP (2) JP5503976B2 (enExample)
KR (1) KR101455883B1 (enExample)
CN (1) CN101606232B (enExample)
TW (1) TWI440083B (enExample)
WO (1) WO2008097925A1 (enExample)

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US20070218691A1 (en) * 2006-03-17 2007-09-20 Tokyo Electron Limited Plasma etching method, plasma etching apparatus and computer-readable storage medium
WO2009073361A1 (en) * 2007-11-29 2009-06-11 Lam Research Corporation Pulsed bias plasma process to control microloading
US9059116B2 (en) * 2007-11-29 2015-06-16 Lam Research Corporation Etch with pulsed bias
WO2010033924A2 (en) * 2008-09-22 2010-03-25 Applied Materials, Inc. Etch reactor suitable for etching high aspect ratio features
US8383001B2 (en) * 2009-02-20 2013-02-26 Tokyo Electron Limited Plasma etching method, plasma etching apparatus and storage medium
US8475673B2 (en) * 2009-04-24 2013-07-02 Lam Research Company Method and apparatus for high aspect ratio dielectric etch
US8394723B2 (en) * 2010-01-07 2013-03-12 Lam Research Corporation Aspect ratio adjustment of mask pattern using trimming to alter geometry of photoresist features
JP2012079792A (ja) * 2010-09-30 2012-04-19 Fujitsu Semiconductor Ltd 半導体装置の製造方法
US20130344702A1 (en) * 2011-03-04 2013-12-26 Tokyo Electron Limited Method of etching silicon nitride films
US8420545B2 (en) * 2011-05-23 2013-04-16 Nanya Technology Corporation Plasma etching method and plasma etching apparatus for preparing high-aspect-ratio structures
JP5802454B2 (ja) * 2011-06-30 2015-10-28 株式会社日立ハイテクノロジーズ プラズマ処理方法
US20130119018A1 (en) * 2011-11-15 2013-05-16 Keren Jacobs Kanarik Hybrid pulsing plasma processing systems
US9224618B2 (en) * 2012-01-17 2015-12-29 Lam Research Corporation Method to increase mask selectivity in ultra-high aspect ratio etches
US20140051256A1 (en) * 2012-08-15 2014-02-20 Lam Research Corporation Etch with mixed mode pulsing
KR102099408B1 (ko) 2012-09-18 2020-04-10 도쿄엘렉트론가부시키가이샤 플라즈마 에칭 방법 및 플라즈마 에칭 장치
JP6267953B2 (ja) * 2013-12-19 2018-01-24 東京エレクトロン株式会社 半導体装置の製造方法
US9159561B2 (en) * 2013-12-26 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning
JP6315809B2 (ja) * 2014-08-28 2018-04-25 東京エレクトロン株式会社 エッチング方法
US10599039B2 (en) * 2016-09-14 2020-03-24 Mattson Technology, Inc. Strip process for high aspect ratio structure
US10134600B2 (en) 2017-02-06 2018-11-20 Lam Research Corporation Dielectric contact etch
JP6840041B2 (ja) * 2017-06-21 2021-03-10 東京エレクトロン株式会社 エッチング方法
JP2019102483A (ja) * 2017-11-28 2019-06-24 東京エレクトロン株式会社 エッチング方法およびエッチング装置
US11037784B2 (en) * 2018-02-05 2021-06-15 Lam Research Corporation Amorphous carbon layer opening process
US10504744B1 (en) 2018-07-19 2019-12-10 Lam Research Corporation Three or more states for achieving high aspect ratio dielectric etch
JP2022550057A (ja) * 2019-10-01 2022-11-30 ラム リサーチ コーポレーション 高アスペクト比フィーチャの製造中に劣化を防止するためのマスク封入
CN113035706A (zh) * 2019-12-25 2021-06-25 中微半导体设备(上海)股份有限公司 一种等离子体刻蚀方法和刻蚀装置
JP7462444B2 (ja) * 2020-03-19 2024-04-05 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
US12266534B2 (en) 2020-06-15 2025-04-01 Tokyo Electron Limited Forming a semiconductor device using a protective layer
JP7650349B2 (ja) * 2021-04-14 2025-03-24 東京エレクトロン株式会社 エッチング方法及びプラズマ処理装置
US11495470B1 (en) * 2021-04-16 2022-11-08 Applied Materials, Inc. Method of enhancing etching selectivity using a pulsed plasma
WO2025177876A1 (ja) * 2024-02-22 2025-08-28 東京エレクトロン株式会社 基板処理方法及び基板処理システム

Citations (3)

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US6368974B1 (en) * 1999-08-02 2002-04-09 United Microelectronics Corp. Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching
US6617253B1 (en) * 1999-07-20 2003-09-09 Samsung Electronics Co., Ltd. Plasma etching method using polymer deposition and method of forming contact hole using the plasma etching method
US6759340B2 (en) * 2002-05-09 2004-07-06 Padmapani C. Nallan Method of etching a trench in a silicon-on-insulator (SOI) structure

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US4687543A (en) 1986-02-21 1987-08-18 Tegal Corporation Selective plasma etching during formation of integrated circuitry
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US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
US20010051438A1 (en) 1997-06-25 2001-12-13 Samsung Electronics Process and apparatus for dry-etching a semiconductor layer
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JP4408313B2 (ja) * 1999-10-29 2010-02-03 東京エレクトロン株式会社 プラズマ処理装置およびプラズマ処理方法
US6147005A (en) 1999-07-23 2000-11-14 Worldwide Semiconductor Manufacturing Corp. Method of forming dual damascene structures
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US6617253B1 (en) * 1999-07-20 2003-09-09 Samsung Electronics Co., Ltd. Plasma etching method using polymer deposition and method of forming contact hole using the plasma etching method
US6368974B1 (en) * 1999-08-02 2002-04-09 United Microelectronics Corp. Shrinking equal effect critical dimension of mask by in situ polymer deposition and etching
US6759340B2 (en) * 2002-05-09 2004-07-06 Padmapani C. Nallan Method of etching a trench in a silicon-on-insulator (SOI) structure

Also Published As

Publication number Publication date
KR20090125076A (ko) 2009-12-03
JP2010518605A (ja) 2010-05-27
US20080188082A1 (en) 2008-08-07
CN101606232A (zh) 2009-12-16
JP5503976B2 (ja) 2014-05-28
WO2008097925A1 (en) 2008-08-14
TW200849377A (en) 2008-12-16
KR101455883B1 (ko) 2014-11-03
TWI440083B (zh) 2014-06-01
JP2013239729A (ja) 2013-11-28
US7547636B2 (en) 2009-06-16

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Owner name: LAM SEMICONDUCTOR EQUIPMENT TECHNOLOGY ( SHANGHAI

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Patentee after: Pan Lin semiconductor equipment technology (Shanghai) Co., Ltd.

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Patentee before: Lam Research Corp.