TWI438899B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI438899B
TWI438899B TW098105461A TW98105461A TWI438899B TW I438899 B TWI438899 B TW I438899B TW 098105461 A TW098105461 A TW 098105461A TW 98105461 A TW98105461 A TW 98105461A TW I438899 B TWI438899 B TW I438899B
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conductive type
trenches
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Masayuki Hashitani
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Seiko Instr Inc
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Description

半導體裝置及其製造方法
本發明關於一種半導體裝置及製造該半導體記憶體裝置的方法。特別是，本發明關於一種具有一溝渠之MOS電晶體，其利用一埋入層以增強驅動性能。
一MOS電晶體係一設在電子組件核芯處之裝置，因此，MOS電晶體之縮小化、功率消耗減低、及驅動性能增強即為重要課題。作為一增強MOS電晶體驅動性能之方法，目前已有一種關於將一閘極寬度變大之方法，藉此減小導通電阻。惟，閘極寬度變大會導致一項問題產生，亦即MOS電晶體之一佔用面積變大。有鑑於是項問題，目前所提出之一項技術為閘極寬度不僅變大，同時可以利用一溝渠而抑制MOS電晶體之佔用面積增加。
請參閱圖4A至4D，其說明一習知半導體裝置。
如圖4A之立體圖中所示，在一MOS電晶體之寬度方向中(W方向)設有一溝渠13，其中一有效閘極寬度之長度較大於一閘極電極15在一表面上之寬度，藉此使單位面積之一導通電阻得以減小，且不致於降低MOS電晶體之耐電壓。
圖4B係MOS電晶體之概略平面圖。圖4D及圖4C中分別說明以A-A’表示之溝渠13之截面及以B-B’表示之一無溝渠13的區域之截面。圖4C中所示之一區域成為一常態下呈平面形之MOS電晶體，且因此，當一電流從一高濃度源極擴散層16流到一高濃度汲極擴散層17時，一電流路徑即如圖4C中之箭頭A所示。另方面，在具有溝渠13的區域中，如圖4D中所示，電流係在一如箭頭B所示之MOS電晶體寬度方向中與紙面平行的側表面上及一如箭頭C所示的底部上取得。(例如，請參閱JP 2006-49826 A)
惟，在習知技術中，在一電晶體長度L減小以利於達成較為增強之驅動性能的例子中，可以明顯觀察到有效通道長度之一距離差異。在圖4D之路徑C及圖4C之路徑A中，主要為一由路徑A所示之平面區，且電流幾乎不流入底部C。因此，其產生一問題在於即使溝渠13深入地形成且一有效閘極寬度之長度加大，以便減小導通電阻時，仍未能取得驅動性能。此外，由於電晶體之一閘極長度(L方向)無法減小，因而發生面積無法減小的困擾。
如上所述，在圖4A之結構中，即使是一溝渠深度變得較大或閘極寬度(W方向)減小以令有效閘極寬度變長時，閘極長度(L長度方向)無法減小。因此，其產生一問題在於驅動性能根本無法取得，或一問題在於電晶體面積無法減小。這是因為在溝渠之一頂表面、一側表面、及一底表面之間之有效通道長度差異由於L長度減小而可明顯看出，一電流優先流過溝渠之頂表面，且在底表面上流動之電流減少，此係溝渠設置上之一特性。
本發明具有一目的，即在溝渠之一底表面上取得一電流路徑，及取得一所想要的驅動性能，亦即，其抑制驅動性能之減低，即使是在一半導體裝置中具有一溝渠的MOS電晶體之一長度L減小時。
為了達成上述目的，本發明採用以下方法。
(1)一種半導體裝置，其包括：一第一傳導性型半導體基板；一第二傳導性型埋入層，其形成於該第一傳導性型半導體基板上之一預定區域中；一第一傳導性型磊晶生長層，其形成於該第二傳導性型埋入層及該第一傳導性型半導體基板上；複數個溝渠，其形成於該第一傳導性型磊晶生長層中且在一待形成電晶體之一閘極寬度方向中呈並列配置，及其具有一底部且到達該第二傳導性型埋入層；一閘極電極，其形成於各該溝渠內側，且藉由一閘極絕緣膜而形成於各該溝渠之一頂表面上及與各該溝渠相鄰之該第一傳導性型磊晶生長層之一表面上；一第二傳導性型高濃度源極擴散層，其形成於該閘極電極之一側面上；及一第二傳導性型高濃度汲極擴散層，其形成於該閘極電極之另一側面上。
(2)一種製造一半導體裝置之方法，其包括：形成一第二傳導性型埋入層於一第一傳導性型半導體基板上之一預定區域中；形成一第一傳導性型磊晶生長層於該第二傳導性型埋入層及該第一傳導性型半導體基板上；形成複數個溝渠於該第一傳導性型磊晶生長層中，且在一待形成電晶體之一閘極寬度方向中呈並列配置，使得各該溝渠之一底部到達該第二傳導性型埋入層；形成一閘極絕緣膜；形成一閘極電極於各該溝渠內側，且藉由該閘極絕緣膜而形成於各該溝渠之一頂表面上及與各該溝渠相鄰之該第一傳導性型磊晶生長層之一表面上；及形成一第二傳導性型高濃度源極擴散層於該閘極電極之一側面上，及形成一第二傳導性型高濃度汲極擴散層於該閘極電極之另一側面上。
本發明具有一項特性，亦即，即使是具有一溝渠的MOS電晶體之長度L減小時，驅動性能方面之降低仍可被抑制。本發明提供一具有距離相等於或小於MOS電晶體長度L之深度的溝渠，及一埋入層係用於該溝渠之一底部，藉此使得從一高濃度源極擴散層下端部及一高濃度汲極擴散層下端部各者到該溝渠底表面的一有效通道長度較短於該溝渠頂表面上的最短長度L。據此，一電流路徑即從該溝渠之一側表面保持在其底表面上，該側表面利用該埋入層而與該源極或該高濃度汲極擴散層接觸，藉此使驅動性能得以增強。結果，其產生一項抑制驅動性能降低的效果，即使是在閘極長度減小時。
下文中，本發明之實施例即參考圖式而說明。
圖1A至1C係概略圖，其說明根據本發明第一實施例之一半導體裝置。圖1A係一具有一溝渠6之MOS電晶體之概略平面圖。圖1B係沿線A-A’所取之概略截面圖，其對應於一不包括圖1A之溝渠6在內的平面形電晶體結構。圖1C係沿圖1A之溝渠6之線B-B’所取之概略截面圖。在圖1B中，僅在一第一傳導性型半導體基板1上之一預定區域中局部性形成一第二傳導性型埋入層2，且一具有與半導體基板者相同傳導性型之磊晶生長層3形成於其上。一具有一閘極長度L之閘極電極8通過一閘極絕緣膜7而形成於磊晶生長層3之一頂表面上。同時形成複數個區域，其相對立於彼此且間隔為閘極電極8之閘極長度L，該區域包括一區域以供一第二傳導性型高濃度源極擴散層9形成於其中，及另一區域以供一第二傳導性型高濃度汲極擴散層10形成於其中。在此例子中，高濃度源極擴散層9與高濃度汲極擴散層10之間之一電流路徑係以圖1B中之箭頭A說明。
圖1C係一具有溝渠6之區域之截面圖。在第一傳導性型半導體基板1上局部性形成第二傳導性型埋入層2，且具有與半導體基板者相同傳導性型之磊晶生長層3形成於其上。在磊晶生長層3中設有溝渠6，以便與埋入層2接觸。當埋入層2之一長度及溝渠6之一長度係在一閘極長度方向中於彼此比較時，一等於或較長於溝渠6長度之長度即足夠用於埋入層2。高濃度源極擴散層9及高濃度汲極擴散層10係形成於溝渠6之側表面上，且閘極絕緣膜7形成於溝渠6之一內表面上、高濃度源極擴散層9之一表面上、及高濃度汲極擴散層10之一表面上。溝渠6係以閘極電極8充填。在此結構中，以下二電流路徑即可以想見：其中一者係一以箭頭B表示之電流路徑及另一者係一從高濃度源極擴散層9經過一以箭頭D表示之路徑、埋入層2、一以箭頭E表示之路徑，而到達理入層2之電流路徑(下文稱為一電流路徑C’)。在此例子中，當高濃度源極擴散層9與埋入層2之間之一距離(其等於高濃度汲極擴散層10與埋入層2之間之一距離)係一等於或較短於閘極長度之長度時，一電流即可能也在電流路徑C’中流動。藉由此結構，MOS電晶體之驅動性能得以增強。
圖2A至2F係用於製造本發明第一實施例之半導體裝置的流程圖。在此，與圖1C相對應之截面圖係用於說明。
在圖2A中，首先，在第一傳導性型半導體基板上(例如，一p型半導體基板1)，在添加硼且具有一範圍從20Ωcm至30Ωcm電阻率雜質濃度之半導體基板之一預定區域中，當第二傳導性型埋入層2例如為一濃度範圍從大約1×1018 原子/cm3 至大約1×1021 原子/cm3 之n型埋入層時，第二傳導性型埋入層2係使用雜質(例如砷、磷、或銻)而形成。請注意，當第二傳導性型埋入層2例如為一n型埋入層時，可以使用像是硼之雜質。隨後，第一傳導性型磊晶生長層3形成於半導體基板1及埋入層2上，以便將埋入層2夾置於其間。磊晶生長層3具有一範圍從例如數微米至數十微米之厚度。在磊晶生長層3之一表面上，其藉由一矽局部氧化(LOCOS)法而形成一LOCOS氧化物膜4。
其次，如圖2B中所示，磊晶生長層3係製成圖案，以利用一遮罩5作溝渠蝕刻。例如，遮罩5可以是一具有一厚度範圍從數十奈米至數百奈米之熱氧化物膜及一具有一厚度範圍從數百奈米至一微米之沈積氧化物膜二者中之任一者，或者，其可以是熱氧化物膜及沈積氧化物膜之一疊層式結構。再者，遮罩5可以是一抗蝕膜或一氮化物膜。溝渠6係利用圖案化之遮罩5而形成。在此例子中，溝渠6係形成用於和埋入層2接觸。隨後，將遮罩5去除及接著，如圖2C中所示，形成閘極絕緣膜7，其例如為一具有一厚度範圍從數百至數千埃()之熱氧化物膜。再者，在第二傳導性型埋入層2具有一大約中至高濃度之例子中，熱氧化物膜係在第二傳導性型埋入層2之一表面上變厚。據此，閘極絕緣膜7與第二傳導性型埋入層2之間之一電容可以自動減小。
其次，如圖2D中所示，一多晶矽閘極膜較佳以一範圍從100奈米至500奈米之厚度形成，且雜質係藉由預先沈積或離子植入法導入，藉此取得閘極電極8。在此，可以採用第一傳導性型或第二傳導性型。閘極電極8使用一抗蝕膜9以製成圖案，藉此完成如圖2E中所示一具有溝渠6之電晶體結構。接著，如圖2E中所示，雜質被植入以便藉由一自動對準法而形成一源極區及一汲極區。在此例子中，一自動對準法係與本發明之本質無關。由於雜質植入源極區及汲極區，在傳導性型為n型之例子中，所實施之離子植入中砷或磷較佳以一範圍從1×1015 原子/cm2 至大約1×1016 原子/cm2 劑量植入。另方面，在傳導性型為p型之例子中，所實施之離子植入中硼或二氟化硼較佳以一範圍從1×1015 原子/cm2 至大約1×1016 原子/cm2 劑量植入。在此，當製造另一個在同一晶片內並無溝渠6之MOS電晶體時，對於源極區及汲極區之雜質植入可以在相同條件下同時實施。隨後，如圖2F中所示，生成物以一範圍從800℃至1,000℃溫度進行數小時之熱處理，藉此形成高濃度源極擴散層9及高濃度汲極擴散層10。如上所述，具有第二傳導性型埋入層2及溝渠6之MOS電晶體即告製成。
圖3A係概略圖，其說明根據本發明第二實施例之一半導體裝置。同樣如本發明之第一實施例中所述，溝渠6與第二傳導性型埋入層2之間之一位置關係被適當地設定，以致使溝渠6之一側表面之一端部G係位於第二傳導性型埋入層2之一側表面之一端部F朝內處。惟，在從高濃度源極擴散層9之一下端部及高濃度汲極擴散層10之一下端部各者到第二傳導性型埋入層2之一距離H係一等於或小於一閘極長度L’之長度的例子中，一電流優先流過一定位於溝渠6底部處之電流路徑。據此，即使是當溝渠6之側表面之端部G定位於第二傳導性型埋入層2之側表面之端部F朝外處時，只要能滿足從高濃度源極擴散層9下端部及高濃度汲極擴散層10下端部各者到第二傳導性型埋入層2之側表面之端部F之距離H係一等於或小於閘極長度L’的長度條件，一電流亦流過溝渠6之底部，且驅動性能因而增強。
圖3B說明一模式，其中溝渠6之長度及第二傳導性型埋入層2之長度係設定相等於彼此，且溝渠6之側表面之端部G及第二傳導性型埋入層2之側表面之端部F係在同一直線上對準。同樣在此例子中，只要能滿足從高濃度源極擴散層9下端部及高濃度汲極擴散層10下端部各者到第二傳導性型埋入層2之距離H係一等於或小於閘極長度L’的長度條件，一電流亦流過溝渠6之底部，且驅動性能因而增強。
如上所述，當埋入層被提供於溝渠之底部上，且埋入層與高濃度源極擴散層及高濃度汲極擴散層各者之間之距離被設定於一等於或小於閘極長度的長度時，一電流即流入溝渠之底部，且驅動性能因而增強。
1．．．半導體基板
2．．．埋入層
3．．．磊晶生長層
4．．．LOCOS氧化物膜
5．．．遮罩
6、13．．．溝渠
7．．．閘極絕緣膜
8、15．．．閘極電極
9、16．．．高濃度源極擴散層/抗蝕膜
10、17．．．高濃度汲極擴散層
A、B、C、D、E．．．電流路徑
F．．．端部
G．．．端部
H．．．距離
L、L’．．．閘極長度
在附圖中：圖1A至1C係概略平面圖及概略截面圖，其說明根據本發明第一實施例之一半導體裝置；圖2A至2F係用於製造本發明第一實施例之半導體裝置的流程圖；圖3A及3B係概略截面圖，其說明根據本發明第二實施例之一半導體裝置；及圖4A至4D係概略圖，其說明一習知半導體裝置。
2．．．埋入層
3．．．磊晶生長層
4．．．LOCOS氧化物膜
6．．．溝渠
7．．．閘極絕緣膜
8．．．閘極電極
9．．．高濃度源極據散層/抗蝕膜
10．．．高濃度汲極擴散層
A、B、D、E．．．電流路徑
L．．．閘極長度

Claims (7)

  1. 一種半導體裝置，其包含：一第一傳導性型半導體基板；一第二傳導性型埋入層，其形成於該第一傳導性型半導體基板上之一預定區域中；一第一傳導性型磊晶生長層，其形成於該第二傳導性型埋入層及該第一傳導性型半導體基板上；複數個溝渠，其形成於該第一傳導性型磊晶生長層中且在一待形成電晶體之一閘極寬度方向中呈並列配置，及其具有一底部且到達該第二傳導性型埋入層；一閘極電極，其形成於各該溝渠內側，且藉由一閘極絕緣膜而形成於各該溝渠之一頂表面上及與各該溝渠相鄰之該第一傳導性型磊晶生長層之一表面上；一第二傳導性型高濃度源極擴散層，其形成於該閘極電極之一側面上；及一第二傳導性型高濃度汲極擴散層，其形成於該閘極電極之另一側面上。
  2. 如申請專利範圍第1項之半導體裝置，其中各該溝渠具有一深度，其長度等於或較短於該待形成電晶體之一閘極長度。
  3. 如申請專利範圍第2項之半導體裝置，其中各該溝渠定位於該第二傳導性型埋入層之一側表面一端的內側。
  4. 如申請專利範圍第2項之半導體裝置，其中各該溝渠具有一側表面之一端，其定位在與該第二傳導性型埋入層之一側表面一端相同的平面上。
  5. 如申請專利範圍第2項之半導體裝置，其中各該溝渠定位於該第二傳導性型埋入層之一側表面一端的外側，在一例子中，從該第二傳導性型高濃度源極擴散層之一下端部及該第二傳導性型高濃度汲極擴散層之一下端部其中一者到該第二傳導性型埋入層的一距離係較短於該待形成電晶體之該閘極長度。
  6. 如申請專利範圍第1至5項中任一項之半導體裝置，其中該第二傳導性型埋入層具有一範圍從大約1×1018 原子/cm3 至大約1×1021 原子/cm3 濃度。
  7. 一種製造半導體裝置之方法，其包含：形成一第二傳導性型埋入層於一第一傳導性型半導體基板上之一預定區域中；形成一第一傳導性型磊晶生長層於該第二傳導性型埋入層及該第一傳導性型半導體基板上；形成複數個溝渠於該第一傳導性型磊晶生長層中，且在一待形成電晶體之一閘極寬度方向中呈並列配置，使得各該溝渠之一底部到達該第二傳導性型埋入層；形成一閘極絕緣膜；形成一閘極電極於各該溝渠內側，且藉由該閘極絕緣膜而形成於各該溝渠之一頂表面上及與各該溝渠相鄰之該第一傳導性型磊晶生長層之一表面上；及形成一第二傳導性型高濃度源極擴散層於該閘極電極之一側面上，及形成一第二傳導性型高濃度汲極擴散層於該閘極電極之另一側面上。
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